arch/mips/include/asm/irq.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle
   7  * Copyright (C) 1995, 96, 97, 98, 99, 2000, 01, 02, 03 by Ralf Baechle
   8  */
   9 #ifndef _ASM_IRQ_H
  10 #define _ASM_IRQ_H
  11
  12 #include <linux/linkage.h>
  13 #include <linux/smp.h>
  14
  15 #include <asm/mipsmtregs.h>
  16
  17 #include <irq.h>
  18
  19 static inline void irq_dispose_mapping(unsigned int virq)
  20 {
  21         return;
  22 }
  23
  24 #ifdef CONFIG_I8259
  25 static inline int irq_canonicalize(int irq)
  26 {
  27         return ((irq == I8259A_IRQ_BASE + 2) ? I8259A_IRQ_BASE + 9 : irq);
  28 }
  29 #else
  30 #define irq_canonicalize(irq) (irq)     /* Sane hardware, sane code ... */
  31 #endif
  32
  33 #ifdef CONFIG_MIPS_MT_SMTC
  34
  35 struct irqaction;
  36
  37 extern unsigned long irq_hwmask[];
  38 extern int setup_irq_smtc(unsigned int irq, struct irqaction * new,
  39                           unsigned long hwmask);
  40
  41 static inline void smtc_im_ack_irq(unsigned int irq)
  42 {
  43         if (irq_hwmask[irq] & ST0_IM)
  44                 set_c0_status(irq_hwmask[irq] & ST0_IM);
  45 }
  46
  47 #else
  48
  49 static inline void smtc_im_ack_irq(unsigned int irq)
  50 {
  51 }
  52
  53 #endif /* CONFIG_MIPS_MT_SMTC */
  54
  55 #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
  56 #include <linux/cpumask.h>
  57
  58 extern int plat_set_irq_affinity(unsigned int irq,
  59                                   const struct cpumask *affinity);
  60 extern void smtc_forward_irq(unsigned int irq);
  61
  62 /*
  63  * IRQ affinity hook invoked at the beginning of interrupt dispatch
  64  * if option is enabled.
  65  *
  66  * Up through Linux 2.6.22 (at least) cpumask operations are very
  67  * inefficient on MIPS.  Initial prototypes of SMTC IRQ affinity
  68  * used a "fast path" per-IRQ-descriptor cache of affinity information
  69  * to reduce latency.  As there is a project afoot to optimize the
  70  * cpumask implementations, this version is optimistically assuming
  71  * that cpumask.h macro overhead is reasonable during interrupt dispatch.
  72  */
  73 #define IRQ_AFFINITY_HOOK(irq)                                          \
  74 do {                                                                    \
  75     if (!cpumask_test_cpu(smp_processor_id(), irq_desc[irq].affinity)) {\
  76         smtc_forward_irq(irq);                                          \
  77         irq_exit();                                                     \
  78         return;                                                         \
  79     }                                                                   \
  80 } while (0)
  81
  82 #else /* Not doing SMTC affinity */
  83
  84 #define IRQ_AFFINITY_HOOK(irq) do { } while (0)
  85
  86 #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
  87
  88 #ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP
  89
  90 /*
  91  * Clear interrupt mask handling "backstop" if irq_hwmask
  92  * entry so indicates. This implies that the ack() or end()
  93  * functions will take over re-enabling the low-level mask.
  94  * Otherwise it will be done on return from exception.
  95  */
  96 #define __DO_IRQ_SMTC_HOOK(irq)                                         \
  97 do {                                                                    \
  98         IRQ_AFFINITY_HOOK(irq);                                         \
  99         if (irq_hwmask[irq] & 0x0000ff00)                               \
 100                 write_c0_tccontext(read_c0_tccontext() &                \
 101                                    ~(irq_hwmask[irq] & 0x0000ff00));    \
 102 } while (0)
 103
 104 #define __NO_AFFINITY_IRQ_SMTC_HOOK(irq)                                \
 105 do {                                                                    \
 106         if (irq_hwmask[irq] & 0x0000ff00)                               \
 107                 write_c0_tccontext(read_c0_tccontext() &                \
 108                                    ~(irq_hwmask[irq] & 0x0000ff00));    \
 109 } while (0)
 110
 111 #else
 112
 113 #define __DO_IRQ_SMTC_HOOK(irq)                                         \
 114 do {                                                                    \
 115         IRQ_AFFINITY_HOOK(irq);                                         \
 116 } while (0)
 117 #define __NO_AFFINITY_IRQ_SMTC_HOOK(irq) do { } while (0)
 118
 119 #endif
 120
 121 extern void do_IRQ(unsigned int irq);
 122
 123 #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
 124
 125 extern void do_IRQ_no_affinity(unsigned int irq);
 126
 127 #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
 128
 129 extern void arch_init_irq(void);
 130 extern void spurious_interrupt(void);
 131
 132 extern int allocate_irqno(void);
 133 extern void alloc_legacy_irqno(void);
 134 extern void free_irqno(unsigned int irq);
 135
 136 /*
 137  * Before R2 the timer and performance counter interrupts were both fixed to
 138  * IE7.  Since R2 their number has to be read from the c0_intctl register.
 139  */
 140 #define CP0_LEGACY_COMPARE_IRQ 7
 141
 142 extern int cp0_compare_irq;
 143 extern int cp0_compare_irq_shift;
 144 extern int cp0_perfcount_irq;
 145
 146 #endif /* _ASM_IRQ_H */