2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle
7 * Copyright (C) 1995, 96, 97, 98, 99, 2000, 01, 02, 03 by Ralf Baechle
12 #include <linux/linkage.h>
13 #include <linux/smp.h>
15 #include <asm/mipsmtregs.h>
19 static inline void irq_dispose_mapping(unsigned int virq)
25 static inline int irq_canonicalize(int irq)
27 return ((irq == I8259A_IRQ_BASE + 2) ? I8259A_IRQ_BASE + 9 : irq);
30 #define irq_canonicalize(irq) (irq) /* Sane hardware, sane code ... */
33 #ifdef CONFIG_MIPS_MT_SMTC
37 extern unsigned long irq_hwmask[];
38 extern int setup_irq_smtc(unsigned int irq, struct irqaction * new,
39 unsigned long hwmask);
41 static inline void smtc_im_ack_irq(unsigned int irq)
43 if (irq_hwmask[irq] & ST0_IM)
44 set_c0_status(irq_hwmask[irq] & ST0_IM);
49 static inline void smtc_im_ack_irq(unsigned int irq)
53 #endif /* CONFIG_MIPS_MT_SMTC */
55 #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
56 #include <linux/cpumask.h>
58 extern int plat_set_irq_affinity(unsigned int irq,
59 const struct cpumask *affinity);
60 extern void smtc_forward_irq(unsigned int irq);
63 * IRQ affinity hook invoked at the beginning of interrupt dispatch
64 * if option is enabled.
66 * Up through Linux 2.6.22 (at least) cpumask operations are very
67 * inefficient on MIPS. Initial prototypes of SMTC IRQ affinity
68 * used a "fast path" per-IRQ-descriptor cache of affinity information
69 * to reduce latency. As there is a project afoot to optimize the
70 * cpumask implementations, this version is optimistically assuming
71 * that cpumask.h macro overhead is reasonable during interrupt dispatch.
73 #define IRQ_AFFINITY_HOOK(irq) \
75 if (!cpumask_test_cpu(smp_processor_id(), irq_desc[irq].affinity)) {\
76 smtc_forward_irq(irq); \
82 #else /* Not doing SMTC affinity */
84 #define IRQ_AFFINITY_HOOK(irq) do { } while (0)
86 #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
88 #ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP
91 * Clear interrupt mask handling "backstop" if irq_hwmask
92 * entry so indicates. This implies that the ack() or end()
93 * functions will take over re-enabling the low-level mask.
94 * Otherwise it will be done on return from exception.
96 #define __DO_IRQ_SMTC_HOOK(irq) \
98 IRQ_AFFINITY_HOOK(irq); \
99 if (irq_hwmask[irq] & 0x0000ff00) \
100 write_c0_tccontext(read_c0_tccontext() & \
101 ~(irq_hwmask[irq] & 0x0000ff00)); \
104 #define __NO_AFFINITY_IRQ_SMTC_HOOK(irq) \
106 if (irq_hwmask[irq] & 0x0000ff00) \
107 write_c0_tccontext(read_c0_tccontext() & \
108 ~(irq_hwmask[irq] & 0x0000ff00)); \
113 #define __DO_IRQ_SMTC_HOOK(irq) \
115 IRQ_AFFINITY_HOOK(irq); \
117 #define __NO_AFFINITY_IRQ_SMTC_HOOK(irq) do { } while (0)
121 extern void do_IRQ(unsigned int irq);
123 #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
125 extern void do_IRQ_no_affinity(unsigned int irq);
127 #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
129 extern void arch_init_irq(void);
130 extern void spurious_interrupt(void);
132 extern int allocate_irqno(void);
133 extern void alloc_legacy_irqno(void);
134 extern void free_irqno(unsigned int irq);
137 * Before R2 the timer and performance counter interrupts were both fixed to
138 * IE7. Since R2 their number has to be read from the c0_intctl register.
140 #define CP0_LEGACY_COMPARE_IRQ 7
142 extern int cp0_compare_irq;
143 extern int cp0_compare_irq_shift;
144 extern int cp0_perfcount_irq;
146 #endif /* _ASM_IRQ_H */