arch/mips/cobalt/setup.c

   1 /*
   2  * Setup pointers to hardware dependent routines.
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 1996, 1997, 2004, 05 by Ralf Baechle (ralf@linux-mips.org)
   9  * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv)
  10  *
  11  */
  12 #include <linux/interrupt.h>
  13 #include <linux/pci.h>
  14 #include <linux/init.h>
  15 #include <linux/pm.h>
  16 #include <linux/serial.h>
  17 #include <linux/serial_core.h>
  18
  19 #include <asm/bootinfo.h>
  20 #include <asm/time.h>
  21 #include <asm/io.h>
  22 #include <asm/reboot.h>
  23 #include <asm/gt64120.h>
  24
  25 #include <cobalt.h>
  26
  27 extern void cobalt_machine_restart(char *command);
  28 extern void cobalt_machine_halt(void);
  29 extern void cobalt_machine_power_off(void);
  30 extern void cobalt_early_console(void);
  31
  32 int cobalt_board_id;
  33
  34 const char *get_system_type(void)
  35 {
  36         switch (cobalt_board_id) {
  37                 case COBALT_BRD_ID_QUBE1:
  38                         return "Cobalt Qube";
  39                 case COBALT_BRD_ID_RAQ1:
  40                         return "Cobalt RaQ";
  41                 case COBALT_BRD_ID_QUBE2:
  42                         return "Cobalt Qube2";
  43                 case COBALT_BRD_ID_RAQ2:
  44                         return "Cobalt RaQ2";
  45         }
  46         return "MIPS Cobalt";
  47 }
  48
  49 void __init plat_timer_setup(struct irqaction *irq)
  50 {
  51         /* Load timer value for HZ (TCLK is 50MHz) */
  52         GT_WRITE(GT_TC0_OFS, 50*1000*1000 / HZ);
  53
  54         /* Enable timer */
  55         GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);
  56
  57         /* Register interrupt */
  58         setup_irq(COBALT_GALILEO_IRQ, irq);
  59
  60         /* Enable interrupt */
  61         GT_WRITE(GT_INTRMASK_OFS, GT_INTR_T0EXP_MSK | GT_READ(GT_INTRMASK_OFS));
  62 }
  63
  64 /*
  65  * Cobalt doesn't have PS/2 keyboard/mouse interfaces,
  66  * keyboard conntroller is never used.
  67  * Also PCI-ISA bridge DMA contoroller is never used.
  68  */
  69 static struct resource cobalt_reserved_resources[] = {
  70         {       /* dma1 */
  71                 .start  = 0x00,
  72                 .end    = 0x1f,
  73                 .name   = "reserved",
  74                 .flags  = IORESOURCE_BUSY | IORESOURCE_IO,
  75         },
  76         {       /* keyboard */
  77                 .start  = 0x60,
  78                 .end    = 0x6f,
  79                 .name   = "reserved",
  80                 .flags  = IORESOURCE_BUSY | IORESOURCE_IO,
  81         },
  82         {       /* dma page reg */
  83                 .start  = 0x80,
  84                 .end    = 0x8f,
  85                 .name   = "reserved",
  86                 .flags  = IORESOURCE_BUSY | IORESOURCE_IO,
  87         },
  88         {       /* dma2 */
  89                 .start  = 0xc0,
  90                 .end    = 0xdf,
  91                 .name   = "reserved",
  92                 .flags  = IORESOURCE_BUSY | IORESOURCE_IO,
  93         },
  94 };
  95
  96 void __init plat_mem_setup(void)
  97 {
  98         static struct uart_port uart;
  99         unsigned int devfn = PCI_DEVFN(COBALT_PCICONF_VIA, 0);
 100         int i;
 101
 102         _machine_restart = cobalt_machine_restart;
 103         _machine_halt = cobalt_machine_halt;
 104         pm_power_off = cobalt_machine_power_off;
 105
 106         set_io_port_base(CKSEG1ADDR(GT_DEF_PCI0_IO_BASE));
 107
 108         /* I/O port resource must include LCD/buttons */
 109         ioport_resource.end = 0x0fffffff;
 110
 111         /* These resources have been reserved by VIA SuperI/O chip. */
 112         for (i = 0; i < ARRAY_SIZE(cobalt_reserved_resources); i++)
 113                 request_resource(&ioport_resource, cobalt_reserved_resources + i);
 114
 115         /* Read the cobalt id register out of the PCI config space */
 116         PCI_CFG_SET(devfn, (VIA_COBALT_BRD_ID_REG & ~0x3));
 117         cobalt_board_id = GT_READ(GT_PCI0_CFGDATA_OFS);
 118         cobalt_board_id >>= ((VIA_COBALT_BRD_ID_REG & 3) * 8);
 119         cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(cobalt_board_id);
 120
 121         printk("Cobalt board ID: %d\n", cobalt_board_id);
 122
 123         if (cobalt_board_id > COBALT_BRD_ID_RAQ1) {
 124 #ifdef CONFIG_SERIAL_8250
 125                 uart.line       = 0;
 126                 uart.type       = PORT_UNKNOWN;
 127                 uart.uartclk    = 18432000;
 128                 uart.irq        = COBALT_SERIAL_IRQ;
 129                 uart.flags      = UPF_IOREMAP | UPF_BOOT_AUTOCONF |
 130                                   UPF_SKIP_TEST;
 131                 uart.iotype     = UPIO_MEM;
 132                 uart.mapbase    = 0x1c800000;
 133
 134                 early_serial_setup(&uart);
 135 #endif
 136         }
 137 }
 138
 139 /*
 140  * Prom init. We read our one and only communication with the firmware.
 141  * Grab the amount of installed memory.
 142  * Better boot loaders (CoLo) pass a command line too :-)
 143  */
 144
 145 void __init prom_init(void)
 146 {
 147         int narg, indx, posn, nchr;
 148         unsigned long memsz;
 149         char **argv;
 150
 151         mips_machgroup = MACH_GROUP_COBALT;
 152
 153         memsz = fw_arg0 & 0x7fff0000;
 154         narg = fw_arg0 & 0x0000ffff;
 155
 156         if (narg) {
 157                 arcs_cmdline[0] = '\0';
 158                 argv = (char **) fw_arg1;
 159                 posn = 0;
 160                 for (indx = 1; indx < narg; ++indx) {
 161                         nchr = strlen(argv[indx]);
 162                         if (posn + 1 + nchr + 1 > sizeof(arcs_cmdline))
 163                                 break;
 164                         if (posn)
 165                                 arcs_cmdline[posn++] = ' ';
 166                         strcpy(arcs_cmdline + posn, argv[indx]);
 167                         posn += nchr;
 168                 }
 169         }
 170
 171         add_memory_region(0x0, memsz, BOOT_MEM_RAM);
 172 }
 173
 174 void __init prom_free_prom_memory(void)
 175 {
 176         /* Nothing to do! */
 177 }