arch/mips/ath79/irq.c

   1 /*
   2  *  Atheros AR71xx/AR724x/AR913x specific interrupt handling
   3  *
   4  *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Parts of this file are based on Atheros' 2.6.15 BSP
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/irq.h>
  18
  19 #include <asm/irq_cpu.h>
  20 #include <asm/mipsregs.h>
  21
  22 #include <asm/mach-ath79/ath79.h>
  23 #include <asm/mach-ath79/ar71xx_regs.h>
  24 #include "common.h"
  25
  26 static unsigned int ath79_ip2_flush_reg;
  27 static unsigned int ath79_ip3_flush_reg;
  28
  29 static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
  30 {
  31         void __iomem *base = ath79_reset_base;
  32         u32 pending;
  33
  34         pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) &
  35                   __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
  36
  37         if (pending & MISC_INT_UART)
  38                 generic_handle_irq(ATH79_MISC_IRQ_UART);
  39
  40         else if (pending & MISC_INT_DMA)
  41                 generic_handle_irq(ATH79_MISC_IRQ_DMA);
  42
  43         else if (pending & MISC_INT_PERFC)
  44                 generic_handle_irq(ATH79_MISC_IRQ_PERFC);
  45
  46         else if (pending & MISC_INT_TIMER)
  47                 generic_handle_irq(ATH79_MISC_IRQ_TIMER);
  48
  49         else if (pending & MISC_INT_OHCI)
  50                 generic_handle_irq(ATH79_MISC_IRQ_OHCI);
  51
  52         else if (pending & MISC_INT_ERROR)
  53                 generic_handle_irq(ATH79_MISC_IRQ_ERROR);
  54
  55         else if (pending & MISC_INT_GPIO)
  56                 generic_handle_irq(ATH79_MISC_IRQ_GPIO);
  57
  58         else if (pending & MISC_INT_WDOG)
  59                 generic_handle_irq(ATH79_MISC_IRQ_WDOG);
  60
  61         else
  62                 spurious_interrupt();
  63 }
  64
  65 static void ar71xx_misc_irq_unmask(unsigned int irq)
  66 {
  67         void __iomem *base = ath79_reset_base;
  68         u32 t;
  69
  70         irq -= ATH79_MISC_IRQ_BASE;
  71
  72         t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
  73         __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
  74
  75         /* flush write */
  76         __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
  77 }
  78
  79 static void ar71xx_misc_irq_mask(unsigned int irq)
  80 {
  81         void __iomem *base = ath79_reset_base;
  82         u32 t;
  83
  84         irq -= ATH79_MISC_IRQ_BASE;
  85
  86         t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
  87         __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
  88
  89         /* flush write */
  90         __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
  91 }
  92
  93 static void ar724x_misc_irq_ack(unsigned int irq)
  94 {
  95         void __iomem *base = ath79_reset_base;
  96         u32 t;
  97
  98         irq -= ATH79_MISC_IRQ_BASE;
  99
 100         t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
 101         __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_STATUS);
 102
 103         /* flush write */
 104         __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
 105 }
 106
 107 static struct irq_chip ath79_misc_irq_chip = {
 108         .name           = "MISC",
 109         .unmask         = ar71xx_misc_irq_unmask,
 110         .mask           = ar71xx_misc_irq_mask,
 111 };
 112
 113 static void __init ath79_misc_irq_init(void)
 114 {
 115         void __iomem *base = ath79_reset_base;
 116         int i;
 117
 118         __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);
 119         __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);
 120
 121         if (soc_is_ar71xx() || soc_is_ar913x())
 122                 ath79_misc_irq_chip.mask_ack = ar71xx_misc_irq_mask;
 123         else if (soc_is_ar724x())
 124                 ath79_misc_irq_chip.ack = ar724x_misc_irq_ack;
 125         else
 126                 BUG();
 127
 128         for (i = ATH79_MISC_IRQ_BASE;
 129              i < ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT; i++) {
 130                 irq_desc[i].status = IRQ_DISABLED;
 131                 set_irq_chip_and_handler(i, &ath79_misc_irq_chip,
 132                                          handle_level_irq);
 133         }
 134
 135         set_irq_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler);
 136 }
 137
 138 asmlinkage void plat_irq_dispatch(void)
 139 {
 140         unsigned long pending;
 141
 142         pending = read_c0_status() & read_c0_cause() & ST0_IM;
 143
 144         if (pending & STATUSF_IP7)
 145                 do_IRQ(ATH79_CPU_IRQ_TIMER);
 146
 147         else if (pending & STATUSF_IP2) {
 148                 ath79_ddr_wb_flush(ath79_ip2_flush_reg);
 149                 do_IRQ(ATH79_CPU_IRQ_IP2);
 150         }
 151
 152         else if (pending & STATUSF_IP4)
 153                 do_IRQ(ATH79_CPU_IRQ_GE0);
 154
 155         else if (pending & STATUSF_IP5)
 156                 do_IRQ(ATH79_CPU_IRQ_GE1);
 157
 158         else if (pending & STATUSF_IP3) {
 159                 ath79_ddr_wb_flush(ath79_ip3_flush_reg);
 160                 do_IRQ(ATH79_CPU_IRQ_USB);
 161         }
 162
 163         else if (pending & STATUSF_IP6)
 164                 do_IRQ(ATH79_CPU_IRQ_MISC);
 165
 166         else
 167                 spurious_interrupt();
 168 }
 169
 170 void __init arch_init_irq(void)
 171 {
 172         if (soc_is_ar71xx()) {
 173                 ath79_ip2_flush_reg = AR71XX_DDR_REG_FLUSH_PCI;
 174                 ath79_ip3_flush_reg = AR71XX_DDR_REG_FLUSH_USB;
 175         } else if (soc_is_ar724x()) {
 176                 ath79_ip2_flush_reg = AR724X_DDR_REG_FLUSH_PCIE;
 177                 ath79_ip3_flush_reg = AR724X_DDR_REG_FLUSH_USB;
 178         } else if (soc_is_ar913x()) {
 179                 ath79_ip2_flush_reg = AR913X_DDR_REG_FLUSH_WMAC;
 180                 ath79_ip3_flush_reg = AR913X_DDR_REG_FLUSH_USB;
 181         } else
 182                 BUG();
 183
 184         cp0_perfcount_irq = ATH79_MISC_IRQ_PERFC;
 185         mips_cpu_irq_init();
 186         ath79_misc_irq_init();
 187 }