1 #ifndef _ASM_MICROBLAZE_PCI_BRIDGE_H
2 #define _ASM_MICROBLAZE_PCI_BRIDGE_H
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
10 #include <linux/pci.h>
11 #include <linux/list.h>
12 #include <linux/ioport.h>
17 /* Force re-assigning all resources (ignore firmware
20 PCI_REASSIGN_ALL_RSRC = 0x00000001,
22 /* Do not try to assign, just use existing setup */
23 PCI_PROBE_ONLY = 0x00000004,
25 /* Don't bother with ISA alignment unless the bridge has
26 * ISA forwarding enabled
28 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008,
30 /* Enable domain numbers in /proc */
31 PCI_ENABLE_PROC_DOMAINS = 0x00000010,
32 /* ... except for domain 0 */
33 PCI_COMPAT_DOMAIN_0 = 0x00000020,
37 * Structure of a PCI controller (host bridge)
39 struct pci_controller {
42 struct device_node *dn;
43 struct list_head list_node;
44 struct device *parent;
51 void __iomem *io_base_virt;
52 resource_size_t io_base_phys;
54 resource_size_t pci_io_size;
56 /* Some machines (PReP) have a non 1:1 mapping of
57 * the PCI memory space in the CPU bus space
59 resource_size_t pci_mem_offset;
61 /* Some machines have a special region to forward the ISA
62 * "memory" cycles such as VGA memory regions. Left to 0
65 resource_size_t isa_mem_phys;
66 resource_size_t isa_mem_size;
69 unsigned int __iomem *cfg_addr;
70 void __iomem *cfg_data;
73 * Used for variants of PCI indirect handling and possible quirks:
74 * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
75 * EXT_REG - provides access to PCI-e extended registers
76 * SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
77 * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
78 * to determine which bus number to match on when generating type0
80 * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
81 * hanging if we don't have link and try to do config cycles to
82 * anything but the PHB. Only allow talking to the PHB if this is
84 * BIG_ENDIAN - cfg_addr is a big endian register
85 * BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs
86 * on the PLB4. Effectively disable MRM commands by setting this.
88 #define INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
89 #define INDIRECT_TYPE_EXT_REG 0x00000002
90 #define INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004
91 #define INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
92 #define INDIRECT_TYPE_BIG_ENDIAN 0x00000010
93 #define INDIRECT_TYPE_BROKEN_MRM 0x00000020
96 /* Currently, we limit ourselves to 1 IO range and 3 mem
97 * ranges since the common pci_bus structure can't handle more
99 struct resource io_resource;
100 struct resource mem_resources[3];
101 int global_number; /* PCI domain number */
105 static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
110 static inline int isa_vaddr_is_ioport(void __iomem *address)
112 /* No specific ISA handling on ppc32 at this stage, it
113 * all goes through PCI
117 #endif /* CONFIG_PCI */
119 /* These are used for config access before all the PCI probing
121 extern int early_read_config_byte(struct pci_controller *hose, int bus,
122 int dev_fn, int where, u8 *val);
123 extern int early_read_config_word(struct pci_controller *hose, int bus,
124 int dev_fn, int where, u16 *val);
125 extern int early_read_config_dword(struct pci_controller *hose, int bus,
126 int dev_fn, int where, u32 *val);
127 extern int early_write_config_byte(struct pci_controller *hose, int bus,
128 int dev_fn, int where, u8 val);
129 extern int early_write_config_word(struct pci_controller *hose, int bus,
130 int dev_fn, int where, u16 val);
131 extern int early_write_config_dword(struct pci_controller *hose, int bus,
132 int dev_fn, int where, u32 val);
134 extern int early_find_capability(struct pci_controller *hose, int bus,
135 int dev_fn, int cap);
137 extern void setup_indirect_pci(struct pci_controller *hose,
138 resource_size_t cfg_addr,
139 resource_size_t cfg_data, u32 flags);
141 /* Get the PCI host controller for an OF device */
142 extern struct pci_controller *pci_find_hose_for_OF_device(
143 struct device_node *node);
145 /* Fill up host controller resources from the OF node */
146 extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
147 struct device_node *dev, int primary);
149 /* Allocate & free a PCI host bridge structure */
150 extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
151 extern void pcibios_free_controller(struct pci_controller *phb);
152 extern void pcibios_setup_phb_resources(struct pci_controller *hose);
155 extern unsigned int pci_flags;
157 static inline void pci_set_flags(int flags)
162 static inline void pci_add_flags(int flags)
167 static inline int pci_has_flag(int flag)
169 return pci_flags & flag;
172 extern struct list_head hose_list;
174 extern int pcibios_vaddr_is_ioport(void __iomem *address);
176 static inline int pcibios_vaddr_is_ioport(void __iomem *address)
181 static inline void pci_set_flags(int flags) { }
182 static inline void pci_add_flags(int flags) { }
183 static inline int pci_has_flag(int flag)
187 #endif /* CONFIG_PCI */
189 #endif /* __KERNEL__ */
190 #endif /* _ASM_MICROBLAZE_PCI_BRIDGE_H */