arch/m32r/platforms/oaks32r/setup.c

   1 /*
   2  *  linux/arch/m32r/platforms/oaks32r/setup.c
   3  *
   4  *  Setup routines for OAKS32R Board
   5  *
   6  *  Copyright (c) 2002-2005  Hiroyuki Kondo, Hirokazu Takata,
   7  *                           Hitoshi Yamamoto, Mamoru Sakugawa
   8  */
   9
  10 #include <linux/irq.h>
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13
  14 #include <asm/system.h>
  15 #include <asm/m32r.h>
  16 #include <asm/io.h>
  17
  18 #define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
  19
  20 icu_data_t icu_data[NR_IRQS];
  21
  22 static void disable_oaks32r_irq(unsigned int irq)
  23 {
  24         unsigned long port, data;
  25
  26         port = irq2port(irq);
  27         data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
  28         outl(data, port);
  29 }
  30
  31 static void enable_oaks32r_irq(unsigned int irq)
  32 {
  33         unsigned long port, data;
  34
  35         port = irq2port(irq);
  36         data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
  37         outl(data, port);
  38 }
  39
  40 static void mask_oaks32r(struct irq_data *data)
  41 {
  42         disable_oaks32r_irq(data->irq);
  43 }
  44
  45 static void unmask_oaks32r(struct irq_data *data)
  46 {
  47         enable_oaks32r_irq(data->irq);
  48 }
  49
  50 static void shutdown_oaks32r(struct irq_data *data)
  51 {
  52         unsigned long port;
  53
  54         port = irq2port(data->irq);
  55         outl(M32R_ICUCR_ILEVEL7, port);
  56 }
  57
  58 static struct irq_chip oaks32r_irq_type =
  59 {
  60         .name           = "OAKS32R-IRQ",
  61         .irq_shutdown   = shutdown_oaks32r,
  62         .irq_mask       = mask_oaks32r,
  63         .irq_unmask     = unmask_oaks32r,
  64 };
  65
  66 void __init init_IRQ(void)
  67 {
  68         static int once = 0;
  69
  70         if (once)
  71                 return;
  72         else
  73                 once++;
  74
  75 #ifdef CONFIG_NE2000
  76         /* INT3 : LAN controller (RTL8019AS) */
  77         set_irq_chip_and_handler(M32R_IRQ_INT3, &oaks32r_irq_type,
  78                                  handle_level_irq);
  79         icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
  80         disable_oaks32r_irq(M32R_IRQ_INT3);
  81 #endif /* CONFIG_M32R_NE2000 */
  82
  83         /* MFT2 : system timer */
  84         set_irq_chip_and_handler(M32R_IRQ_MFT2, &oaks32r_irq_type,
  85                                  handle_level_irq);
  86         icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
  87         disable_oaks32r_irq(M32R_IRQ_MFT2);
  88
  89 #ifdef CONFIG_SERIAL_M32R_SIO
  90         /* SIO0_R : uart receive data */
  91         set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &oaks32r_irq_type,
  92                                  handle_level_irq);
  93         icu_data[M32R_IRQ_SIO0_R].icucr = 0;
  94         disable_oaks32r_irq(M32R_IRQ_SIO0_R);
  95
  96         /* SIO0_S : uart send data */
  97         set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &oaks32r_irq_type,
  98                                  handle_level_irq);
  99         icu_data[M32R_IRQ_SIO0_S].icucr = 0;
 100         disable_oaks32r_irq(M32R_IRQ_SIO0_S);
 101
 102         /* SIO1_R : uart receive data */
 103         set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &oaks32r_irq_type,
 104                                  handle_level_irq);
 105         icu_data[M32R_IRQ_SIO1_R].icucr = 0;
 106         disable_oaks32r_irq(M32R_IRQ_SIO1_R);
 107
 108         /* SIO1_S : uart send data */
 109         set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &oaks32r_irq_type,
 110                                  handle_level_irq);
 111         icu_data[M32R_IRQ_SIO1_S].icucr = 0;
 112         disable_oaks32r_irq(M32R_IRQ_SIO1_S);
 113 #endif /* CONFIG_SERIAL_M32R_SIO */
 114 }