arch/m32r/kernel/setup_mappi2.c

   1 /*
   2  *  linux/arch/m32r/kernel/setup_mappi2.c
   3  *
   4  *  Setup routines for Renesas MAPPI-II(M3A-ZA36) Board
   5  *
   6  *  Copyright (c) 2001-2005  Hiroyuki Kondo, Hirokazu Takata,
   7  *                           Hitoshi Yamamoto, Mamoru Sakugawa
   8  */
   9
  10 #include <linux/config.h>
  11 #include <linux/irq.h>
  12 #include <linux/kernel.h>
  13 #include <linux/init.h>
  14 #include <linux/platform_device.h>
  15
  16 #include <asm/system.h>
  17 #include <asm/m32r.h>
  18 #include <asm/io.h>
  19
  20 #define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
  21
  22 icu_data_t icu_data[NR_IRQS];
  23
  24 static void disable_mappi2_irq(unsigned int irq)
  25 {
  26         unsigned long port, data;
  27
  28         if ((irq == 0) ||(irq >= NR_IRQS))  {
  29                 printk("bad irq 0x%08x\n", irq);
  30                 return;
  31         }
  32         port = irq2port(irq);
  33         data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
  34         outl(data, port);
  35 }
  36
  37 static void enable_mappi2_irq(unsigned int irq)
  38 {
  39         unsigned long port, data;
  40
  41         if ((irq == 0) ||(irq >= NR_IRQS))  {
  42                 printk("bad irq 0x%08x\n", irq);
  43                 return;
  44         }
  45         port = irq2port(irq);
  46         data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
  47         outl(data, port);
  48 }
  49
  50 static void mask_and_ack_mappi2(unsigned int irq)
  51 {
  52         disable_mappi2_irq(irq);
  53 }
  54
  55 static void end_mappi2_irq(unsigned int irq)
  56 {
  57         enable_mappi2_irq(irq);
  58 }
  59
  60 static unsigned int startup_mappi2_irq(unsigned int irq)
  61 {
  62         enable_mappi2_irq(irq);
  63         return (0);
  64 }
  65
  66 static void shutdown_mappi2_irq(unsigned int irq)
  67 {
  68         unsigned long port;
  69
  70         port = irq2port(irq);
  71         outl(M32R_ICUCR_ILEVEL7, port);
  72 }
  73
  74 static struct hw_interrupt_type mappi2_irq_type =
  75 {
  76         .typename = "MAPPI2-IRQ",
  77         .startup = startup_mappi2_irq,
  78         .shutdown = shutdown_mappi2_irq,
  79         .enable = enable_mappi2_irq,
  80         .disable = disable_mappi2_irq,
  81         .ack = mask_and_ack_mappi2,
  82         .end = end_mappi2_irq
  83 };
  84
  85 void __init init_IRQ(void)
  86 {
  87 #if defined(CONFIG_SMC91X)
  88         /* INT0 : LAN controller (SMC91111) */
  89         irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED;
  90         irq_desc[M32R_IRQ_INT0].chip = &mappi2_irq_type;
  91         irq_desc[M32R_IRQ_INT0].action = 0;
  92         irq_desc[M32R_IRQ_INT0].depth = 1;
  93         icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
  94         disable_mappi2_irq(M32R_IRQ_INT0);
  95 #endif  /* CONFIG_SMC91X */
  96
  97         /* MFT2 : system timer */
  98         irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
  99         irq_desc[M32R_IRQ_MFT2].chip = &mappi2_irq_type;
 100         irq_desc[M32R_IRQ_MFT2].action = 0;
 101         irq_desc[M32R_IRQ_MFT2].depth = 1;
 102         icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
 103         disable_mappi2_irq(M32R_IRQ_MFT2);
 104
 105 #ifdef CONFIG_SERIAL_M32R_SIO
 106         /* SIO0_R : uart receive data */
 107         irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
 108         irq_desc[M32R_IRQ_SIO0_R].chip = &mappi2_irq_type;
 109         irq_desc[M32R_IRQ_SIO0_R].action = 0;
 110         irq_desc[M32R_IRQ_SIO0_R].depth = 1;
 111         icu_data[M32R_IRQ_SIO0_R].icucr = 0;
 112         disable_mappi2_irq(M32R_IRQ_SIO0_R);
 113
 114         /* SIO0_S : uart send data */
 115         irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
 116         irq_desc[M32R_IRQ_SIO0_S].chip = &mappi2_irq_type;
 117         irq_desc[M32R_IRQ_SIO0_S].action = 0;
 118         irq_desc[M32R_IRQ_SIO0_S].depth = 1;
 119         icu_data[M32R_IRQ_SIO0_S].icucr = 0;
 120         disable_mappi2_irq(M32R_IRQ_SIO0_S);
 121         /* SIO1_R : uart receive data */
 122         irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
 123         irq_desc[M32R_IRQ_SIO1_R].chip = &mappi2_irq_type;
 124         irq_desc[M32R_IRQ_SIO1_R].action = 0;
 125         irq_desc[M32R_IRQ_SIO1_R].depth = 1;
 126         icu_data[M32R_IRQ_SIO1_R].icucr = 0;
 127         disable_mappi2_irq(M32R_IRQ_SIO1_R);
 128
 129         /* SIO1_S : uart send data */
 130         irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
 131         irq_desc[M32R_IRQ_SIO1_S].chip = &mappi2_irq_type;
 132         irq_desc[M32R_IRQ_SIO1_S].action = 0;
 133         irq_desc[M32R_IRQ_SIO1_S].depth = 1;
 134         icu_data[M32R_IRQ_SIO1_S].icucr = 0;
 135         disable_mappi2_irq(M32R_IRQ_SIO1_S);
 136 #endif  /* CONFIG_M32R_USE_DBG_CONSOLE */
 137
 138 #if defined(CONFIG_USB)
 139         /* INT1 : USB Host controller interrupt */
 140         irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED;
 141         irq_desc[M32R_IRQ_INT1].chip = &mappi2_irq_type;
 142         irq_desc[M32R_IRQ_INT1].action = 0;
 143         irq_desc[M32R_IRQ_INT1].depth = 1;
 144         icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01;
 145         disable_mappi2_irq(M32R_IRQ_INT1);
 146 #endif /* CONFIG_USB */
 147
 148         /* ICUCR40: CFC IREQ */
 149         irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED;
 150         irq_desc[PLD_IRQ_CFIREQ].chip = &mappi2_irq_type;
 151         irq_desc[PLD_IRQ_CFIREQ].action = 0;
 152         irq_desc[PLD_IRQ_CFIREQ].depth = 1;     /* disable nested irq */
 153         icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
 154         disable_mappi2_irq(PLD_IRQ_CFIREQ);
 155
 156 #if defined(CONFIG_M32R_CFC)
 157         /* ICUCR41: CFC Insert */
 158         irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED;
 159         irq_desc[PLD_IRQ_CFC_INSERT].chip = &mappi2_irq_type;
 160         irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
 161         irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
 162         icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00;
 163         disable_mappi2_irq(PLD_IRQ_CFC_INSERT);
 164
 165         /* ICUCR42: CFC Eject */
 166         irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED;
 167         irq_desc[PLD_IRQ_CFC_EJECT].chip = &mappi2_irq_type;
 168         irq_desc[PLD_IRQ_CFC_EJECT].action = 0;
 169         irq_desc[PLD_IRQ_CFC_EJECT].depth = 1;  /* disable nested irq */
 170         icu_data[PLD_IRQ_CFC_EJECT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
 171         disable_mappi2_irq(PLD_IRQ_CFC_EJECT);
 172 #endif /* CONFIG_MAPPI2_CFC */
 173 }
 174
 175 #define LAN_IOSTART     0x300
 176 #define LAN_IOEND       0x320
 177 static struct resource smc91x_resources[] = {
 178         [0] = {
 179                 .start  = (LAN_IOSTART),
 180                 .end    = (LAN_IOEND),
 181                 .flags  = IORESOURCE_MEM,
 182         },
 183         [1] = {
 184                 .start  = M32R_IRQ_INT0,
 185                 .end    = M32R_IRQ_INT0,
 186                 .flags  = IORESOURCE_IRQ,
 187         }
 188 };
 189
 190 static struct platform_device smc91x_device = {
 191         .name           = "smc91x",
 192         .id             = 0,
 193         .num_resources  = ARRAY_SIZE(smc91x_resources),
 194         .resource       = smc91x_resources,
 195 };
 196
 197 static int __init platform_init(void)
 198 {
 199         platform_device_register(&smc91x_device);
 200         return 0;
 201 }
 202 arch_initcall(platform_init);