arch/ia64/sn/pci/pcibr/pcibr_provider.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2001-2004 Silicon Graphics, Inc. All rights reserved.
   7  */
   8
   9 #include <linux/interrupt.h>
  10 #include <linux/types.h>
  11 #include <linux/pci.h>
  12 #include <asm/sn/addrs.h>
  13 #include <asm/sn/geo.h>
  14 #include <asm/sn/pcibr_provider.h>
  15 #include <asm/sn/pcibus_provider_defs.h>
  16 #include <asm/sn/pcidev.h>
  17 #include <asm/sn/sn_sal.h>
  18 #include "xtalk/xwidgetdev.h"
  19 #include "xtalk/hubdev.h"
  20
  21 int
  22 sal_pcibr_slot_enable(struct pcibus_info *soft, int device, void *resp)
  23 {
  24         struct ia64_sal_retval ret_stuff;
  25         uint64_t busnum;
  26
  27         ret_stuff.status = 0;
  28         ret_stuff.v0 = 0;
  29
  30         busnum = soft->pbi_buscommon.bs_persist_busnum;
  31         SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_SLOT_ENABLE, (u64) busnum,
  32                         (u64) device, (u64) resp, 0, 0, 0, 0);
  33
  34         return (int)ret_stuff.v0;
  35 }
  36
  37 int
  38 sal_pcibr_slot_disable(struct pcibus_info *soft, int device, int action,
  39                        void *resp)
  40 {
  41         struct ia64_sal_retval ret_stuff;
  42         uint64_t busnum;
  43
  44         ret_stuff.status = 0;
  45         ret_stuff.v0 = 0;
  46
  47         busnum = soft->pbi_buscommon.bs_persist_busnum;
  48         SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_SLOT_DISABLE,
  49                         (u64) busnum, (u64) device, (u64) action,
  50                         (u64) resp, 0, 0, 0);
  51
  52         return (int)ret_stuff.v0;
  53 }
  54
  55 static int sal_pcibr_error_interrupt(struct pcibus_info *soft)
  56 {
  57         struct ia64_sal_retval ret_stuff;
  58         uint64_t busnum;
  59         int segment;
  60         ret_stuff.status = 0;
  61         ret_stuff.v0 = 0;
  62
  63         segment = 0;
  64         busnum = soft->pbi_buscommon.bs_persist_busnum;
  65         SAL_CALL_NOLOCK(ret_stuff,
  66                         (u64) SN_SAL_IOIF_ERROR_INTERRUPT,
  67                         (u64) segment, (u64) busnum, 0, 0, 0, 0, 0);
  68
  69         return (int)ret_stuff.v0;
  70 }
  71
  72 /*
  73  * PCI Bridge Error interrupt handler.  Gets invoked whenever a PCI
  74  * bridge sends an error interrupt.
  75  */
  76 static irqreturn_t
  77 pcibr_error_intr_handler(int irq, void *arg, struct pt_regs *regs)
  78 {
  79         struct pcibus_info *soft = (struct pcibus_info *)arg;
  80
  81         if (sal_pcibr_error_interrupt(soft) < 0) {
  82                 panic("pcibr_error_intr_handler(): Fatal Bridge Error");
  83         }
  84         return IRQ_HANDLED;
  85 }
  86
  87 void *
  88 pcibr_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *controller)
  89 {
  90         int nasid, cnode, j;
  91         struct hubdev_info *hubdev_info;
  92         struct pcibus_info *soft;
  93         struct sn_flush_device_list *sn_flush_device_list;
  94
  95         if (! IS_PCI_BRIDGE_ASIC(prom_bussoft->bs_asic_type)) {
  96                 return NULL;
  97         }
  98
  99         /*
 100          * Allocate kernel bus soft and copy from prom.
 101          */
 102
 103         soft = kmalloc(sizeof(struct pcibus_info), GFP_KERNEL);
 104         if (!soft) {
 105                 return NULL;
 106         }
 107
 108         memcpy(soft, prom_bussoft, sizeof(struct pcibus_info));
 109         soft->pbi_buscommon.bs_base =
 110             (((u64) soft->pbi_buscommon.
 111               bs_base << 4) >> 4) | __IA64_UNCACHED_OFFSET;
 112
 113         spin_lock_init(&soft->pbi_lock);
 114
 115         /*
 116          * register the bridge's error interrupt handler
 117          */
 118         if (request_irq(SGI_PCIBR_ERROR, (void *)pcibr_error_intr_handler,
 119                         SA_SHIRQ, "PCIBR error", (void *)(soft))) {
 120                 printk(KERN_WARNING
 121                        "pcibr cannot allocate interrupt for error handler\n");
 122         }
 123
 124         /*
 125          * Update the Bridge with the "kernel" pagesize
 126          */
 127         if (PAGE_SIZE < 16384) {
 128                 pcireg_control_bit_clr(soft, PCIBR_CTRL_PAGE_SIZE);
 129         } else {
 130                 pcireg_control_bit_set(soft, PCIBR_CTRL_PAGE_SIZE);
 131         }
 132
 133         nasid = NASID_GET(soft->pbi_buscommon.bs_base);
 134         cnode = nasid_to_cnodeid(nasid);
 135         hubdev_info = (struct hubdev_info *)(NODEPDA(cnode)->pdinfo);
 136
 137         if (hubdev_info->hdi_flush_nasid_list.widget_p) {
 138                 sn_flush_device_list = hubdev_info->hdi_flush_nasid_list.
 139                     widget_p[(int)soft->pbi_buscommon.bs_xid];
 140                 if (sn_flush_device_list) {
 141                         for (j = 0; j < DEV_PER_WIDGET;
 142                              j++, sn_flush_device_list++) {
 143                                 if (sn_flush_device_list->sfdl_slot == -1)
 144                                         continue;
 145                                 if (sn_flush_device_list->
 146                                     sfdl_persistent_busnum ==
 147                                     soft->pbi_buscommon.bs_persist_busnum)
 148                                         sn_flush_device_list->sfdl_pcibus_info =
 149                                             soft;
 150                         }
 151                 }
 152         }
 153
 154         /* Setup the PMU ATE map */
 155         soft->pbi_int_ate_resource.lowest_free_index = 0;
 156         soft->pbi_int_ate_resource.ate =
 157             kmalloc(soft->pbi_int_ate_size * sizeof(uint64_t), GFP_KERNEL);
 158         memset(soft->pbi_int_ate_resource.ate, 0,
 159                (soft->pbi_int_ate_size * sizeof(uint64_t)));
 160
 161         if (prom_bussoft->bs_asic_type == PCIIO_ASIC_TYPE_TIOCP)
 162                 /*
 163                  * TIO PCI Bridge with no closest node information.
 164                  * FIXME: Find another way to determine the closest node
 165                  */
 166                 controller->node = -1;
 167         else
 168                 controller->node = cnode;
 169         return soft;
 170 }
 171
 172 void pcibr_force_interrupt(struct sn_irq_info *sn_irq_info)
 173 {
 174         struct pcidev_info *pcidev_info;
 175         struct pcibus_info *pcibus_info;
 176         int bit = sn_irq_info->irq_int_bit;
 177
 178         pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
 179         if (pcidev_info) {
 180                 pcibus_info =
 181                     (struct pcibus_info *)pcidev_info->pdi_host_pcidev_info->
 182                     pdi_pcibus_info;
 183                 pcireg_force_intr_set(pcibus_info, bit);
 184         }
 185 }
 186
 187 void pcibr_change_devices_irq(struct sn_irq_info *sn_irq_info)
 188 {
 189         struct pcidev_info *pcidev_info;
 190         struct pcibus_info *pcibus_info;
 191         int bit = sn_irq_info->irq_int_bit;
 192         uint64_t xtalk_addr = sn_irq_info->irq_xtalkaddr;
 193
 194         pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
 195         if (pcidev_info) {
 196                 pcibus_info =
 197                     (struct pcibus_info *)pcidev_info->pdi_host_pcidev_info->
 198                     pdi_pcibus_info;
 199
 200                 /* Disable the device's IRQ   */
 201                 pcireg_intr_enable_bit_clr(pcibus_info, bit);
 202
 203                 /* Change the device's IRQ    */
 204                 pcireg_intr_addr_addr_set(pcibus_info, bit, xtalk_addr);
 205
 206                 /* Re-enable the device's IRQ */
 207                 pcireg_intr_enable_bit_set(pcibus_info, bit);
 208
 209                 pcibr_force_interrupt(sn_irq_info);
 210         }
 211 }
 212
 213 /*
 214  * Provider entries for PIC/CP
 215  */
 216
 217 struct sn_pcibus_provider pcibr_provider = {
 218         .dma_map = pcibr_dma_map,
 219         .dma_map_consistent = pcibr_dma_map_consistent,
 220         .dma_unmap = pcibr_dma_unmap,
 221         .bus_fixup = pcibr_bus_fixup,
 222 };
 223
 224 int
 225 pcibr_init_provider(void)
 226 {
 227         sn_pci_provider[PCIIO_ASIC_TYPE_PIC] = &pcibr_provider;
 228         sn_pci_provider[PCIIO_ASIC_TYPE_TIOCP] = &pcibr_provider;
 229
 230         return 0;
 231 }
 232
 233 EXPORT_SYMBOL_GPL(sal_pcibr_slot_enable);
 234 EXPORT_SYMBOL_GPL(sal_pcibr_slot_disable);