arch/ia64/kernel/mca.c

   1 /*
   2  * File:        mca.c
   3  * Purpose:     Generic MCA handling layer
   4  *
   5  * Updated for latest kernel
   6  * Copyright (C) 2003 Hewlett-Packard Co
   7  *      David Mosberger-Tang <davidm@hpl.hp.com>
   8  *
   9  * Copyright (C) 2002 Dell Inc.
  10  * Copyright (C) Matt Domsch (Matt_Domsch@dell.com)
  11  *
  12  * Copyright (C) 2002 Intel
  13  * Copyright (C) Jenna Hall (jenna.s.hall@intel.com)
  14  *
  15  * Copyright (C) 2001 Intel
  16  * Copyright (C) Fred Lewis (frederick.v.lewis@intel.com)
  17  *
  18  * Copyright (C) 2000 Intel
  19  * Copyright (C) Chuck Fleckenstein (cfleck@co.intel.com)
  20  *
  21  * Copyright (C) 1999, 2004 Silicon Graphics, Inc.
  22  * Copyright (C) Vijay Chander(vijay@engr.sgi.com)
  23  *
  24  * 03/04/15 D. Mosberger Added INIT backtrace support.
  25  * 02/03/25 M. Domsch   GUID cleanups
  26  *
  27  * 02/01/04 J. Hall     Aligned MCA stack to 16 bytes, added platform vs. CPU
  28  *                      error flag, set SAL default return values, changed
  29  *                      error record structure to linked list, added init call
  30  *                      to sal_get_state_info_size().
  31  *
  32  * 01/01/03 F. Lewis    Added setup of CMCI and CPEI IRQs, logging of corrected
  33  *                      platform errors, completed code for logging of
  34  *                      corrected & uncorrected machine check errors, and
  35  *                      updated for conformance with Nov. 2000 revision of the
  36  *                      SAL 3.0 spec.
  37  * 00/03/29 C. Fleckenstein  Fixed PAL/SAL update issues, began MCA bug fixes, logging issues,
  38  *                           added min save state dump, added INIT handler.
  39  *
  40  * 2003-12-08 Keith Owens <kaos@sgi.com>
  41  *            smp_call_function() must not be called from interrupt context (can
  42  *            deadlock on tasklist_lock).  Use keventd to call smp_call_function().
  43  *
  44  * 2004-02-01 Keith Owens <kaos@sgi.com>
  45  *            Avoid deadlock when using printk() for MCA and INIT records.
  46  *            Delete all record printing code, moved to salinfo_decode in user space.
  47  *            Mark variables and functions static where possible.
  48  *            Delete dead variables and functions.
  49  *            Reorder to remove the need for forward declarations and to consolidate
  50  *            related code.
  51  *
  52  * 2005-08-12 Keith Owens <kaos@sgi.com>
  53  *            Convert MCA/INIT handlers to use per event stacks and SAL/OS state.
  54  *
  55  * 2005-10-07 Keith Owens <kaos@sgi.com>
  56  *            Add notify_die() hooks.
  57  */
  58 #include <linux/types.h>
  59 #include <linux/init.h>
  60 #include <linux/sched.h>
  61 #include <linux/interrupt.h>
  62 #include <linux/irq.h>
  63 #include <linux/smp_lock.h>
  64 #include <linux/bootmem.h>
  65 #include <linux/acpi.h>
  66 #include <linux/timer.h>
  67 #include <linux/module.h>
  68 #include <linux/kernel.h>
  69 #include <linux/smp.h>
  70 #include <linux/workqueue.h>
  71 #include <linux/cpumask.h>
  72
  73 #include <asm/delay.h>
  74 #include <asm/kdebug.h>
  75 #include <asm/machvec.h>
  76 #include <asm/meminit.h>
  77 #include <asm/page.h>
  78 #include <asm/ptrace.h>
  79 #include <asm/system.h>
  80 #include <asm/sal.h>
  81 #include <asm/mca.h>
  82
  83 #include <asm/irq.h>
  84 #include <asm/hw_irq.h>
  85
  86 #include "mca_drv.h"
  87 #include "entry.h"
  88
  89 #if defined(IA64_MCA_DEBUG_INFO)
  90 # define IA64_MCA_DEBUG(fmt...) printk(fmt)
  91 #else
  92 # define IA64_MCA_DEBUG(fmt...)
  93 #endif
  94
  95 /* Used by mca_asm.S */
  96 u32                             ia64_mca_serialize;
  97 DEFINE_PER_CPU(u64, ia64_mca_data); /* == __per_cpu_mca[smp_processor_id()] */
  98 DEFINE_PER_CPU(u64, ia64_mca_per_cpu_pte); /* PTE to map per-CPU area */
  99 DEFINE_PER_CPU(u64, ia64_mca_pal_pte);      /* PTE to map PAL code */
 100 DEFINE_PER_CPU(u64, ia64_mca_pal_base);    /* vaddr PAL code granule */
 101
 102 unsigned long __per_cpu_mca[NR_CPUS];
 103
 104 /* In mca_asm.S */
 105 extern void                     ia64_os_init_dispatch_monarch (void);
 106 extern void                     ia64_os_init_dispatch_slave (void);
 107
 108 static int monarch_cpu = -1;
 109
 110 static ia64_mc_info_t           ia64_mc_info;
 111
 112 #define MAX_CPE_POLL_INTERVAL (15*60*HZ) /* 15 minutes */
 113 #define MIN_CPE_POLL_INTERVAL (2*60*HZ)  /* 2 minutes */
 114 #define CMC_POLL_INTERVAL     (1*60*HZ)  /* 1 minute */
 115 #define CPE_HISTORY_LENGTH    5
 116 #define CMC_HISTORY_LENGTH    5
 117
 118 static struct timer_list cpe_poll_timer;
 119 static struct timer_list cmc_poll_timer;
 120 /*
 121  * This variable tells whether we are currently in polling mode.
 122  * Start with this in the wrong state so we won't play w/ timers
 123  * before the system is ready.
 124  */
 125 static int cmc_polling_enabled = 1;
 126
 127 /*
 128  * Clearing this variable prevents CPE polling from getting activated
 129  * in mca_late_init.  Use it if your system doesn't provide a CPEI,
 130  * but encounters problems retrieving CPE logs.  This should only be
 131  * necessary for debugging.
 132  */
 133 static int cpe_poll_enabled = 1;
 134
 135 extern void salinfo_log_wakeup(int type, u8 *buffer, u64 size, int irqsafe);
 136
 137 static int mca_init __initdata;
 138
 139
 140 static void inline
 141 ia64_mca_spin(const char *func)
 142 {
 143         printk(KERN_EMERG "%s: spinning here, not returning to SAL\n", func);
 144         while (1)
 145                 cpu_relax();
 146 }
 147 /*
 148  * IA64_MCA log support
 149  */
 150 #define IA64_MAX_LOGS           2       /* Double-buffering for nested MCAs */
 151 #define IA64_MAX_LOG_TYPES      4   /* MCA, INIT, CMC, CPE */
 152
 153 typedef struct ia64_state_log_s
 154 {
 155         spinlock_t      isl_lock;
 156         int             isl_index;
 157         unsigned long   isl_count;
 158         ia64_err_rec_t  *isl_log[IA64_MAX_LOGS]; /* need space to store header + error log */
 159 } ia64_state_log_t;
 160
 161 static ia64_state_log_t ia64_state_log[IA64_MAX_LOG_TYPES];
 162
 163 #define IA64_LOG_ALLOCATE(it, size) \
 164         {ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)] = \
 165                 (ia64_err_rec_t *)alloc_bootmem(size); \
 166         ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)] = \
 167                 (ia64_err_rec_t *)alloc_bootmem(size);}
 168 #define IA64_LOG_LOCK_INIT(it) spin_lock_init(&ia64_state_log[it].isl_lock)
 169 #define IA64_LOG_LOCK(it)      spin_lock_irqsave(&ia64_state_log[it].isl_lock, s)
 170 #define IA64_LOG_UNLOCK(it)    spin_unlock_irqrestore(&ia64_state_log[it].isl_lock,s)
 171 #define IA64_LOG_NEXT_INDEX(it)    ia64_state_log[it].isl_index
 172 #define IA64_LOG_CURR_INDEX(it)    1 - ia64_state_log[it].isl_index
 173 #define IA64_LOG_INDEX_INC(it) \
 174     {ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index; \
 175     ia64_state_log[it].isl_count++;}
 176 #define IA64_LOG_INDEX_DEC(it) \
 177     ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index
 178 #define IA64_LOG_NEXT_BUFFER(it)   (void *)((ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)]))
 179 #define IA64_LOG_CURR_BUFFER(it)   (void *)((ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)]))
 180 #define IA64_LOG_COUNT(it)         ia64_state_log[it].isl_count
 181
 182 /*
 183  * ia64_log_init
 184  *      Reset the OS ia64 log buffer
 185  * Inputs   :   info_type   (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
 186  * Outputs      :       None
 187  */
 188 static void __init
 189 ia64_log_init(int sal_info_type)
 190 {
 191         u64     max_size = 0;
 192
 193         IA64_LOG_NEXT_INDEX(sal_info_type) = 0;
 194         IA64_LOG_LOCK_INIT(sal_info_type);
 195
 196         // SAL will tell us the maximum size of any error record of this type
 197         max_size = ia64_sal_get_state_info_size(sal_info_type);
 198         if (!max_size)
 199                 /* alloc_bootmem() doesn't like zero-sized allocations! */
 200                 return;
 201
 202         // set up OS data structures to hold error info
 203         IA64_LOG_ALLOCATE(sal_info_type, max_size);
 204         memset(IA64_LOG_CURR_BUFFER(sal_info_type), 0, max_size);
 205         memset(IA64_LOG_NEXT_BUFFER(sal_info_type), 0, max_size);
 206 }
 207
 208 /*
 209  * ia64_log_get
 210  *
 211  *      Get the current MCA log from SAL and copy it into the OS log buffer.
 212  *
 213  *  Inputs  :   info_type   (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
 214  *              irq_safe    whether you can use printk at this point
 215  *  Outputs :   size        (total record length)
 216  *              *buffer     (ptr to error record)
 217  *
 218  */
 219 static u64
 220 ia64_log_get(int sal_info_type, u8 **buffer, int irq_safe)
 221 {
 222         sal_log_record_header_t     *log_buffer;
 223         u64                         total_len = 0;
 224         int                         s;
 225
 226         IA64_LOG_LOCK(sal_info_type);
 227
 228         /* Get the process state information */
 229         log_buffer = IA64_LOG_NEXT_BUFFER(sal_info_type);
 230
 231         total_len = ia64_sal_get_state_info(sal_info_type, (u64 *)log_buffer);
 232
 233         if (total_len) {
 234                 IA64_LOG_INDEX_INC(sal_info_type);
 235                 IA64_LOG_UNLOCK(sal_info_type);
 236                 if (irq_safe) {
 237                         IA64_MCA_DEBUG("%s: SAL error record type %d retrieved. "
 238                                        "Record length = %ld\n", __FUNCTION__, sal_info_type, total_len);
 239                 }
 240                 *buffer = (u8 *) log_buffer;
 241                 return total_len;
 242         } else {
 243                 IA64_LOG_UNLOCK(sal_info_type);
 244                 return 0;
 245         }
 246 }
 247
 248 /*
 249  *  ia64_mca_log_sal_error_record
 250  *
 251  *  This function retrieves a specified error record type from SAL
 252  *  and wakes up any processes waiting for error records.
 253  *
 254  *  Inputs  :   sal_info_type   (Type of error record MCA/CMC/CPE)
 255  *              FIXME: remove MCA and irq_safe.
 256  */
 257 static void
 258 ia64_mca_log_sal_error_record(int sal_info_type)
 259 {
 260         u8 *buffer;
 261         sal_log_record_header_t *rh;
 262         u64 size;
 263         int irq_safe = sal_info_type != SAL_INFO_TYPE_MCA;
 264 #ifdef IA64_MCA_DEBUG_INFO
 265         static const char * const rec_name[] = { "MCA", "INIT", "CMC", "CPE" };
 266 #endif
 267
 268         size = ia64_log_get(sal_info_type, &buffer, irq_safe);
 269         if (!size)
 270                 return;
 271
 272         salinfo_log_wakeup(sal_info_type, buffer, size, irq_safe);
 273
 274         if (irq_safe)
 275                 IA64_MCA_DEBUG("CPU %d: SAL log contains %s error record\n",
 276                         smp_processor_id(),
 277                         sal_info_type < ARRAY_SIZE(rec_name) ? rec_name[sal_info_type] : "UNKNOWN");
 278
 279         /* Clear logs from corrected errors in case there's no user-level logger */
 280         rh = (sal_log_record_header_t *)buffer;
 281         if (rh->severity == sal_log_severity_corrected)
 282                 ia64_sal_clear_state_info(sal_info_type);
 283 }
 284
 285 /*
 286  * search_mca_table
 287  *  See if the MCA surfaced in an instruction range
 288  *  that has been tagged as recoverable.
 289  *
 290  *  Inputs
 291  *      first   First address range to check
 292  *      last    Last address range to check
 293  *      ip      Instruction pointer, address we are looking for
 294  *
 295  * Return value:
 296  *      1 on Success (in the table)/ 0 on Failure (not in the  table)
 297  */
 298 int
 299 search_mca_table (const struct mca_table_entry *first,
 300                 const struct mca_table_entry *last,
 301                 unsigned long ip)
 302 {
 303         const struct mca_table_entry *curr;
 304         u64 curr_start, curr_end;
 305
 306         curr = first;
 307         while (curr <= last) {
 308                 curr_start = (u64) &curr->start_addr + curr->start_addr;
 309                 curr_end = (u64) &curr->end_addr + curr->end_addr;
 310
 311                 if ((ip >= curr_start) && (ip <= curr_end)) {
 312                         return 1;
 313                 }
 314                 curr++;
 315         }
 316         return 0;
 317 }
 318
 319 /* Given an address, look for it in the mca tables. */
 320 int mca_recover_range(unsigned long addr)
 321 {
 322         extern struct mca_table_entry __start___mca_table[];
 323         extern struct mca_table_entry __stop___mca_table[];
 324
 325         return search_mca_table(__start___mca_table, __stop___mca_table-1, addr);
 326 }
 327 EXPORT_SYMBOL_GPL(mca_recover_range);
 328
 329 #ifdef CONFIG_ACPI
 330
 331 int cpe_vector = -1;
 332 int ia64_cpe_irq = -1;
 333
 334 static irqreturn_t
 335 ia64_mca_cpe_int_handler (int cpe_irq, void *arg, struct pt_regs *ptregs)
 336 {
 337         static unsigned long    cpe_history[CPE_HISTORY_LENGTH];
 338         static int              index;
 339         static DEFINE_SPINLOCK(cpe_history_lock);
 340
 341         IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n",
 342                        __FUNCTION__, cpe_irq, smp_processor_id());
 343
 344         /* SAL spec states this should run w/ interrupts enabled */
 345         local_irq_enable();
 346
 347         /* Get the CPE error record and log it */
 348         ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CPE);
 349
 350         spin_lock(&cpe_history_lock);
 351         if (!cpe_poll_enabled && cpe_vector >= 0) {
 352
 353                 int i, count = 1; /* we know 1 happened now */
 354                 unsigned long now = jiffies;
 355
 356                 for (i = 0; i < CPE_HISTORY_LENGTH; i++) {
 357                         if (now - cpe_history[i] <= HZ)
 358                                 count++;
 359                 }
 360
 361                 IA64_MCA_DEBUG(KERN_INFO "CPE threshold %d/%d\n", count, CPE_HISTORY_LENGTH);
 362                 if (count >= CPE_HISTORY_LENGTH) {
 363
 364                         cpe_poll_enabled = 1;
 365                         spin_unlock(&cpe_history_lock);
 366                         disable_irq_nosync(local_vector_to_irq(IA64_CPE_VECTOR));
 367
 368                         /*
 369                          * Corrected errors will still be corrected, but
 370                          * make sure there's a log somewhere that indicates
 371                          * something is generating more than we can handle.
 372                          */
 373                         printk(KERN_WARNING "WARNING: Switching to polling CPE handler; error records may be lost\n");
 374
 375                         mod_timer(&cpe_poll_timer, jiffies + MIN_CPE_POLL_INTERVAL);
 376
 377                         /* lock already released, get out now */
 378                         return IRQ_HANDLED;
 379                 } else {
 380                         cpe_history[index++] = now;
 381                         if (index == CPE_HISTORY_LENGTH)
 382                                 index = 0;
 383                 }
 384         }
 385         spin_unlock(&cpe_history_lock);
 386         return IRQ_HANDLED;
 387 }
 388
 389 #endif /* CONFIG_ACPI */
 390
 391 #ifdef CONFIG_ACPI
 392 /*
 393  * ia64_mca_register_cpev
 394  *
 395  *  Register the corrected platform error vector with SAL.
 396  *
 397  *  Inputs
 398  *      cpev        Corrected Platform Error Vector number
 399  *
 400  *  Outputs
 401  *      None
 402  */
 403 static void __init
 404 ia64_mca_register_cpev (int cpev)
 405 {
 406         /* Register the CPE interrupt vector with SAL */
 407         struct ia64_sal_retval isrv;
 408
 409         isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_CPE_INT, SAL_MC_PARAM_MECHANISM_INT, cpev, 0, 0);
 410         if (isrv.status) {
 411                 printk(KERN_ERR "Failed to register Corrected Platform "
 412                        "Error interrupt vector with SAL (status %ld)\n", isrv.status);
 413                 return;
 414         }
 415
 416         IA64_MCA_DEBUG("%s: corrected platform error "
 417                        "vector %#x registered\n", __FUNCTION__, cpev);
 418 }
 419 #endif /* CONFIG_ACPI */
 420
 421 /*
 422  * ia64_mca_cmc_vector_setup
 423  *
 424  *  Setup the corrected machine check vector register in the processor.
 425  *  (The interrupt is masked on boot. ia64_mca_late_init unmask this.)
 426  *  This function is invoked on a per-processor basis.
 427  *
 428  * Inputs
 429  *      None
 430  *
 431  * Outputs
 432  *      None
 433  */
 434 void __cpuinit
 435 ia64_mca_cmc_vector_setup (void)
 436 {
 437         cmcv_reg_t      cmcv;
 438
 439         cmcv.cmcv_regval        = 0;
 440         cmcv.cmcv_mask          = 1;        /* Mask/disable interrupt at first */
 441         cmcv.cmcv_vector        = IA64_CMC_VECTOR;
 442         ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
 443
 444         IA64_MCA_DEBUG("%s: CPU %d corrected "
 445                        "machine check vector %#x registered.\n",
 446                        __FUNCTION__, smp_processor_id(), IA64_CMC_VECTOR);
 447
 448         IA64_MCA_DEBUG("%s: CPU %d CMCV = %#016lx\n",
 449                        __FUNCTION__, smp_processor_id(), ia64_getreg(_IA64_REG_CR_CMCV));
 450 }
 451
 452 /*
 453  * ia64_mca_cmc_vector_disable
 454  *
 455  *  Mask the corrected machine check vector register in the processor.
 456  *  This function is invoked on a per-processor basis.
 457  *
 458  * Inputs
 459  *      dummy(unused)
 460  *
 461  * Outputs
 462  *      None
 463  */
 464 static void
 465 ia64_mca_cmc_vector_disable (void *dummy)
 466 {
 467         cmcv_reg_t      cmcv;
 468
 469         cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV);
 470
 471         cmcv.cmcv_mask = 1; /* Mask/disable interrupt */
 472         ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
 473
 474         IA64_MCA_DEBUG("%s: CPU %d corrected "
 475                        "machine check vector %#x disabled.\n",
 476                        __FUNCTION__, smp_processor_id(), cmcv.cmcv_vector);
 477 }
 478
 479 /*
 480  * ia64_mca_cmc_vector_enable
 481  *
 482  *  Unmask the corrected machine check vector register in the processor.
 483  *  This function is invoked on a per-processor basis.
 484  *
 485  * Inputs
 486  *      dummy(unused)
 487  *
 488  * Outputs
 489  *      None
 490  */
 491 static void
 492 ia64_mca_cmc_vector_enable (void *dummy)
 493 {
 494         cmcv_reg_t      cmcv;
 495
 496         cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV);
 497
 498         cmcv.cmcv_mask = 0; /* Unmask/enable interrupt */
 499         ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
 500
 501         IA64_MCA_DEBUG("%s: CPU %d corrected "
 502                        "machine check vector %#x enabled.\n",
 503                        __FUNCTION__, smp_processor_id(), cmcv.cmcv_vector);
 504 }
 505
 506 /*
 507  * ia64_mca_cmc_vector_disable_keventd
 508  *
 509  * Called via keventd (smp_call_function() is not safe in interrupt context) to
 510  * disable the cmc interrupt vector.
 511  */
 512 static void
 513 ia64_mca_cmc_vector_disable_keventd(void *unused)
 514 {
 515         on_each_cpu(ia64_mca_cmc_vector_disable, NULL, 1, 0);
 516 }
 517
 518 /*
 519  * ia64_mca_cmc_vector_enable_keventd
 520  *
 521  * Called via keventd (smp_call_function() is not safe in interrupt context) to
 522  * enable the cmc interrupt vector.
 523  */
 524 static void
 525 ia64_mca_cmc_vector_enable_keventd(void *unused)
 526 {
 527         on_each_cpu(ia64_mca_cmc_vector_enable, NULL, 1, 0);
 528 }
 529
 530 /*
 531  * ia64_mca_wakeup
 532  *
 533  *      Send an inter-cpu interrupt to wake-up a particular cpu
 534  *      and mark that cpu to be out of rendez.
 535  *
 536  *  Inputs  :   cpuid
 537  *  Outputs :   None
 538  */
 539 static void
 540 ia64_mca_wakeup(int cpu)
 541 {
 542         platform_send_ipi(cpu, IA64_MCA_WAKEUP_VECTOR, IA64_IPI_DM_INT, 0);
 543         ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
 544
 545 }
 546
 547 /*
 548  * ia64_mca_wakeup_all
 549  *
 550  *      Wakeup all the cpus which have rendez'ed previously.
 551  *
 552  *  Inputs  :   None
 553  *  Outputs :   None
 554  */
 555 static void
 556 ia64_mca_wakeup_all(void)
 557 {
 558         int cpu;
 559
 560         /* Clear the Rendez checkin flag for all cpus */
 561         for_each_online_cpu(cpu) {
 562                 if (ia64_mc_info.imi_rendez_checkin[cpu] == IA64_MCA_RENDEZ_CHECKIN_DONE)
 563                         ia64_mca_wakeup(cpu);
 564         }
 565
 566 }
 567
 568 /*
 569  * ia64_mca_rendez_interrupt_handler
 570  *
 571  *      This is handler used to put slave processors into spinloop
 572  *      while the monarch processor does the mca handling and later
 573  *      wake each slave up once the monarch is done.
 574  *
 575  *  Inputs  :   None
 576  *  Outputs :   None
 577  */
 578 static irqreturn_t
 579 ia64_mca_rendez_int_handler(int rendez_irq, void *arg, struct pt_regs *regs)
 580 {
 581         unsigned long flags;
 582         int cpu = smp_processor_id();
 583         struct ia64_mca_notify_die nd =
 584                 { .sos = NULL, .monarch_cpu = &monarch_cpu };
 585
 586         /* Mask all interrupts */
 587         local_irq_save(flags);
 588         if (notify_die(DIE_MCA_RENDZVOUS_ENTER, "MCA", regs, (long)&nd, 0, 0)
 589                         == NOTIFY_STOP)
 590                 ia64_mca_spin(__FUNCTION__);
 591
 592         ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_DONE;
 593         /* Register with the SAL monarch that the slave has
 594          * reached SAL
 595          */
 596         ia64_sal_mc_rendez();
 597
 598         if (notify_die(DIE_MCA_RENDZVOUS_PROCESS, "MCA", regs, (long)&nd, 0, 0)
 599                         == NOTIFY_STOP)
 600                 ia64_mca_spin(__FUNCTION__);
 601
 602         /* Wait for the monarch cpu to exit. */
 603         while (monarch_cpu != -1)
 604                cpu_relax();     /* spin until monarch leaves */
 605
 606         if (notify_die(DIE_MCA_RENDZVOUS_LEAVE, "MCA", regs, (long)&nd, 0, 0)
 607                         == NOTIFY_STOP)
 608                 ia64_mca_spin(__FUNCTION__);
 609
 610         /* Enable all interrupts */
 611         local_irq_restore(flags);
 612         return IRQ_HANDLED;
 613 }
 614
 615 /*
 616  * ia64_mca_wakeup_int_handler
 617  *
 618  *      The interrupt handler for processing the inter-cpu interrupt to the
 619  *      slave cpu which was spinning in the rendez loop.
 620  *      Since this spinning is done by turning off the interrupts and
 621  *      polling on the wakeup-interrupt bit in the IRR, there is
 622  *      nothing useful to be done in the handler.
 623  *
 624  *  Inputs  :   wakeup_irq  (Wakeup-interrupt bit)
 625  *      arg             (Interrupt handler specific argument)
 626  *      ptregs          (Exception frame at the time of the interrupt)
 627  *  Outputs :   None
 628  *
 629  */
 630 static irqreturn_t
 631 ia64_mca_wakeup_int_handler(int wakeup_irq, void *arg, struct pt_regs *ptregs)
 632 {
 633         return IRQ_HANDLED;
 634 }
 635
 636 /* Function pointer for extra MCA recovery */
 637 int (*ia64_mca_ucmc_extension)
 638         (void*,struct ia64_sal_os_state*)
 639         = NULL;
 640
 641 int
 642 ia64_reg_MCA_extension(int (*fn)(void *, struct ia64_sal_os_state *))
 643 {
 644         if (ia64_mca_ucmc_extension)
 645                 return 1;
 646
 647         ia64_mca_ucmc_extension = fn;
 648         return 0;
 649 }
 650
 651 void
 652 ia64_unreg_MCA_extension(void)
 653 {
 654         if (ia64_mca_ucmc_extension)
 655                 ia64_mca_ucmc_extension = NULL;
 656 }
 657
 658 EXPORT_SYMBOL(ia64_reg_MCA_extension);
 659 EXPORT_SYMBOL(ia64_unreg_MCA_extension);
 660
 661
 662 static inline void
 663 copy_reg(const u64 *fr, u64 fnat, u64 *tr, u64 *tnat)
 664 {
 665         u64 fslot, tslot, nat;
 666         *tr = *fr;
 667         fslot = ((unsigned long)fr >> 3) & 63;
 668         tslot = ((unsigned long)tr >> 3) & 63;
 669         *tnat &= ~(1UL << tslot);
 670         nat = (fnat >> fslot) & 1;
 671         *tnat |= (nat << tslot);
 672 }
 673
 674 /* Change the comm field on the MCA/INT task to include the pid that
 675  * was interrupted, it makes for easier debugging.  If that pid was 0
 676  * (swapper or nested MCA/INIT) then use the start of the previous comm
 677  * field suffixed with its cpu.
 678  */
 679
 680 static void
 681 ia64_mca_modify_comm(const task_t *previous_current)
 682 {
 683         char *p, comm[sizeof(current->comm)];
 684         if (previous_current->pid)
 685                 snprintf(comm, sizeof(comm), "%s %d",
 686                         current->comm, previous_current->pid);
 687         else {
 688                 int l;
 689                 if ((p = strchr(previous_current->comm, ' ')))
 690                         l = p - previous_current->comm;
 691                 else
 692                         l = strlen(previous_current->comm);
 693                 snprintf(comm, sizeof(comm), "%s %*s %d",
 694                         current->comm, l, previous_current->comm,
 695                         task_thread_info(previous_current)->cpu);
 696         }
 697         memcpy(current->comm, comm, sizeof(current->comm));
 698 }
 699
 700 /* On entry to this routine, we are running on the per cpu stack, see
 701  * mca_asm.h.  The original stack has not been touched by this event.  Some of
 702  * the original stack's registers will be in the RBS on this stack.  This stack
 703  * also contains a partial pt_regs and switch_stack, the rest of the data is in
 704  * PAL minstate.
 705  *
 706  * The first thing to do is modify the original stack to look like a blocked
 707  * task so we can run backtrace on the original task.  Also mark the per cpu
 708  * stack as current to ensure that we use the correct task state, it also means
 709  * that we can do backtrace on the MCA/INIT handler code itself.
 710  */
 711
 712 static task_t *
 713 ia64_mca_modify_original_stack(struct pt_regs *regs,
 714                 const struct switch_stack *sw,
 715                 struct ia64_sal_os_state *sos,
 716                 const char *type)
 717 {
 718         char *p;
 719         ia64_va va;
 720         extern char ia64_leave_kernel[];        /* Need asm address, not function descriptor */
 721         const pal_min_state_area_t *ms = sos->pal_min_state;
 722         task_t *previous_current;
 723         struct pt_regs *old_regs;
 724         struct switch_stack *old_sw;
 725         unsigned size = sizeof(struct pt_regs) +
 726                         sizeof(struct switch_stack) + 16;
 727         u64 *old_bspstore, *old_bsp;
 728         u64 *new_bspstore, *new_bsp;
 729         u64 old_unat, old_rnat, new_rnat, nat;
 730         u64 slots, loadrs = regs->loadrs;
 731         u64 r12 = ms->pmsa_gr[12-1], r13 = ms->pmsa_gr[13-1];
 732         u64 ar_bspstore = regs->ar_bspstore;
 733         u64 ar_bsp = regs->ar_bspstore + (loadrs >> 16);
 734         const u64 *bank;
 735         const char *msg;
 736         int cpu = smp_processor_id();
 737
 738         previous_current = curr_task(cpu);
 739         set_curr_task(cpu, current);
 740         if ((p = strchr(current->comm, ' ')))
 741                 *p = '\0';
 742
 743         /* Best effort attempt to cope with MCA/INIT delivered while in
 744          * physical mode.
 745          */
 746         regs->cr_ipsr = ms->pmsa_ipsr;
 747         if (ia64_psr(regs)->dt == 0) {
 748                 va.l = r12;
 749                 if (va.f.reg == 0) {
 750                         va.f.reg = 7;
 751                         r12 = va.l;
 752                 }
 753                 va.l = r13;
 754                 if (va.f.reg == 0) {
 755                         va.f.reg = 7;
 756                         r13 = va.l;
 757                 }
 758         }
 759         if (ia64_psr(regs)->rt == 0) {
 760                 va.l = ar_bspstore;
 761                 if (va.f.reg == 0) {
 762                         va.f.reg = 7;
 763                         ar_bspstore = va.l;
 764                 }
 765                 va.l = ar_bsp;
 766                 if (va.f.reg == 0) {
 767                         va.f.reg = 7;
 768                         ar_bsp = va.l;
 769                 }
 770         }
 771
 772         /* mca_asm.S ia64_old_stack() cannot assume that the dirty registers
 773          * have been copied to the old stack, the old stack may fail the
 774          * validation tests below.  So ia64_old_stack() must restore the dirty
 775          * registers from the new stack.  The old and new bspstore probably
 776          * have different alignments, so loadrs calculated on the old bsp
 777          * cannot be used to restore from the new bsp.  Calculate a suitable
 778          * loadrs for the new stack and save it in the new pt_regs, where
 779          * ia64_old_stack() can get it.
 780          */
 781         old_bspstore = (u64 *)ar_bspstore;
 782         old_bsp = (u64 *)ar_bsp;
 783         slots = ia64_rse_num_regs(old_bspstore, old_bsp);
 784         new_bspstore = (u64 *)((u64)current + IA64_RBS_OFFSET);
 785         new_bsp = ia64_rse_skip_regs(new_bspstore, slots);
 786         regs->loadrs = (new_bsp - new_bspstore) * 8 << 16;
 787
 788         /* Verify the previous stack state before we change it */
 789         if (user_mode(regs)) {
 790                 msg = "occurred in user space";
 791                 /* previous_current is guaranteed to be valid when the task was
 792                  * in user space, so ...
 793                  */
 794                 ia64_mca_modify_comm(previous_current);
 795                 goto no_mod;
 796         }
 797
 798         if (!mca_recover_range(ms->pmsa_iip)) {
 799                 if (r13 != sos->prev_IA64_KR_CURRENT) {
 800                         msg = "inconsistent previous current and r13";
 801                         goto no_mod;
 802                 }
 803                 if ((r12 - r13) >= KERNEL_STACK_SIZE) {
 804                         msg = "inconsistent r12 and r13";
 805                         goto no_mod;
 806                 }
 807                 if ((ar_bspstore - r13) >= KERNEL_STACK_SIZE) {
 808                         msg = "inconsistent ar.bspstore and r13";
 809                         goto no_mod;
 810                 }
 811                 va.p = old_bspstore;
 812                 if (va.f.reg < 5) {
 813                         msg = "old_bspstore is in the wrong region";
 814                         goto no_mod;
 815                 }
 816                 if ((ar_bsp - r13) >= KERNEL_STACK_SIZE) {
 817                         msg = "inconsistent ar.bsp and r13";
 818                         goto no_mod;
 819                 }
 820                 size += (ia64_rse_skip_regs(old_bspstore, slots) - old_bspstore) * 8;
 821                 if (ar_bspstore + size > r12) {
 822                         msg = "no room for blocked state";
 823                         goto no_mod;
 824                 }
 825         }
 826
 827         ia64_mca_modify_comm(previous_current);
 828
 829         /* Make the original task look blocked.  First stack a struct pt_regs,
 830          * describing the state at the time of interrupt.  mca_asm.S built a
 831          * partial pt_regs, copy it and fill in the blanks using minstate.
 832          */
 833         p = (char *)r12 - sizeof(*regs);
 834         old_regs = (struct pt_regs *)p;
 835         memcpy(old_regs, regs, sizeof(*regs));
 836         /* If ipsr.ic then use pmsa_{iip,ipsr,ifs}, else use
 837          * pmsa_{xip,xpsr,xfs}
 838          */
 839         if (ia64_psr(regs)->ic) {
 840                 old_regs->cr_iip = ms->pmsa_iip;
 841                 old_regs->cr_ipsr = ms->pmsa_ipsr;
 842                 old_regs->cr_ifs = ms->pmsa_ifs;
 843         } else {
 844                 old_regs->cr_iip = ms->pmsa_xip;
 845                 old_regs->cr_ipsr = ms->pmsa_xpsr;
 846                 old_regs->cr_ifs = ms->pmsa_xfs;
 847         }
 848         old_regs->pr = ms->pmsa_pr;
 849         old_regs->b0 = ms->pmsa_br0;
 850         old_regs->loadrs = loadrs;
 851         old_regs->ar_rsc = ms->pmsa_rsc;
 852         old_unat = old_regs->ar_unat;
 853         copy_reg(&ms->pmsa_gr[1-1], ms->pmsa_nat_bits, &old_regs->r1, &old_unat);
 854         copy_reg(&ms->pmsa_gr[2-1], ms->pmsa_nat_bits, &old_regs->r2, &old_unat);
 855         copy_reg(&ms->pmsa_gr[3-1], ms->pmsa_nat_bits, &old_regs->r3, &old_unat);
 856         copy_reg(&ms->pmsa_gr[8-1], ms->pmsa_nat_bits, &old_regs->r8, &old_unat);
 857         copy_reg(&ms->pmsa_gr[9-1], ms->pmsa_nat_bits, &old_regs->r9, &old_unat);
 858         copy_reg(&ms->pmsa_gr[10-1], ms->pmsa_nat_bits, &old_regs->r10, &old_unat);
 859         copy_reg(&ms->pmsa_gr[11-1], ms->pmsa_nat_bits, &old_regs->r11, &old_unat);
 860         copy_reg(&ms->pmsa_gr[12-1], ms->pmsa_nat_bits, &old_regs->r12, &old_unat);
 861         copy_reg(&ms->pmsa_gr[13-1], ms->pmsa_nat_bits, &old_regs->r13, &old_unat);
 862         copy_reg(&ms->pmsa_gr[14-1], ms->pmsa_nat_bits, &old_regs->r14, &old_unat);
 863         copy_reg(&ms->pmsa_gr[15-1], ms->pmsa_nat_bits, &old_regs->r15, &old_unat);
 864         if (ia64_psr(old_regs)->bn)
 865                 bank = ms->pmsa_bank1_gr;
 866         else
 867                 bank = ms->pmsa_bank0_gr;
 868         copy_reg(&bank[16-16], ms->pmsa_nat_bits, &old_regs->r16, &old_unat);
 869         copy_reg(&bank[17-16], ms->pmsa_nat_bits, &old_regs->r17, &old_unat);
 870         copy_reg(&bank[18-16], ms->pmsa_nat_bits, &old_regs->r18, &old_unat);
 871         copy_reg(&bank[19-16], ms->pmsa_nat_bits, &old_regs->r19, &old_unat);
 872         copy_reg(&bank[20-16], ms->pmsa_nat_bits, &old_regs->r20, &old_unat);
 873         copy_reg(&bank[21-16], ms->pmsa_nat_bits, &old_regs->r21, &old_unat);
 874         copy_reg(&bank[22-16], ms->pmsa_nat_bits, &old_regs->r22, &old_unat);
 875         copy_reg(&bank[23-16], ms->pmsa_nat_bits, &old_regs->r23, &old_unat);
 876         copy_reg(&bank[24-16], ms->pmsa_nat_bits, &old_regs->r24, &old_unat);
 877         copy_reg(&bank[25-16], ms->pmsa_nat_bits, &old_regs->r25, &old_unat);
 878         copy_reg(&bank[26-16], ms->pmsa_nat_bits, &old_regs->r26, &old_unat);
 879         copy_reg(&bank[27-16], ms->pmsa_nat_bits, &old_regs->r27, &old_unat);
 880         copy_reg(&bank[28-16], ms->pmsa_nat_bits, &old_regs->r28, &old_unat);
 881         copy_reg(&bank[29-16], ms->pmsa_nat_bits, &old_regs->r29, &old_unat);
 882         copy_reg(&bank[30-16], ms->pmsa_nat_bits, &old_regs->r30, &old_unat);
 883         copy_reg(&bank[31-16], ms->pmsa_nat_bits, &old_regs->r31, &old_unat);
 884
 885         /* Next stack a struct switch_stack.  mca_asm.S built a partial
 886          * switch_stack, copy it and fill in the blanks using pt_regs and
 887          * minstate.
 888          *
 889          * In the synthesized switch_stack, b0 points to ia64_leave_kernel,
 890          * ar.pfs is set to 0.
 891          *
 892          * unwind.c::unw_unwind() does special processing for interrupt frames.
 893          * It checks if the PRED_NON_SYSCALL predicate is set, if the predicate
 894          * is clear then unw_unwind() does _not_ adjust bsp over pt_regs.  Not
 895          * that this is documented, of course.  Set PRED_NON_SYSCALL in the
 896          * switch_stack on the original stack so it will unwind correctly when
 897          * unwind.c reads pt_regs.
 898          *
 899          * thread.ksp is updated to point to the synthesized switch_stack.
 900          */
 901         p -= sizeof(struct switch_stack);
 902         old_sw = (struct switch_stack *)p;
 903         memcpy(old_sw, sw, sizeof(*sw));
 904         old_sw->caller_unat = old_unat;
 905         old_sw->ar_fpsr = old_regs->ar_fpsr;
 906         copy_reg(&ms->pmsa_gr[4-1], ms->pmsa_nat_bits, &old_sw->r4, &old_unat);
 907         copy_reg(&ms->pmsa_gr[5-1], ms->pmsa_nat_bits, &old_sw->r5, &old_unat);
 908         copy_reg(&ms->pmsa_gr[6-1], ms->pmsa_nat_bits, &old_sw->r6, &old_unat);
 909         copy_reg(&ms->pmsa_gr[7-1], ms->pmsa_nat_bits, &old_sw->r7, &old_unat);
 910         old_sw->b0 = (u64)ia64_leave_kernel;
 911         old_sw->b1 = ms->pmsa_br1;
 912         old_sw->ar_pfs = 0;
 913         old_sw->ar_unat = old_unat;
 914         old_sw->pr = old_regs->pr | (1UL << PRED_NON_SYSCALL);
 915         previous_current->thread.ksp = (u64)p - 16;
 916
 917         /* Finally copy the original stack's registers back to its RBS.
 918          * Registers from ar.bspstore through ar.bsp at the time of the event
 919          * are in the current RBS, copy them back to the original stack.  The
 920          * copy must be done register by register because the original bspstore
 921          * and the current one have different alignments, so the saved RNAT
 922          * data occurs at different places.
 923          *
 924          * mca_asm does cover, so the old_bsp already includes all registers at
 925          * the time of MCA/INIT.  It also does flushrs, so all registers before
 926          * this function have been written to backing store on the MCA/INIT
 927          * stack.
 928          */
 929         new_rnat = ia64_get_rnat(ia64_rse_rnat_addr(new_bspstore));
 930         old_rnat = regs->ar_rnat;
 931         while (slots--) {
 932                 if (ia64_rse_is_rnat_slot(new_bspstore)) {
 933                         new_rnat = ia64_get_rnat(new_bspstore++);
 934                 }
 935                 if (ia64_rse_is_rnat_slot(old_bspstore)) {
 936                         *old_bspstore++ = old_rnat;
 937                         old_rnat = 0;
 938                 }
 939                 nat = (new_rnat >> ia64_rse_slot_num(new_bspstore)) & 1UL;
 940                 old_rnat &= ~(1UL << ia64_rse_slot_num(old_bspstore));
 941                 old_rnat |= (nat << ia64_rse_slot_num(old_bspstore));
 942                 *old_bspstore++ = *new_bspstore++;
 943         }
 944         old_sw->ar_bspstore = (unsigned long)old_bspstore;
 945         old_sw->ar_rnat = old_rnat;
 946
 947         sos->prev_task = previous_current;
 948         return previous_current;
 949
 950 no_mod:
 951         printk(KERN_INFO "cpu %d, %s %s, original stack not modified\n",
 952                         smp_processor_id(), type, msg);
 953         return previous_current;
 954 }
 955
 956 /* The monarch/slave interaction is based on monarch_cpu and requires that all
 957  * slaves have entered rendezvous before the monarch leaves.  If any cpu has
 958  * not entered rendezvous yet then wait a bit.  The assumption is that any
 959  * slave that has not rendezvoused after a reasonable time is never going to do
 960  * so.  In this context, slave includes cpus that respond to the MCA rendezvous
 961  * interrupt, as well as cpus that receive the INIT slave event.
 962  */
 963
 964 static void
 965 ia64_wait_for_slaves(int monarch, const char *type)
 966 {
 967         int c, wait = 0, missing = 0;
 968         for_each_online_cpu(c) {
 969                 if (c == monarch)
 970                         continue;
 971                 if (ia64_mc_info.imi_rendez_checkin[c] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE) {
 972                         udelay(1000);           /* short wait first */
 973                         wait = 1;
 974                         break;
 975                 }
 976         }
 977         if (!wait)
 978                 goto all_in;
 979         for_each_online_cpu(c) {
 980                 if (c == monarch)
 981                         continue;
 982                 if (ia64_mc_info.imi_rendez_checkin[c] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE) {
 983                         udelay(5*1000000);      /* wait 5 seconds for slaves (arbitrary) */
 984                         if (ia64_mc_info.imi_rendez_checkin[c] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE)
 985                                 missing = 1;
 986                         break;
 987                 }
 988         }
 989         if (!missing)
 990                 goto all_in;
 991         printk(KERN_INFO "OS %s slave did not rendezvous on cpu", type);
 992         for_each_online_cpu(c) {
 993                 if (c == monarch)
 994                         continue;
 995                 if (ia64_mc_info.imi_rendez_checkin[c] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE)
 996                         printk(" %d", c);
 997         }
 998         printk("\n");
 999         return;
1000
1001 all_in:
1002         printk(KERN_INFO "All OS %s slaves have reached rendezvous\n", type);
1003         return;
1004 }
1005
1006 /*
1007  * ia64_mca_handler
1008  *
1009  *      This is uncorrectable machine check handler called from OS_MCA
1010  *      dispatch code which is in turn called from SAL_CHECK().
1011  *      This is the place where the core of OS MCA handling is done.
1012  *      Right now the logs are extracted and displayed in a well-defined
1013  *      format. This handler code is supposed to be run only on the
1014  *      monarch processor. Once the monarch is done with MCA handling
1015  *      further MCA logging is enabled by clearing logs.
1016  *      Monarch also has the duty of sending wakeup-IPIs to pull the
1017  *      slave processors out of rendezvous spinloop.
1018  */
1019 void
1020 ia64_mca_handler(struct pt_regs *regs, struct switch_stack *sw,
1021                  struct ia64_sal_os_state *sos)
1022 {
1023         pal_processor_state_info_t *psp = (pal_processor_state_info_t *)
1024                 &sos->proc_state_param;
1025         int recover, cpu = smp_processor_id();
1026         task_t *previous_current;
1027         struct ia64_mca_notify_die nd =
1028                 { .sos = sos, .monarch_cpu = &monarch_cpu };
1029
1030         oops_in_progress = 1;   /* FIXME: make printk NMI/MCA/INIT safe */
1031         console_loglevel = 15;  /* make sure printks make it to console */
1032         printk(KERN_INFO "Entered OS MCA handler. PSP=%lx cpu=%d monarch=%ld\n",
1033                 sos->proc_state_param, cpu, sos->monarch);
1034
1035         previous_current = ia64_mca_modify_original_stack(regs, sw, sos, "MCA");
1036         monarch_cpu = cpu;
1037         if (notify_die(DIE_MCA_MONARCH_ENTER, "MCA", regs, (long)&nd, 0, 0)
1038                         == NOTIFY_STOP)
1039                 ia64_mca_spin(__FUNCTION__);
1040         ia64_wait_for_slaves(cpu, "MCA");
1041
1042         /* Wakeup all the processors which are spinning in the rendezvous loop.
1043          * They will leave SAL, then spin in the OS with interrupts disabled
1044          * until this monarch cpu leaves the MCA handler.  That gets control
1045          * back to the OS so we can backtrace the other cpus, backtrace when
1046          * spinning in SAL does not work.
1047          */
1048         ia64_mca_wakeup_all();
1049         if (notify_die(DIE_MCA_MONARCH_PROCESS, "MCA", regs, (long)&nd, 0, 0)
1050                         == NOTIFY_STOP)
1051                 ia64_mca_spin(__FUNCTION__);
1052
1053         /* Get the MCA error record and log it */
1054         ia64_mca_log_sal_error_record(SAL_INFO_TYPE_MCA);
1055
1056         /* TLB error is only exist in this SAL error record */
1057         recover = (psp->tc && !(psp->cc || psp->bc || psp->rc || psp->uc))
1058         /* other error recovery */
1059            || (ia64_mca_ucmc_extension
1060                 && ia64_mca_ucmc_extension(
1061                         IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_MCA),
1062                         sos));
1063
1064         if (recover) {
1065                 sal_log_record_header_t *rh = IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_MCA);
1066                 rh->severity = sal_log_severity_corrected;
1067                 ia64_sal_clear_state_info(SAL_INFO_TYPE_MCA);
1068                 sos->os_status = IA64_MCA_CORRECTED;
1069         }
1070         if (notify_die(DIE_MCA_MONARCH_LEAVE, "MCA", regs, (long)&nd, 0, recover)
1071                         == NOTIFY_STOP)
1072                 ia64_mca_spin(__FUNCTION__);
1073
1074         set_curr_task(cpu, previous_current);
1075         monarch_cpu = -1;
1076 }
1077
1078 static DECLARE_WORK(cmc_disable_work, ia64_mca_cmc_vector_disable_keventd, NULL);
1079 static DECLARE_WORK(cmc_enable_work, ia64_mca_cmc_vector_enable_keventd, NULL);
1080
1081 /*
1082  * ia64_mca_cmc_int_handler
1083  *
1084  *  This is corrected machine check interrupt handler.
1085  *      Right now the logs are extracted and displayed in a well-defined
1086  *      format.
1087  *
1088  * Inputs
1089  *      interrupt number
1090  *      client data arg ptr
1091  *      saved registers ptr
1092  *
1093  * Outputs
1094  *      None
1095  */
1096 static irqreturn_t
1097 ia64_mca_cmc_int_handler(int cmc_irq, void *arg, struct pt_regs *ptregs)
1098 {
1099         static unsigned long    cmc_history[CMC_HISTORY_LENGTH];
1100         static int              index;
1101         static DEFINE_SPINLOCK(cmc_history_lock);
1102
1103         IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n",
1104                        __FUNCTION__, cmc_irq, smp_processor_id());
1105
1106         /* SAL spec states this should run w/ interrupts enabled */
1107         local_irq_enable();
1108
1109         /* Get the CMC error record and log it */
1110         ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CMC);
1111
1112         spin_lock(&cmc_history_lock);
1113         if (!cmc_polling_enabled) {
1114                 int i, count = 1; /* we know 1 happened now */
1115                 unsigned long now = jiffies;
1116
1117                 for (i = 0; i < CMC_HISTORY_LENGTH; i++) {
1118                         if (now - cmc_history[i] <= HZ)
1119                                 count++;
1120                 }
1121
1122                 IA64_MCA_DEBUG(KERN_INFO "CMC threshold %d/%d\n", count, CMC_HISTORY_LENGTH);
1123                 if (count >= CMC_HISTORY_LENGTH) {
1124
1125                         cmc_polling_enabled = 1;
1126                         spin_unlock(&cmc_history_lock);
1127                         /* If we're being hit with CMC interrupts, we won't
1128                          * ever execute the schedule_work() below.  Need to
1129                          * disable CMC interrupts on this processor now.
1130                          */
1131                         ia64_mca_cmc_vector_disable(NULL);
1132                         schedule_work(&cmc_disable_work);
1133
1134                         /*
1135                          * Corrected errors will still be corrected, but
1136                          * make sure there's a log somewhere that indicates
1137                          * something is generating more than we can handle.
1138                          */
1139                         printk(KERN_WARNING "WARNING: Switching to polling CMC handler; error records may be lost\n");
1140
1141                         mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL);
1142
1143                         /* lock already released, get out now */
1144                         return IRQ_HANDLED;
1145                 } else {
1146                         cmc_history[index++] = now;
1147                         if (index == CMC_HISTORY_LENGTH)
1148                                 index = 0;
1149                 }
1150         }
1151         spin_unlock(&cmc_history_lock);
1152         return IRQ_HANDLED;
1153 }
1154
1155 /*
1156  *  ia64_mca_cmc_int_caller
1157  *
1158  *      Triggered by sw interrupt from CMC polling routine.  Calls
1159  *      real interrupt handler and either triggers a sw interrupt
1160  *      on the next cpu or does cleanup at the end.
1161  *
1162  * Inputs
1163  *      interrupt number
1164  *      client data arg ptr
1165  *      saved registers ptr
1166  * Outputs
1167  *      handled
1168  */
1169 static irqreturn_t
1170 ia64_mca_cmc_int_caller(int cmc_irq, void *arg, struct pt_regs *ptregs)
1171 {
1172         static int start_count = -1;
1173         unsigned int cpuid;
1174
1175         cpuid = smp_processor_id();
1176
1177         /* If first cpu, update count */
1178         if (start_count == -1)
1179                 start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CMC);
1180
1181         ia64_mca_cmc_int_handler(cmc_irq, arg, ptregs);
1182
1183         for (++cpuid ; cpuid < NR_CPUS && !cpu_online(cpuid) ; cpuid++);
1184
1185         if (cpuid < NR_CPUS) {
1186                 platform_send_ipi(cpuid, IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0);
1187         } else {
1188                 /* If no log record, switch out of polling mode */
1189                 if (start_count == IA64_LOG_COUNT(SAL_INFO_TYPE_CMC)) {
1190
1191                         printk(KERN_WARNING "Returning to interrupt driven CMC handler\n");
1192                         schedule_work(&cmc_enable_work);
1193                         cmc_polling_enabled = 0;
1194
1195                 } else {
1196
1197                         mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL);
1198                 }
1199
1200                 start_count = -1;
1201         }
1202
1203         return IRQ_HANDLED;
1204 }
1205
1206 /*
1207  *  ia64_mca_cmc_poll
1208  *
1209  *      Poll for Corrected Machine Checks (CMCs)
1210  *
1211  * Inputs   :   dummy(unused)
1212  * Outputs  :   None
1213  *
1214  */
1215 static void
1216 ia64_mca_cmc_poll (unsigned long dummy)
1217 {
1218         /* Trigger a CMC interrupt cascade  */
1219         platform_send_ipi(first_cpu(cpu_online_map), IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0);
1220 }
1221
1222 /*
1223  *  ia64_mca_cpe_int_caller
1224  *
1225  *      Triggered by sw interrupt from CPE polling routine.  Calls
1226  *      real interrupt handler and either triggers a sw interrupt
1227  *      on the next cpu or does cleanup at the end.
1228  *
1229  * Inputs
1230  *      interrupt number
1231  *      client data arg ptr
1232  *      saved registers ptr
1233  * Outputs
1234  *      handled
1235  */
1236 #ifdef CONFIG_ACPI
1237
1238 static irqreturn_t
1239 ia64_mca_cpe_int_caller(int cpe_irq, void *arg, struct pt_regs *ptregs)
1240 {
1241         static int start_count = -1;
1242         static int poll_time = MIN_CPE_POLL_INTERVAL;
1243         unsigned int cpuid;
1244
1245         cpuid = smp_processor_id();
1246
1247         /* If first cpu, update count */
1248         if (start_count == -1)
1249                 start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CPE);
1250
1251         ia64_mca_cpe_int_handler(cpe_irq, arg, ptregs);
1252
1253         for (++cpuid ; cpuid < NR_CPUS && !cpu_online(cpuid) ; cpuid++);
1254
1255         if (cpuid < NR_CPUS) {
1256                 platform_send_ipi(cpuid, IA64_CPEP_VECTOR, IA64_IPI_DM_INT, 0);
1257         } else {
1258                 /*
1259                  * If a log was recorded, increase our polling frequency,
1260                  * otherwise, backoff or return to interrupt mode.
1261                  */
1262                 if (start_count != IA64_LOG_COUNT(SAL_INFO_TYPE_CPE)) {
1263                         poll_time = max(MIN_CPE_POLL_INTERVAL, poll_time / 2);
1264                 } else if (cpe_vector < 0) {
1265                         poll_time = min(MAX_CPE_POLL_INTERVAL, poll_time * 2);
1266                 } else {
1267                         poll_time = MIN_CPE_POLL_INTERVAL;
1268
1269                         printk(KERN_WARNING "Returning to interrupt driven CPE handler\n");
1270                         enable_irq(local_vector_to_irq(IA64_CPE_VECTOR));
1271                         cpe_poll_enabled = 0;
1272                 }
1273
1274                 if (cpe_poll_enabled)
1275                         mod_timer(&cpe_poll_timer, jiffies + poll_time);
1276                 start_count = -1;
1277         }
1278
1279         return IRQ_HANDLED;
1280 }
1281
1282 /*
1283  *  ia64_mca_cpe_poll
1284  *
1285  *      Poll for Corrected Platform Errors (CPEs), trigger interrupt
1286  *      on first cpu, from there it will trickle through all the cpus.
1287  *
1288  * Inputs   :   dummy(unused)
1289  * Outputs  :   None
1290  *
1291  */
1292 static void
1293 ia64_mca_cpe_poll (unsigned long dummy)
1294 {
1295         /* Trigger a CPE interrupt cascade  */
1296         platform_send_ipi(first_cpu(cpu_online_map), IA64_CPEP_VECTOR, IA64_IPI_DM_INT, 0);
1297 }
1298
1299 #endif /* CONFIG_ACPI */
1300
1301 static int
1302 default_monarch_init_process(struct notifier_block *self, unsigned long val, void *data)
1303 {
1304         int c;
1305         struct task_struct *g, *t;
1306         if (val != DIE_INIT_MONARCH_PROCESS)
1307                 return NOTIFY_DONE;
1308         printk(KERN_ERR "Processes interrupted by INIT -");
1309         for_each_online_cpu(c) {
1310                 struct ia64_sal_os_state *s;
1311                 t = __va(__per_cpu_mca[c] + IA64_MCA_CPU_INIT_STACK_OFFSET);
1312                 s = (struct ia64_sal_os_state *)((char *)t + MCA_SOS_OFFSET);
1313                 g = s->prev_task;
1314                 if (g) {
1315                         if (g->pid)
1316                                 printk(" %d", g->pid);
1317                         else
1318                                 printk(" %d (cpu %d task 0x%p)", g->pid, task_cpu(g), g);
1319                 }
1320         }
1321         printk("\n\n");
1322         if (read_trylock(&tasklist_lock)) {
1323                 do_each_thread (g, t) {
1324                         printk("\nBacktrace of pid %d (%s)\n", t->pid, t->comm);
1325                         show_stack(t, NULL);
1326                 } while_each_thread (g, t);
1327                 read_unlock(&tasklist_lock);
1328         }
1329         return NOTIFY_DONE;
1330 }
1331
1332 /*
1333  * C portion of the OS INIT handler
1334  *
1335  * Called from ia64_os_init_dispatch
1336  *
1337  * Inputs: pointer to pt_regs where processor info was saved.  SAL/OS state for
1338  * this event.  This code is used for both monarch and slave INIT events, see
1339  * sos->monarch.
1340  *
1341  * All INIT events switch to the INIT stack and change the previous process to
1342  * blocked status.  If one of the INIT events is the monarch then we are
1343  * probably processing the nmi button/command.  Use the monarch cpu to dump all
1344  * the processes.  The slave INIT events all spin until the monarch cpu
1345  * returns.  We can also get INIT slave events for MCA, in which case the MCA
1346  * process is the monarch.
1347  */
1348
1349 void
1350 ia64_init_handler(struct pt_regs *regs, struct switch_stack *sw,
1351                   struct ia64_sal_os_state *sos)
1352 {
1353         static atomic_t slaves;
1354         static atomic_t monarchs;
1355         task_t *previous_current;
1356         int cpu = smp_processor_id();
1357         struct ia64_mca_notify_die nd =
1358                 { .sos = sos, .monarch_cpu = &monarch_cpu };
1359
1360         oops_in_progress = 1;   /* FIXME: make printk NMI/MCA/INIT safe */
1361         console_loglevel = 15;  /* make sure printks make it to console */
1362
1363         (void) notify_die(DIE_INIT_ENTER, "INIT", regs, (long)&nd, 0, 0);
1364
1365         printk(KERN_INFO "Entered OS INIT handler. PSP=%lx cpu=%d monarch=%ld\n",
1366                 sos->proc_state_param, cpu, sos->monarch);
1367         salinfo_log_wakeup(SAL_INFO_TYPE_INIT, NULL, 0, 0);
1368
1369         previous_current = ia64_mca_modify_original_stack(regs, sw, sos, "INIT");
1370         sos->os_status = IA64_INIT_RESUME;
1371
1372         /* FIXME: Workaround for broken proms that drive all INIT events as
1373          * slaves.  The last slave that enters is promoted to be a monarch.
1374          * Remove this code in September 2006, that gives platforms a year to
1375          * fix their proms and get their customers updated.
1376          */
1377         if (!sos->monarch && atomic_add_return(1, &slaves) == num_online_cpus()) {
1378                 printk(KERN_WARNING "%s: Promoting cpu %d to monarch.\n",
1379                        __FUNCTION__, cpu);
1380                 atomic_dec(&slaves);
1381                 sos->monarch = 1;
1382         }
1383
1384         /* FIXME: Workaround for broken proms that drive all INIT events as
1385          * monarchs.  Second and subsequent monarchs are demoted to slaves.
1386          * Remove this code in September 2006, that gives platforms a year to
1387          * fix their proms and get their customers updated.
1388          */
1389         if (sos->monarch && atomic_add_return(1, &monarchs) > 1) {
1390                 printk(KERN_WARNING "%s: Demoting cpu %d to slave.\n",
1391                                __FUNCTION__, cpu);
1392                 atomic_dec(&monarchs);
1393                 sos->monarch = 0;
1394         }
1395
1396         if (!sos->monarch) {
1397                 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_INIT;
1398                 while (monarch_cpu == -1)
1399                        cpu_relax();     /* spin until monarch enters */
1400                 if (notify_die(DIE_INIT_SLAVE_ENTER, "INIT", regs, (long)&nd, 0, 0)
1401                                 == NOTIFY_STOP)
1402                         ia64_mca_spin(__FUNCTION__);
1403                 if (notify_die(DIE_INIT_SLAVE_PROCESS, "INIT", regs, (long)&nd, 0, 0)
1404                                 == NOTIFY_STOP)
1405                         ia64_mca_spin(__FUNCTION__);
1406                 while (monarch_cpu != -1)
1407                        cpu_relax();     /* spin until monarch leaves */
1408                 if (notify_die(DIE_INIT_SLAVE_LEAVE, "INIT", regs, (long)&nd, 0, 0)
1409                                 == NOTIFY_STOP)
1410                         ia64_mca_spin(__FUNCTION__);
1411                 printk("Slave on cpu %d returning to normal service.\n", cpu);
1412                 set_curr_task(cpu, previous_current);
1413                 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
1414                 atomic_dec(&slaves);
1415                 return;
1416         }
1417
1418         monarch_cpu = cpu;
1419         if (notify_die(DIE_INIT_MONARCH_ENTER, "INIT", regs, (long)&nd, 0, 0)
1420                         == NOTIFY_STOP)
1421                 ia64_mca_spin(__FUNCTION__);
1422
1423         /*
1424          * Wait for a bit.  On some machines (e.g., HP's zx2000 and zx6000, INIT can be
1425          * generated via the BMC's command-line interface, but since the console is on the
1426          * same serial line, the user will need some time to switch out of the BMC before
1427          * the dump begins.
1428          */
1429         printk("Delaying for 5 seconds...\n");
1430         udelay(5*1000000);
1431         ia64_wait_for_slaves(cpu, "INIT");
1432         /* If nobody intercepts DIE_INIT_MONARCH_PROCESS then we drop through
1433          * to default_monarch_init_process() above and just print all the
1434          * tasks.
1435          */
1436         if (notify_die(DIE_INIT_MONARCH_PROCESS, "INIT", regs, (long)&nd, 0, 0)
1437                         == NOTIFY_STOP)
1438                 ia64_mca_spin(__FUNCTION__);
1439         if (notify_die(DIE_INIT_MONARCH_LEAVE, "INIT", regs, (long)&nd, 0, 0)
1440                         == NOTIFY_STOP)
1441                 ia64_mca_spin(__FUNCTION__);
1442         printk("\nINIT dump complete.  Monarch on cpu %d returning to normal service.\n", cpu);
1443         atomic_dec(&monarchs);
1444         set_curr_task(cpu, previous_current);
1445         monarch_cpu = -1;
1446         return;
1447 }
1448
1449 static int __init
1450 ia64_mca_disable_cpe_polling(char *str)
1451 {
1452         cpe_poll_enabled = 0;
1453         return 1;
1454 }
1455
1456 __setup("disable_cpe_poll", ia64_mca_disable_cpe_polling);
1457
1458 static struct irqaction cmci_irqaction = {
1459         .handler =      ia64_mca_cmc_int_handler,
1460         .flags =        IRQF_DISABLED,
1461         .name =         "cmc_hndlr"
1462 };
1463
1464 static struct irqaction cmcp_irqaction = {
1465         .handler =      ia64_mca_cmc_int_caller,
1466         .flags =        IRQF_DISABLED,
1467         .name =         "cmc_poll"
1468 };
1469
1470 static struct irqaction mca_rdzv_irqaction = {
1471         .handler =      ia64_mca_rendez_int_handler,
1472         .flags =        IRQF_DISABLED,
1473         .name =         "mca_rdzv"
1474 };
1475
1476 static struct irqaction mca_wkup_irqaction = {
1477         .handler =      ia64_mca_wakeup_int_handler,
1478         .flags =        IRQF_DISABLED,
1479         .name =         "mca_wkup"
1480 };
1481
1482 #ifdef CONFIG_ACPI
1483 static struct irqaction mca_cpe_irqaction = {
1484         .handler =      ia64_mca_cpe_int_handler,
1485         .flags =        IRQF_DISABLED,
1486         .name =         "cpe_hndlr"
1487 };
1488
1489 static struct irqaction mca_cpep_irqaction = {
1490         .handler =      ia64_mca_cpe_int_caller,
1491         .flags =        IRQF_DISABLED,
1492         .name =         "cpe_poll"
1493 };
1494 #endif /* CONFIG_ACPI */
1495
1496 /* Minimal format of the MCA/INIT stacks.  The pseudo processes that run on
1497  * these stacks can never sleep, they cannot return from the kernel to user
1498  * space, they do not appear in a normal ps listing.  So there is no need to
1499  * format most of the fields.
1500  */
1501
1502 static void __cpuinit
1503 format_mca_init_stack(void *mca_data, unsigned long offset,
1504                 const char *type, int cpu)
1505 {
1506         struct task_struct *p = (struct task_struct *)((char *)mca_data + offset);
1507         struct thread_info *ti;
1508         memset(p, 0, KERNEL_STACK_SIZE);
1509         ti = task_thread_info(p);
1510         ti->flags = _TIF_MCA_INIT;
1511         ti->preempt_count = 1;
1512         ti->task = p;
1513         ti->cpu = cpu;
1514         p->thread_info = ti;
1515         p->state = TASK_UNINTERRUPTIBLE;
1516         cpu_set(cpu, p->cpus_allowed);
1517         INIT_LIST_HEAD(&p->tasks);
1518         p->parent = p->real_parent = p->group_leader = p;
1519         INIT_LIST_HEAD(&p->children);
1520         INIT_LIST_HEAD(&p->sibling);
1521         strncpy(p->comm, type, sizeof(p->comm)-1);
1522 }
1523
1524 /* Do per-CPU MCA-related initialization.  */
1525
1526 void __cpuinit
1527 ia64_mca_cpu_init(void *cpu_data)
1528 {
1529         void *pal_vaddr;
1530         static int first_time = 1;
1531
1532         if (first_time) {
1533                 void *mca_data;
1534                 int cpu;
1535
1536                 first_time = 0;
1537                 mca_data = alloc_bootmem(sizeof(struct ia64_mca_cpu)
1538                                          * NR_CPUS + KERNEL_STACK_SIZE);
1539                 mca_data = (void *)(((unsigned long)mca_data +
1540                                         KERNEL_STACK_SIZE - 1) &
1541                                 (-KERNEL_STACK_SIZE));
1542                 for (cpu = 0; cpu < NR_CPUS; cpu++) {
1543                         format_mca_init_stack(mca_data,
1544                                         offsetof(struct ia64_mca_cpu, mca_stack),
1545                                         "MCA", cpu);
1546                         format_mca_init_stack(mca_data,
1547                                         offsetof(struct ia64_mca_cpu, init_stack),
1548                                         "INIT", cpu);
1549                         __per_cpu_mca[cpu] = __pa(mca_data);
1550                         mca_data += sizeof(struct ia64_mca_cpu);
1551                 }
1552         }
1553
1554         /*
1555          * The MCA info structure was allocated earlier and its
1556          * physical address saved in __per_cpu_mca[cpu].  Copy that
1557          * address * to ia64_mca_data so we can access it as a per-CPU
1558          * variable.
1559          */
1560         __get_cpu_var(ia64_mca_data) = __per_cpu_mca[smp_processor_id()];
1561
1562         /*
1563          * Stash away a copy of the PTE needed to map the per-CPU page.
1564          * We may need it during MCA recovery.
1565          */
1566         __get_cpu_var(ia64_mca_per_cpu_pte) =
1567                 pte_val(mk_pte_phys(__pa(cpu_data), PAGE_KERNEL));
1568
1569         /*
1570          * Also, stash away a copy of the PAL address and the PTE
1571          * needed to map it.
1572          */
1573         pal_vaddr = efi_get_pal_addr();
1574         if (!pal_vaddr)
1575                 return;
1576         __get_cpu_var(ia64_mca_pal_base) =
1577                 GRANULEROUNDDOWN((unsigned long) pal_vaddr);
1578         __get_cpu_var(ia64_mca_pal_pte) = pte_val(mk_pte_phys(__pa(pal_vaddr),
1579                                                               PAGE_KERNEL));
1580 }
1581
1582 /*
1583  * ia64_mca_init
1584  *
1585  *  Do all the system level mca specific initialization.
1586  *
1587  *      1. Register spinloop and wakeup request interrupt vectors
1588  *
1589  *      2. Register OS_MCA handler entry point
1590  *
1591  *      3. Register OS_INIT handler entry point
1592  *
1593  *  4. Initialize MCA/CMC/INIT related log buffers maintained by the OS.
1594  *
1595  *  Note that this initialization is done very early before some kernel
1596  *  services are available.
1597  *
1598  *  Inputs  :   None
1599  *
1600  *  Outputs :   None
1601  */
1602 void __init
1603 ia64_mca_init(void)
1604 {
1605         ia64_fptr_t *init_hldlr_ptr_monarch = (ia64_fptr_t *)ia64_os_init_dispatch_monarch;
1606         ia64_fptr_t *init_hldlr_ptr_slave = (ia64_fptr_t *)ia64_os_init_dispatch_slave;
1607         ia64_fptr_t *mca_hldlr_ptr = (ia64_fptr_t *)ia64_os_mca_dispatch;
1608         int i;
1609         s64 rc;
1610         struct ia64_sal_retval isrv;
1611         u64 timeout = IA64_MCA_RENDEZ_TIMEOUT;  /* platform specific */
1612         static struct notifier_block default_init_monarch_nb = {
1613                 .notifier_call = default_monarch_init_process,
1614                 .priority = 0/* we need to notified last */
1615         };
1616
1617         IA64_MCA_DEBUG("%s: begin\n", __FUNCTION__);
1618
1619         /* Clear the Rendez checkin flag for all cpus */
1620         for(i = 0 ; i < NR_CPUS; i++)
1621                 ia64_mc_info.imi_rendez_checkin[i] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
1622
1623         /*
1624          * Register the rendezvous spinloop and wakeup mechanism with SAL
1625          */
1626
1627         /* Register the rendezvous interrupt vector with SAL */
1628         while (1) {
1629                 isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_INT,
1630                                               SAL_MC_PARAM_MECHANISM_INT,
1631                                               IA64_MCA_RENDEZ_VECTOR,
1632                                               timeout,
1633                                               SAL_MC_PARAM_RZ_ALWAYS);
1634                 rc = isrv.status;
1635                 if (rc == 0)
1636                         break;
1637                 if (rc == -2) {
1638                         printk(KERN_INFO "Increasing MCA rendezvous timeout from "
1639                                 "%ld to %ld milliseconds\n", timeout, isrv.v0);
1640                         timeout = isrv.v0;
1641                         (void) notify_die(DIE_MCA_NEW_TIMEOUT, "MCA", NULL, timeout, 0, 0);
1642                         continue;
1643                 }
1644                 printk(KERN_ERR "Failed to register rendezvous interrupt "
1645                        "with SAL (status %ld)\n", rc);
1646                 return;
1647         }
1648
1649         /* Register the wakeup interrupt vector with SAL */
1650         isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_WAKEUP,
1651                                       SAL_MC_PARAM_MECHANISM_INT,
1652                                       IA64_MCA_WAKEUP_VECTOR,
1653                                       0, 0);
1654         rc = isrv.status;
1655         if (rc) {
1656                 printk(KERN_ERR "Failed to register wakeup interrupt with SAL "
1657                        "(status %ld)\n", rc);
1658                 return;
1659         }
1660
1661         IA64_MCA_DEBUG("%s: registered MCA rendezvous spinloop and wakeup mech.\n", __FUNCTION__);
1662
1663         ia64_mc_info.imi_mca_handler        = ia64_tpa(mca_hldlr_ptr->fp);
1664         /*
1665          * XXX - disable SAL checksum by setting size to 0; should be
1666          *      ia64_tpa(ia64_os_mca_dispatch_end) - ia64_tpa(ia64_os_mca_dispatch);
1667          */
1668         ia64_mc_info.imi_mca_handler_size       = 0;
1669
1670         /* Register the os mca handler with SAL */
1671         if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_MCA,
1672                                        ia64_mc_info.imi_mca_handler,
1673                                        ia64_tpa(mca_hldlr_ptr->gp),
1674                                        ia64_mc_info.imi_mca_handler_size,
1675                                        0, 0, 0)))
1676         {
1677                 printk(KERN_ERR "Failed to register OS MCA handler with SAL "
1678                        "(status %ld)\n", rc);
1679                 return;
1680         }
1681
1682         IA64_MCA_DEBUG("%s: registered OS MCA handler with SAL at 0x%lx, gp = 0x%lx\n", __FUNCTION__,
1683                        ia64_mc_info.imi_mca_handler, ia64_tpa(mca_hldlr_ptr->gp));
1684
1685         /*
1686          * XXX - disable SAL checksum by setting size to 0, should be
1687          * size of the actual init handler in mca_asm.S.
1688          */
1689         ia64_mc_info.imi_monarch_init_handler           = ia64_tpa(init_hldlr_ptr_monarch->fp);
1690         ia64_mc_info.imi_monarch_init_handler_size      = 0;
1691         ia64_mc_info.imi_slave_init_handler             = ia64_tpa(init_hldlr_ptr_slave->fp);
1692         ia64_mc_info.imi_slave_init_handler_size        = 0;
1693
1694         IA64_MCA_DEBUG("%s: OS INIT handler at %lx\n", __FUNCTION__,
1695                        ia64_mc_info.imi_monarch_init_handler);
1696
1697         /* Register the os init handler with SAL */
1698         if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_INIT,
1699                                        ia64_mc_info.imi_monarch_init_handler,
1700                                        ia64_tpa(ia64_getreg(_IA64_REG_GP)),
1701                                        ia64_mc_info.imi_monarch_init_handler_size,
1702                                        ia64_mc_info.imi_slave_init_handler,
1703                                        ia64_tpa(ia64_getreg(_IA64_REG_GP)),
1704                                        ia64_mc_info.imi_slave_init_handler_size)))
1705         {
1706                 printk(KERN_ERR "Failed to register m/s INIT handlers with SAL "
1707                        "(status %ld)\n", rc);
1708                 return;
1709         }
1710         if (register_die_notifier(&default_init_monarch_nb)) {
1711                 printk(KERN_ERR "Failed to register default monarch INIT process\n");
1712                 return;
1713         }
1714
1715         IA64_MCA_DEBUG("%s: registered OS INIT handler with SAL\n", __FUNCTION__);
1716
1717         /*
1718          *  Configure the CMCI/P vector and handler. Interrupts for CMC are
1719          *  per-processor, so AP CMC interrupts are setup in smp_callin() (smpboot.c).
1720          */
1721         register_percpu_irq(IA64_CMC_VECTOR, &cmci_irqaction);
1722         register_percpu_irq(IA64_CMCP_VECTOR, &cmcp_irqaction);
1723         ia64_mca_cmc_vector_setup();       /* Setup vector on BSP */
1724
1725         /* Setup the MCA rendezvous interrupt vector */
1726         register_percpu_irq(IA64_MCA_RENDEZ_VECTOR, &mca_rdzv_irqaction);
1727
1728         /* Setup the MCA wakeup interrupt vector */
1729         register_percpu_irq(IA64_MCA_WAKEUP_VECTOR, &mca_wkup_irqaction);
1730
1731 #ifdef CONFIG_ACPI
1732         /* Setup the CPEI/P handler */
1733         register_percpu_irq(IA64_CPEP_VECTOR, &mca_cpep_irqaction);
1734 #endif
1735
1736         /* Initialize the areas set aside by the OS to buffer the
1737          * platform/processor error states for MCA/INIT/CMC
1738          * handling.
1739          */
1740         ia64_log_init(SAL_INFO_TYPE_MCA);
1741         ia64_log_init(SAL_INFO_TYPE_INIT);
1742         ia64_log_init(SAL_INFO_TYPE_CMC);
1743         ia64_log_init(SAL_INFO_TYPE_CPE);
1744
1745         mca_init = 1;
1746         printk(KERN_INFO "MCA related initialization done\n");
1747 }
1748
1749 /*
1750  * ia64_mca_late_init
1751  *
1752  *      Opportunity to setup things that require initialization later
1753  *      than ia64_mca_init.  Setup a timer to poll for CPEs if the
1754  *      platform doesn't support an interrupt driven mechanism.
1755  *
1756  *  Inputs  :   None
1757  *  Outputs :   Status
1758  */
1759 static int __init
1760 ia64_mca_late_init(void)
1761 {
1762         if (!mca_init)
1763                 return 0;
1764
1765         /* Setup the CMCI/P vector and handler */
1766         init_timer(&cmc_poll_timer);
1767         cmc_poll_timer.function = ia64_mca_cmc_poll;
1768
1769         /* Unmask/enable the vector */
1770         cmc_polling_enabled = 0;
1771         schedule_work(&cmc_enable_work);
1772
1773         IA64_MCA_DEBUG("%s: CMCI/P setup and enabled.\n", __FUNCTION__);
1774
1775 #ifdef CONFIG_ACPI
1776         /* Setup the CPEI/P vector and handler */
1777         cpe_vector = acpi_request_vector(ACPI_INTERRUPT_CPEI);
1778         init_timer(&cpe_poll_timer);
1779         cpe_poll_timer.function = ia64_mca_cpe_poll;
1780
1781         {
1782                 irq_desc_t *desc;
1783                 unsigned int irq;
1784
1785                 if (cpe_vector >= 0) {
1786                         /* If platform supports CPEI, enable the irq. */
1787                         cpe_poll_enabled = 0;
1788                         for (irq = 0; irq < NR_IRQS; ++irq)
1789                                 if (irq_to_vector(irq) == cpe_vector) {
1790                                         desc = irq_desc + irq;
1791                                         desc->status |= IRQ_PER_CPU;
1792                                         setup_irq(irq, &mca_cpe_irqaction);
1793                                         ia64_cpe_irq = irq;
1794                                 }
1795                         ia64_mca_register_cpev(cpe_vector);
1796                         IA64_MCA_DEBUG("%s: CPEI/P setup and enabled.\n", __FUNCTION__);
1797                 } else {
1798                         /* If platform doesn't support CPEI, get the timer going. */
1799                         if (cpe_poll_enabled) {
1800                                 ia64_mca_cpe_poll(0UL);
1801                                 IA64_MCA_DEBUG("%s: CPEP setup and enabled.\n", __FUNCTION__);
1802                         }
1803                 }
1804         }
1805 #endif
1806
1807         return 0;
1808 }
1809
1810 device_initcall(ia64_mca_late_init);