arch/ia64/kernel/cyclone.c

   1 #include <linux/module.h>
   2 #include <linux/smp.h>
   3 #include <linux/time.h>
   4 #include <linux/errno.h>
   5 #include <linux/timex.h>
   6 #include <linux/clocksource.h>
   7 #include <asm/io.h>
   8
   9 /* IBM Summit (EXA) Cyclone counter code*/
  10 #define CYCLONE_CBAR_ADDR 0xFEB00CD0
  11 #define CYCLONE_PMCC_OFFSET 0x51A0
  12 #define CYCLONE_MPMC_OFFSET 0x51D0
  13 #define CYCLONE_MPCS_OFFSET 0x51A8
  14 #define CYCLONE_TIMER_FREQ 100000000
  15
  16 int use_cyclone;
  17 void __init cyclone_setup(void)
  18 {
  19         use_cyclone = 1;
  20 }
  21
  22 static void __iomem *cyclone_mc;
  23
  24 static cycle_t read_cyclone(void)
  25 {
  26         return (cycle_t)readq((void __iomem *)cyclone_mc);
  27 }
  28
  29 static struct clocksource clocksource_cyclone = {
  30         .name           = "cyclone",
  31         .rating         = 300,
  32         .read           = read_cyclone,
  33         .mask           = (1LL << 40) - 1,
  34         .mult           = 0, /*to be caluclated*/
  35         .shift          = 16,
  36         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
  37 };
  38
  39 int __init init_cyclone_clock(void)
  40 {
  41         u64* reg;
  42         u64 base;       /* saved cyclone base address */
  43         u64 offset;     /* offset from pageaddr to cyclone_timer register */
  44         int i;
  45         u32* volatile cyclone_timer;    /* Cyclone MPMC0 register */
  46
  47         if (!use_cyclone)
  48                 return 0;
  49
  50         printk(KERN_INFO "Summit chipset: Starting Cyclone Counter.\n");
  51
  52         /* find base address */
  53         offset = (CYCLONE_CBAR_ADDR);
  54         reg = (u64*)ioremap_nocache(offset, sizeof(u64));
  55         if(!reg){
  56                 printk(KERN_ERR "Summit chipset: Could not find valid CBAR"
  57                                 " register.\n");
  58                 use_cyclone = 0;
  59                 return -ENODEV;
  60         }
  61         base = readq(reg);
  62         if(!base){
  63                 printk(KERN_ERR "Summit chipset: Could not find valid CBAR"
  64                                 " value.\n");
  65                 use_cyclone = 0;
  66                 return -ENODEV;
  67         }
  68         iounmap(reg);
  69
  70         /* setup PMCC */
  71         offset = (base + CYCLONE_PMCC_OFFSET);
  72         reg = (u64*)ioremap_nocache(offset, sizeof(u64));
  73         if(!reg){
  74                 printk(KERN_ERR "Summit chipset: Could not find valid PMCC"
  75                                 " register.\n");
  76                 use_cyclone = 0;
  77                 return -ENODEV;
  78         }
  79         writel(0x00000001,reg);
  80         iounmap(reg);
  81
  82         /* setup MPCS */
  83         offset = (base + CYCLONE_MPCS_OFFSET);
  84         reg = (u64*)ioremap_nocache(offset, sizeof(u64));
  85         if(!reg){
  86                 printk(KERN_ERR "Summit chipset: Could not find valid MPCS"
  87                                 " register.\n");
  88                 use_cyclone = 0;
  89                 return -ENODEV;
  90         }
  91         writel(0x00000001,reg);
  92         iounmap(reg);
  93
  94         /* map in cyclone_timer */
  95         offset = (base + CYCLONE_MPMC_OFFSET);
  96         cyclone_timer = (u32*)ioremap_nocache(offset, sizeof(u32));
  97         if(!cyclone_timer){
  98                 printk(KERN_ERR "Summit chipset: Could not find valid MPMC"
  99                                 " register.\n");
 100                 use_cyclone = 0;
 101                 return -ENODEV;
 102         }
 103
 104         /*quick test to make sure its ticking*/
 105         for(i=0; i<3; i++){
 106                 u32 old = readl(cyclone_timer);
 107                 int stall = 100;
 108                 while(stall--) barrier();
 109                 if(readl(cyclone_timer) == old){
 110                         printk(KERN_ERR "Summit chipset: Counter not counting!"
 111                                         " DISABLED\n");
 112                         iounmap(cyclone_timer);
 113                         cyclone_timer = 0;
 114                         use_cyclone = 0;
 115                         return -ENODEV;
 116                 }
 117         }
 118         /* initialize last tick */
 119         cyclone_mc = cyclone_timer;
 120         clocksource_cyclone.fsys_mmio = cyclone_timer;
 121         clocksource_cyclone.mult = clocksource_hz2mult(CYCLONE_TIMER_FREQ,
 122                                                 clocksource_cyclone.shift);
 123         clocksource_register(&clocksource_cyclone);
 124
 125         return 0;
 126 }
 127
 128 __initcall(init_cyclone_clock);