2 * Low-Level PCI Support for PC -- Routing of Interrupts
4 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
7 #include <linux/config.h>
8 #include <linux/types.h>
9 #include <linux/kernel.h>
10 #include <linux/pci.h>
11 #include <linux/init.h>
12 #include <linux/slab.h>
13 #include <linux/interrupt.h>
14 #include <linux/irq.h>
15 #include <linux/dmi.h>
18 #include <asm/io_apic.h>
19 #include <asm/hw_irq.h>
20 #include <linux/acpi.h>
24 #define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
25 #define PIRQ_VERSION 0x0100
27 static int broken_hp_bios_irq9;
28 static int acer_tm360_irqrouting;
30 static struct irq_routing_table *pirq_table;
32 static int pirq_enable_irq(struct pci_dev *dev);
35 * Never use: 0, 1, 2 (timer, keyboard, and cascade)
36 * Avoid using: 13, 14 and 15 (FP error and IDE).
37 * Penalize: 3, 4, 6, 7, 12 (known ISA uses: serial, floppy, parallel and mouse)
39 unsigned int pcibios_irq_mask = 0xfff8;
41 static int pirq_penalty[16] = {
42 1000000, 1000000, 1000000, 1000, 1000, 0, 1000, 1000,
43 0, 0, 0, 0, 1000, 100000, 100000, 100000
49 int (*get)(struct pci_dev *router, struct pci_dev *dev, int pirq);
50 int (*set)(struct pci_dev *router, struct pci_dev *dev, int pirq, int new);
53 struct irq_router_handler {
55 int (*probe)(struct irq_router *r, struct pci_dev *router, u16 device);
58 int (*pcibios_enable_irq)(struct pci_dev *dev) = NULL;
59 void (*pcibios_disable_irq)(struct pci_dev *dev) = NULL;
62 * Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table.
65 static struct irq_routing_table * __init pirq_find_routing_table(void)
68 struct irq_routing_table *rt;
72 for(addr = (u8 *) __va(0xf0000); addr < (u8 *) __va(0x100000); addr += 16) {
73 rt = (struct irq_routing_table *) addr;
74 if (rt->signature != PIRQ_SIGNATURE ||
75 rt->version != PIRQ_VERSION ||
77 rt->size < sizeof(struct irq_routing_table))
80 for(i=0; i<rt->size; i++)
83 DBG("PCI: Interrupt Routing Table found at 0x%p\n", rt);
91 * If we have a IRQ routing table, use it to search for peer host
92 * bridges. It's a gross hack, but since there are no other known
93 * ways how to get a list of buses, we have to go this way.
96 static void __init pirq_peer_trick(void)
98 struct irq_routing_table *rt = pirq_table;
103 memset(busmap, 0, sizeof(busmap));
104 for(i=0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) {
109 DBG("%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot);
111 DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap);
117 for(i = 1; i < 256; i++) {
118 if (!busmap[i] || pci_find_bus(0, i))
120 if (pci_scan_bus(i, &pci_root_ops, NULL))
121 printk(KERN_INFO "PCI: Discovered primary peer bus %02x [IRQ]\n", i);
123 pcibios_last_bus = -1;
127 * Code for querying and setting of IRQ routes on various interrupt routers.
130 void eisa_set_level_irq(unsigned int irq)
132 unsigned char mask = 1 << (irq & 7);
133 unsigned int port = 0x4d0 + (irq >> 3);
135 static u16 eisa_irq_mask;
137 if (irq >= 16 || (1 << irq) & eisa_irq_mask)
140 eisa_irq_mask |= (1 << irq);
141 printk("PCI: setting IRQ %u as level-triggered\n", irq);
145 outb(val | mask, port);
150 * Common IRQ routing practice: nybbles in config space,
151 * offset by some magic constant.
153 static unsigned int read_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr)
156 unsigned reg = offset + (nr >> 1);
158 pci_read_config_byte(router, reg, &x);
159 return (nr & 1) ? (x >> 4) : (x & 0xf);
162 static void write_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr, unsigned int val)
165 unsigned reg = offset + (nr >> 1);
167 pci_read_config_byte(router, reg, &x);
168 x = (nr & 1) ? ((x & 0x0f) | (val << 4)) : ((x & 0xf0) | val);
169 pci_write_config_byte(router, reg, x);
173 * ALI pirq entries are damn ugly, and completely undocumented.
174 * This has been figured out from pirq tables, and it's not a pretty
177 static int pirq_ali_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
179 static unsigned char irqmap[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 };
181 return irqmap[read_config_nybble(router, 0x48, pirq-1)];
184 static int pirq_ali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
186 static unsigned char irqmap[16] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 };
187 unsigned int val = irqmap[irq];
190 write_config_nybble(router, 0x48, pirq-1, val);
197 * The Intel PIIX4 pirq rules are fairly simple: "pirq" is
198 * just a pointer to the config space.
200 static int pirq_piix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
204 pci_read_config_byte(router, pirq, &x);
205 return (x < 16) ? x : 0;
208 static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
210 pci_write_config_byte(router, pirq, irq);
215 * The VIA pirq rules are nibble-based, like ALI,
216 * but without the ugly irq number munging.
217 * However, PIRQD is in the upper instead of lower 4 bits.
219 static int pirq_via_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
221 return read_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq);
224 static int pirq_via_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
226 write_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq, irq);
231 * ITE 8330G pirq rules are nibble-based
232 * FIXME: pirqmap may be { 1, 0, 3, 2 },
233 * 2+3 are both mapped to irq 9 on my system
235 static int pirq_ite_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
237 static unsigned char pirqmap[4] = { 1, 0, 2, 3 };
238 return read_config_nybble(router,0x43, pirqmap[pirq-1]);
241 static int pirq_ite_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
243 static unsigned char pirqmap[4] = { 1, 0, 2, 3 };
244 write_config_nybble(router, 0x43, pirqmap[pirq-1], irq);
249 * OPTI: high four bits are nibble pointer..
250 * I wonder what the low bits do?
252 static int pirq_opti_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
254 return read_config_nybble(router, 0xb8, pirq >> 4);
257 static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
259 write_config_nybble(router, 0xb8, pirq >> 4, irq);
264 * Cyrix: nibble offset 0x5C
265 * 0x5C bits 7:4 is INTB bits 3:0 is INTA
266 * 0x5D bits 7:4 is INTD bits 3:0 is INTC
268 static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
270 return read_config_nybble(router, 0x5C, (pirq-1)^1);
273 static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
275 write_config_nybble(router, 0x5C, (pirq-1)^1, irq);
280 * PIRQ routing for SiS 85C503 router used in several SiS chipsets.
281 * We have to deal with the following issues here:
282 * - vendors have different ideas about the meaning of link values
283 * - some onboard devices (integrated in the chipset) have special
284 * links and are thus routed differently (i.e. not via PCI INTA-INTD)
285 * - different revision of the router have a different layout for
286 * the routing registers, particularly for the onchip devices
288 * For all routing registers the common thing is we have one byte
289 * per routeable link which is defined as:
290 * bit 7 IRQ mapping enabled (0) or disabled (1)
291 * bits [6:4] reserved (sometimes used for onchip devices)
292 * bits [3:0] IRQ to map to
293 * allowed: 3-7, 9-12, 14-15
294 * reserved: 0, 1, 2, 8, 13
296 * The config-space registers located at 0x41/0x42/0x43/0x44 are
297 * always used to route the normal PCI INT A/B/C/D respectively.
298 * Apparently there are systems implementing PCI routing table using
299 * link values 0x01-0x04 and others using 0x41-0x44 for PCI INTA..D.
300 * We try our best to handle both link mappings.
302 * Currently (2003-05-21) it appears most SiS chipsets follow the
303 * definition of routing registers from the SiS-5595 southbridge.
304 * According to the SiS 5595 datasheets the revision id's of the
305 * router (ISA-bridge) should be 0x01 or 0xb0.
307 * Furthermore we've also seen lspci dumps with revision 0x00 and 0xb1.
308 * Looks like these are used in a number of SiS 5xx/6xx/7xx chipsets.
309 * They seem to work with the current routing code. However there is
310 * some concern because of the two USB-OHCI HCs (original SiS 5595
311 * had only one). YMMV.
313 * Onchip routing for router rev-id 0x01/0xb0 and probably 0x00/0xb1:
316 * bits [6:5] must be written 01
317 * bit 4 channel-select primary (0), secondary (1)
320 * bit 6 OHCI function disabled (0), enabled (1)
322 * 0x6a: ACPI/SCI IRQ: bits 4-6 reserved
324 * 0x7e: Data Acq. Module IRQ - bits 4-6 reserved
326 * We support USBIRQ (in addition to INTA-INTD) and keep the
327 * IDE, ACPI and DAQ routing untouched as set by the BIOS.
329 * Currently the only reported exception is the new SiS 65x chipset
330 * which includes the SiS 69x southbridge. Here we have the 85C503
331 * router revision 0x04 and there are changes in the register layout
332 * mostly related to the different USB HCs with USB 2.0 support.
334 * Onchip routing for router rev-id 0x04 (try-and-error observation)
336 * 0x60/0x61/0x62/0x63: 1xEHCI and 3xOHCI (companion) USB-HCs
337 * bit 6-4 are probably unused, not like 5595
340 #define PIRQ_SIS_IRQ_MASK 0x0f
341 #define PIRQ_SIS_IRQ_DISABLE 0x80
342 #define PIRQ_SIS_USB_ENABLE 0x40
344 static int pirq_sis_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
350 if (reg >= 0x01 && reg <= 0x04)
352 pci_read_config_byte(router, reg, &x);
353 return (x & PIRQ_SIS_IRQ_DISABLE) ? 0 : (x & PIRQ_SIS_IRQ_MASK);
356 static int pirq_sis_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
362 if (reg >= 0x01 && reg <= 0x04)
364 pci_read_config_byte(router, reg, &x);
365 x &= ~(PIRQ_SIS_IRQ_MASK | PIRQ_SIS_IRQ_DISABLE);
366 x |= irq ? irq: PIRQ_SIS_IRQ_DISABLE;
367 pci_write_config_byte(router, reg, x);
373 * VLSI: nibble offset 0x74 - educated guess due to routing table and
374 * config space of VLSI 82C534 PCI-bridge/router (1004:0102)
375 * Tested on HP OmniBook 800 covering PIRQ 1, 2, 4, 8 for onboard
376 * devices, PIRQ 3 for non-pci(!) soundchip and (untested) PIRQ 6
377 * for the busbridge to the docking station.
380 static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
383 printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq);
386 return read_config_nybble(router, 0x74, pirq-1);
389 static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
392 printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq);
395 write_config_nybble(router, 0x74, pirq-1, irq);
400 * ServerWorks: PCI interrupts mapped to system IRQ lines through Index
401 * and Redirect I/O registers (0x0c00 and 0x0c01). The Index register
402 * format is (PCIIRQ## | 0x10), e.g.: PCIIRQ10=0x1a. The Redirect
403 * register is a straight binary coding of desired PIC IRQ (low nibble).
405 * The 'link' value in the PIRQ table is already in the correct format
406 * for the Index register. There are some special index values:
407 * 0x00 for ACPI (SCI), 0x01 for USB, 0x02 for IDE0, 0x04 for IDE1,
408 * and 0x03 for SMBus.
410 static int pirq_serverworks_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
413 return inb(0xc01) & 0xf;
416 static int pirq_serverworks_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
423 /* Support for AMD756 PCI IRQ Routing
424 * Jhon H. Caicedo <jhcaiced@osso.org.co>
425 * Jun/21/2001 0.2.0 Release, fixed to use "nybble" functions... (jhcaiced)
426 * Jun/19/2001 Alpha Release 0.1.0 (jhcaiced)
427 * The AMD756 pirq rules are nibble-based
428 * offset 0x56 0-3 PIRQA 4-7 PIRQB
429 * offset 0x57 0-3 PIRQC 4-7 PIRQD
431 static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
437 irq = read_config_nybble(router, 0x56, pirq - 1);
439 printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d get irq : %2d\n",
440 dev->vendor, dev->device, pirq, irq);
444 static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
446 printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d SET irq : %2d\n",
447 dev->vendor, dev->device, pirq, irq);
450 write_config_nybble(router, 0x56, pirq - 1, irq);
455 #ifdef CONFIG_PCI_BIOS
457 static int pirq_bios_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
459 struct pci_dev *bridge;
460 int pin = pci_get_interrupt_pin(dev, &bridge);
461 return pcibios_set_irq_routing(bridge, pin, irq);
466 static __init int intel_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
468 static struct pci_device_id pirq_440gx[] = {
469 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0) },
470 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2) },
474 /* 440GX has a proprietary PIRQ router -- don't use it */
475 if (pci_dev_present(pirq_440gx))
480 case PCI_DEVICE_ID_INTEL_82371FB_0:
481 case PCI_DEVICE_ID_INTEL_82371SB_0:
482 case PCI_DEVICE_ID_INTEL_82371AB_0:
483 case PCI_DEVICE_ID_INTEL_82371MX:
484 case PCI_DEVICE_ID_INTEL_82443MX_0:
485 case PCI_DEVICE_ID_INTEL_82801AA_0:
486 case PCI_DEVICE_ID_INTEL_82801AB_0:
487 case PCI_DEVICE_ID_INTEL_82801BA_0:
488 case PCI_DEVICE_ID_INTEL_82801BA_10:
489 case PCI_DEVICE_ID_INTEL_82801CA_0:
490 case PCI_DEVICE_ID_INTEL_82801CA_12:
491 case PCI_DEVICE_ID_INTEL_82801DB_0:
492 case PCI_DEVICE_ID_INTEL_82801E_0:
493 case PCI_DEVICE_ID_INTEL_82801EB_0:
494 case PCI_DEVICE_ID_INTEL_ESB_1:
495 case PCI_DEVICE_ID_INTEL_ICH6_0:
496 case PCI_DEVICE_ID_INTEL_ICH6_1:
497 case PCI_DEVICE_ID_INTEL_ICH7_0:
498 case PCI_DEVICE_ID_INTEL_ICH7_1:
499 case PCI_DEVICE_ID_INTEL_ICH7_30:
500 case PCI_DEVICE_ID_INTEL_ICH7_31:
501 case PCI_DEVICE_ID_INTEL_ESB2_0:
502 r->name = "PIIX/ICH";
503 r->get = pirq_piix_get;
504 r->set = pirq_piix_set;
510 static __init int via_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
512 /* FIXME: We should move some of the quirk fixup stuff here */
515 case PCI_DEVICE_ID_VIA_82C586_0:
516 case PCI_DEVICE_ID_VIA_82C596:
517 case PCI_DEVICE_ID_VIA_82C686:
518 case PCI_DEVICE_ID_VIA_8231:
519 /* FIXME: add new ones for 8233/5 */
521 r->get = pirq_via_get;
522 r->set = pirq_via_set;
528 static __init int vlsi_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
532 case PCI_DEVICE_ID_VLSI_82C534:
533 r->name = "VLSI 82C534";
534 r->get = pirq_vlsi_get;
535 r->set = pirq_vlsi_set;
542 static __init int serverworks_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
546 case PCI_DEVICE_ID_SERVERWORKS_OSB4:
547 case PCI_DEVICE_ID_SERVERWORKS_CSB5:
548 r->name = "ServerWorks";
549 r->get = pirq_serverworks_get;
550 r->set = pirq_serverworks_set;
556 static __init int sis_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
558 if (device != PCI_DEVICE_ID_SI_503)
562 r->get = pirq_sis_get;
563 r->set = pirq_sis_set;
567 static __init int cyrix_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
571 case PCI_DEVICE_ID_CYRIX_5520:
573 r->get = pirq_cyrix_get;
574 r->set = pirq_cyrix_set;
580 static __init int opti_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
584 case PCI_DEVICE_ID_OPTI_82C700:
586 r->get = pirq_opti_get;
587 r->set = pirq_opti_set;
593 static __init int ite_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
597 case PCI_DEVICE_ID_ITE_IT8330G_0:
599 r->get = pirq_ite_get;
600 r->set = pirq_ite_set;
606 static __init int ali_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
610 case PCI_DEVICE_ID_AL_M1533:
611 case PCI_DEVICE_ID_AL_M1563:
612 printk("PCI: Using ALI IRQ Router\n");
614 r->get = pirq_ali_get;
615 r->set = pirq_ali_set;
621 static __init int amd_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
625 case PCI_DEVICE_ID_AMD_VIPER_740B:
628 case PCI_DEVICE_ID_AMD_VIPER_7413:
631 case PCI_DEVICE_ID_AMD_VIPER_7443:
637 r->get = pirq_amd756_get;
638 r->set = pirq_amd756_set;
642 static __initdata struct irq_router_handler pirq_routers[] = {
643 { PCI_VENDOR_ID_INTEL, intel_router_probe },
644 { PCI_VENDOR_ID_AL, ali_router_probe },
645 { PCI_VENDOR_ID_ITE, ite_router_probe },
646 { PCI_VENDOR_ID_VIA, via_router_probe },
647 { PCI_VENDOR_ID_OPTI, opti_router_probe },
648 { PCI_VENDOR_ID_SI, sis_router_probe },
649 { PCI_VENDOR_ID_CYRIX, cyrix_router_probe },
650 { PCI_VENDOR_ID_VLSI, vlsi_router_probe },
651 { PCI_VENDOR_ID_SERVERWORKS, serverworks_router_probe },
652 { PCI_VENDOR_ID_AMD, amd_router_probe },
653 /* Someone with docs needs to add the ATI Radeon IGP */
656 static struct irq_router pirq_router;
657 static struct pci_dev *pirq_router_dev;
661 * FIXME: should we have an option to say "generic for
665 static void __init pirq_find_router(struct irq_router *r)
667 struct irq_routing_table *rt = pirq_table;
668 struct irq_router_handler *h;
670 #ifdef CONFIG_PCI_BIOS
671 if (!rt->signature) {
672 printk(KERN_INFO "PCI: Using BIOS for IRQ routing\n");
673 r->set = pirq_bios_set;
679 /* Default unless a driver reloads it */
684 DBG("PCI: Attempting to find IRQ router for %04x:%04x\n",
685 rt->rtr_vendor, rt->rtr_device);
687 pirq_router_dev = pci_find_slot(rt->rtr_bus, rt->rtr_devfn);
688 if (!pirq_router_dev) {
689 DBG("PCI: Interrupt router not found at %02x:%02x\n", rt->rtr_bus, rt->rtr_devfn);
693 for( h = pirq_routers; h->vendor; h++) {
694 /* First look for a router match */
695 if (rt->rtr_vendor == h->vendor && h->probe(r, pirq_router_dev, rt->rtr_device))
697 /* Fall back to a device match */
698 if (pirq_router_dev->vendor == h->vendor && h->probe(r, pirq_router_dev, pirq_router_dev->device))
701 printk(KERN_INFO "PCI: Using IRQ router %s [%04x/%04x] at %s\n",
703 pirq_router_dev->vendor,
704 pirq_router_dev->device,
705 pci_name(pirq_router_dev));
708 static struct irq_info *pirq_get_info(struct pci_dev *dev)
710 struct irq_routing_table *rt = pirq_table;
711 int entries = (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info);
712 struct irq_info *info;
714 for (info = rt->slots; entries--; info++)
715 if (info->bus == dev->bus->number && PCI_SLOT(info->devfn) == PCI_SLOT(dev->devfn))
720 static int pcibios_lookup_irq(struct pci_dev *dev, int assign)
723 struct irq_info *info;
727 struct irq_router *r = &pirq_router;
728 struct pci_dev *dev2 = NULL;
732 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
734 DBG(" -> no interrupt pin\n");
739 /* Find IRQ routing entry */
744 DBG("IRQ for %s[%c]", pci_name(dev), 'A' + pin);
745 info = pirq_get_info(dev);
747 DBG(" -> not found in routing table\n");
750 pirq = info->irq[pin].link;
751 mask = info->irq[pin].bitmap;
753 DBG(" -> not routed\n");
756 DBG(" -> PIRQ %02x, mask %04x, excl %04x", pirq, mask, pirq_table->exclusive_irqs);
757 mask &= pcibios_irq_mask;
759 /* Work around broken HP Pavilion Notebooks which assign USB to
760 IRQ 9 even though it is actually wired to IRQ 11 */
762 if (broken_hp_bios_irq9 && pirq == 0x59 && dev->irq == 9) {
764 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
765 r->set(pirq_router_dev, dev, pirq, 11);
768 /* same for Acer Travelmate 360, but with CB and irq 11 -> 10 */
769 if (acer_tm360_irqrouting && dev->irq == 11 && dev->vendor == PCI_VENDOR_ID_O2) {
772 dev->irq = r->get(pirq_router_dev, dev, pirq);
773 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
777 * Find the best IRQ to assign: use the one
778 * reported by the device if possible.
781 if (!((1 << newirq) & mask)) {
782 if ( pci_probe & PCI_USE_PIRQ_MASK) newirq = 0;
783 else printk(KERN_WARNING "PCI: IRQ %i for device %s doesn't match PIRQ mask - try pci=usepirqmask\n", newirq, pci_name(dev));
785 if (!newirq && assign) {
786 for (i = 0; i < 16; i++) {
787 if (!(mask & (1 << i)))
789 if (pirq_penalty[i] < pirq_penalty[newirq] && can_request_irq(i, SA_SHIRQ))
793 DBG(" -> newirq=%d", newirq);
795 /* Check if it is hardcoded */
796 if ((pirq & 0xf0) == 0xf0) {
798 DBG(" -> hardcoded IRQ %d\n", irq);
800 } else if ( r->get && (irq = r->get(pirq_router_dev, dev, pirq)) && \
801 ((!(pci_probe & PCI_USE_PIRQ_MASK)) || ((1 << irq) & mask)) ) {
802 DBG(" -> got IRQ %d\n", irq);
804 } else if (newirq && r->set && (dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) {
805 DBG(" -> assigning IRQ %d", newirq);
806 if (r->set(pirq_router_dev, dev, pirq, newirq)) {
807 eisa_set_level_irq(newirq);
815 DBG(" ... failed\n");
816 if (newirq && mask == (1 << newirq)) {
822 printk(KERN_INFO "PCI: %s IRQ %d for device %s\n", msg, irq, pci_name(dev));
824 /* Update IRQ for all devices with the same pirq value */
825 while ((dev2 = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev2)) != NULL) {
826 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin);
830 info = pirq_get_info(dev2);
833 if (info->irq[pin].link == pirq) {
834 /* We refuse to override the dev->irq information. Give a warning! */
835 if ( dev2->irq && dev2->irq != irq && \
836 (!(pci_probe & PCI_USE_PIRQ_MASK) || \
837 ((1 << dev2->irq) & mask)) ) {
838 #ifndef CONFIG_PCI_MSI
839 printk(KERN_INFO "IRQ routing conflict for %s, have irq %d, want irq %d\n",
840 pci_name(dev2), dev2->irq, irq);
847 printk(KERN_INFO "PCI: Sharing IRQ %d with %s\n", irq, pci_name(dev2));
853 static void __init pcibios_fixup_irqs(void)
855 struct pci_dev *dev = NULL;
858 DBG("PCI: IRQ fixup\n");
859 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
861 * If the BIOS has set an out of range IRQ number, just ignore it.
862 * Also keep track of which IRQ's are already in use.
864 if (dev->irq >= 16) {
865 DBG("%s: ignoring bogus IRQ %d\n", pci_name(dev), dev->irq);
868 /* If the IRQ is already assigned to a PCI device, ignore its ISA use penalty */
869 if (pirq_penalty[dev->irq] >= 100 && pirq_penalty[dev->irq] < 100000)
870 pirq_penalty[dev->irq] = 0;
871 pirq_penalty[dev->irq]++;
875 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
876 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
877 #ifdef CONFIG_X86_IO_APIC
879 * Recalculate IRQ numbers if we use the I/O APIC.
881 if (io_apic_assign_pci_irqs)
886 pin--; /* interrupt pins are numbered starting from 1 */
887 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, PCI_SLOT(dev->devfn), pin);
889 * Busses behind bridges are typically not listed in the MP-table.
890 * In this case we have to look up the IRQ based on the parent bus,
891 * parent slot, and pin number. The SMP code detects such bridged
892 * busses itself so we should get into this branch reliably.
894 if (irq < 0 && dev->bus->parent) { /* go back to the bridge */
895 struct pci_dev * bridge = dev->bus->self;
897 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
898 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
899 PCI_SLOT(bridge->devfn), pin);
901 printk(KERN_WARNING "PCI: using PPB %s[%c] to get irq %d\n",
902 pci_name(bridge), 'A' + pin, irq);
905 if (use_pci_vector() &&
906 !platform_legacy_irq(irq))
907 irq = IO_APIC_VECTOR(irq);
909 printk(KERN_INFO "PCI->APIC IRQ transform: %s[%c] -> IRQ %d\n",
910 pci_name(dev), 'A' + pin, irq);
917 * Still no IRQ? Try to lookup one...
919 if (pin && !dev->irq)
920 pcibios_lookup_irq(dev, 0);
925 * Work around broken HP Pavilion Notebooks which assign USB to
926 * IRQ 9 even though it is actually wired to IRQ 11
928 static int __init fix_broken_hp_bios_irq9(struct dmi_system_id *d)
930 if (!broken_hp_bios_irq9) {
931 broken_hp_bios_irq9 = 1;
932 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n", d->ident);
938 * Work around broken Acer TravelMate 360 Notebooks which assign
939 * Cardbus to IRQ 11 even though it is actually wired to IRQ 10
941 static int __init fix_acer_tm360_irqrouting(struct dmi_system_id *d)
943 if (!acer_tm360_irqrouting) {
944 acer_tm360_irqrouting = 1;
945 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n", d->ident);
950 static struct dmi_system_id __initdata pciirq_dmi_table[] = {
952 .callback = fix_broken_hp_bios_irq9,
953 .ident = "HP Pavilion N5400 Series Laptop",
955 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
956 DMI_MATCH(DMI_BIOS_VERSION, "GE.M1.03"),
957 DMI_MATCH(DMI_PRODUCT_VERSION, "HP Pavilion Notebook Model GE"),
958 DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"),
962 .callback = fix_acer_tm360_irqrouting,
963 .ident = "Acer TravelMate 36x Laptop",
965 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
966 DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate 360"),
972 static int __init pcibios_irq_init(void)
974 DBG("PCI: IRQ init\n");
976 if (pcibios_enable_irq || raw_pci_ops == NULL)
979 dmi_check_system(pciirq_dmi_table);
981 pirq_table = pirq_find_routing_table();
983 #ifdef CONFIG_PCI_BIOS
984 if (!pirq_table && (pci_probe & PCI_BIOS_IRQ_SCAN))
985 pirq_table = pcibios_get_irq_routing_table();
989 pirq_find_router(&pirq_router);
990 if (pirq_table->exclusive_irqs) {
993 if (!(pirq_table->exclusive_irqs & (1 << i)))
994 pirq_penalty[i] += 100;
996 /* If we're using the I/O APIC, avoid using the PCI IRQ routing table */
997 if (io_apic_assign_pci_irqs)
1001 pcibios_enable_irq = pirq_enable_irq;
1003 pcibios_fixup_irqs();
1007 subsys_initcall(pcibios_irq_init);
1010 static void pirq_penalize_isa_irq(int irq, int active)
1013 * If any ISAPnP device reports an IRQ in its list of possible
1014 * IRQ's, we try to avoid assigning it to PCI devices.
1018 pirq_penalty[irq] += 1000;
1020 pirq_penalty[irq] += 100;
1024 void pcibios_penalize_isa_irq(int irq, int active)
1026 #ifdef CONFIG_ACPI_PCI
1028 acpi_penalize_isa_irq(irq, active);
1031 pirq_penalize_isa_irq(irq, active);
1034 static int pirq_enable_irq(struct pci_dev *dev)
1037 struct pci_dev *temp_dev;
1039 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1040 if (pin && !pcibios_lookup_irq(dev, 1) && !dev->irq) {
1043 pin--; /* interrupt pins are numbered starting from 1 */
1045 if (io_apic_assign_pci_irqs) {
1048 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, PCI_SLOT(dev->devfn), pin);
1050 * Busses behind bridges are typically not listed in the MP-table.
1051 * In this case we have to look up the IRQ based on the parent bus,
1052 * parent slot, and pin number. The SMP code detects such bridged
1053 * busses itself so we should get into this branch reliably.
1056 while (irq < 0 && dev->bus->parent) { /* go back to the bridge */
1057 struct pci_dev * bridge = dev->bus->self;
1059 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
1060 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
1061 PCI_SLOT(bridge->devfn), pin);
1063 printk(KERN_WARNING "PCI: using PPB %s[%c] to get irq %d\n",
1064 pci_name(bridge), 'A' + pin, irq);
1069 #ifdef CONFIG_PCI_MSI
1070 if (!platform_legacy_irq(irq))
1071 irq = IO_APIC_VECTOR(irq);
1073 printk(KERN_INFO "PCI->APIC IRQ transform: %s[%c] -> IRQ %d\n",
1074 pci_name(dev), 'A' + pin, irq);
1078 msg = " Probably buggy MP table.";
1079 } else if (pci_probe & PCI_BIOS_IRQ_SCAN)
1082 msg = " Please try using pci=biosirq.";
1084 /* With IDE legacy devices the IRQ lookup failure is not a problem.. */
1085 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE && !(dev->class & 0x5))
1088 printk(KERN_WARNING "PCI: No IRQ known for interrupt pin %c of device %s.%s\n",
1089 'A' + pin, pci_name(dev), msg);
1094 int pci_vector_resources(int last, int nr_released)
1096 int count = nr_released;
1099 int offset = (last % 8);
1101 while (next < FIRST_SYSTEM_VECTOR) {
1103 #ifdef CONFIG_X86_64
1104 if (next == IA32_SYSCALL_VECTOR)
1107 if (next == SYSCALL_VECTOR)
1111 if (next >= FIRST_SYSTEM_VECTOR) {
1113 next = FIRST_DEVICE_VECTOR + offset;