arch/i386/oprofile/nmi_int.c

   1 /**
   2  * @file nmi_int.c
   3  *
   4  * @remark Copyright 2002 OProfile authors
   5  * @remark Read the file COPYING
   6  *
   7  * @author John Levon <levon@movementarian.org>
   8  */
   9
  10 #include <linux/init.h>
  11 #include <linux/notifier.h>
  12 #include <linux/smp.h>
  13 #include <linux/oprofile.h>
  14 #include <linux/sysdev.h>
  15 #include <linux/slab.h>
  16 #include <linux/moduleparam.h>
  17 #include <asm/nmi.h>
  18 #include <asm/msr.h>
  19 #include <asm/apic.h>
  20
  21 #include "op_counter.h"
  22 #include "op_x86_model.h"
  23
  24 static struct op_x86_model_spec const * model;
  25 static struct op_msrs cpu_msrs[NR_CPUS];
  26 static unsigned long saved_lvtpc[NR_CPUS];
  27
  28 static int nmi_start(void);
  29 static void nmi_stop(void);
  30
  31 /* 0 == registered but off, 1 == registered and on */
  32 static int nmi_enabled = 0;
  33
  34 #ifdef CONFIG_PM
  35
  36 static int nmi_suspend(struct sys_device *dev, pm_message_t state)
  37 {
  38         if (nmi_enabled == 1)
  39                 nmi_stop();
  40         return 0;
  41 }
  42
  43
  44 static int nmi_resume(struct sys_device *dev)
  45 {
  46         if (nmi_enabled == 1)
  47                 nmi_start();
  48         return 0;
  49 }
  50
  51
  52 static struct sysdev_class oprofile_sysclass = {
  53         set_kset_name("oprofile"),
  54         .resume         = nmi_resume,
  55         .suspend        = nmi_suspend,
  56 };
  57
  58
  59 static struct sys_device device_oprofile = {
  60         .id     = 0,
  61         .cls    = &oprofile_sysclass,
  62 };
  63
  64
  65 static int __init init_driverfs(void)
  66 {
  67         int error;
  68         if (!(error = sysdev_class_register(&oprofile_sysclass)))
  69                 error = sysdev_register(&device_oprofile);
  70         return error;
  71 }
  72
  73
  74 static void exit_driverfs(void)
  75 {
  76         sysdev_unregister(&device_oprofile);
  77         sysdev_class_unregister(&oprofile_sysclass);
  78 }
  79
  80 #else
  81 #define init_driverfs() do { } while (0)
  82 #define exit_driverfs() do { } while (0)
  83 #endif /* CONFIG_PM */
  84
  85
  86 static int nmi_callback(struct pt_regs * regs, int cpu)
  87 {
  88         return model->check_ctrs(regs, &cpu_msrs[cpu]);
  89 }
  90
  91
  92 static void nmi_cpu_save_registers(struct op_msrs * msrs)
  93 {
  94         unsigned int const nr_ctrs = model->num_counters;
  95         unsigned int const nr_ctrls = model->num_controls;
  96         struct op_msr * counters = msrs->counters;
  97         struct op_msr * controls = msrs->controls;
  98         unsigned int i;
  99
 100         for (i = 0; i < nr_ctrs; ++i) {
 101                 rdmsr(counters[i].addr,
 102                         counters[i].saved.low,
 103                         counters[i].saved.high);
 104         }
 105
 106         for (i = 0; i < nr_ctrls; ++i) {
 107                 rdmsr(controls[i].addr,
 108                         controls[i].saved.low,
 109                         controls[i].saved.high);
 110         }
 111 }
 112
 113
 114 static void nmi_save_registers(void * dummy)
 115 {
 116         int cpu = smp_processor_id();
 117         struct op_msrs * msrs = &cpu_msrs[cpu];
 118         model->fill_in_addresses(msrs);
 119         nmi_cpu_save_registers(msrs);
 120 }
 121
 122
 123 static void free_msrs(void)
 124 {
 125         int i;
 126         for_each_possible_cpu(i) {
 127                 kfree(cpu_msrs[i].counters);
 128                 cpu_msrs[i].counters = NULL;
 129                 kfree(cpu_msrs[i].controls);
 130                 cpu_msrs[i].controls = NULL;
 131         }
 132 }
 133
 134
 135 static int allocate_msrs(void)
 136 {
 137         int success = 1;
 138         size_t controls_size = sizeof(struct op_msr) * model->num_controls;
 139         size_t counters_size = sizeof(struct op_msr) * model->num_counters;
 140
 141         int i;
 142         for_each_online_cpu(i) {
 143                 cpu_msrs[i].counters = kmalloc(counters_size, GFP_KERNEL);
 144                 if (!cpu_msrs[i].counters) {
 145                         success = 0;
 146                         break;
 147                 }
 148                 cpu_msrs[i].controls = kmalloc(controls_size, GFP_KERNEL);
 149                 if (!cpu_msrs[i].controls) {
 150                         success = 0;
 151                         break;
 152                 }
 153         }
 154
 155         if (!success)
 156                 free_msrs();
 157
 158         return success;
 159 }
 160
 161
 162 static void nmi_cpu_setup(void * dummy)
 163 {
 164         int cpu = smp_processor_id();
 165         struct op_msrs * msrs = &cpu_msrs[cpu];
 166         spin_lock(&oprofilefs_lock);
 167         model->setup_ctrs(msrs);
 168         spin_unlock(&oprofilefs_lock);
 169         saved_lvtpc[cpu] = apic_read(APIC_LVTPC);
 170         apic_write(APIC_LVTPC, APIC_DM_NMI);
 171 }
 172
 173
 174 static int nmi_setup(void)
 175 {
 176         if (!allocate_msrs())
 177                 return -ENOMEM;
 178
 179         /* We walk a thin line between law and rape here.
 180          * We need to be careful to install our NMI handler
 181          * without actually triggering any NMIs as this will
 182          * break the core code horrifically.
 183          */
 184         if (reserve_lapic_nmi() < 0) {
 185                 free_msrs();
 186                 return -EBUSY;
 187         }
 188         /* We need to serialize save and setup for HT because the subset
 189          * of msrs are distinct for save and setup operations
 190          */
 191         on_each_cpu(nmi_save_registers, NULL, 0, 1);
 192         on_each_cpu(nmi_cpu_setup, NULL, 0, 1);
 193         set_nmi_callback(nmi_callback);
 194         nmi_enabled = 1;
 195         return 0;
 196 }
 197
 198
 199 static void nmi_restore_registers(struct op_msrs * msrs)
 200 {
 201         unsigned int const nr_ctrs = model->num_counters;
 202         unsigned int const nr_ctrls = model->num_controls;
 203         struct op_msr * counters = msrs->counters;
 204         struct op_msr * controls = msrs->controls;
 205         unsigned int i;
 206
 207         for (i = 0; i < nr_ctrls; ++i) {
 208                 wrmsr(controls[i].addr,
 209                         controls[i].saved.low,
 210                         controls[i].saved.high);
 211         }
 212
 213         for (i = 0; i < nr_ctrs; ++i) {
 214                 wrmsr(counters[i].addr,
 215                         counters[i].saved.low,
 216                         counters[i].saved.high);
 217         }
 218 }
 219
 220
 221 static void nmi_cpu_shutdown(void * dummy)
 222 {
 223         unsigned int v;
 224         int cpu = smp_processor_id();
 225         struct op_msrs * msrs = &cpu_msrs[cpu];
 226
 227         /* restoring APIC_LVTPC can trigger an apic error because the delivery
 228          * mode and vector nr combination can be illegal. That's by design: on
 229          * power on apic lvt contain a zero vector nr which are legal only for
 230          * NMI delivery mode. So inhibit apic err before restoring lvtpc
 231          */
 232         v = apic_read(APIC_LVTERR);
 233         apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
 234         apic_write(APIC_LVTPC, saved_lvtpc[cpu]);
 235         apic_write(APIC_LVTERR, v);
 236         nmi_restore_registers(msrs);
 237 }
 238
 239
 240 static void nmi_shutdown(void)
 241 {
 242         nmi_enabled = 0;
 243         on_each_cpu(nmi_cpu_shutdown, NULL, 0, 1);
 244         unset_nmi_callback();
 245         release_lapic_nmi();
 246         free_msrs();
 247 }
 248
 249
 250 static void nmi_cpu_start(void * dummy)
 251 {
 252         struct op_msrs const * msrs = &cpu_msrs[smp_processor_id()];
 253         model->start(msrs);
 254 }
 255
 256
 257 static int nmi_start(void)
 258 {
 259         on_each_cpu(nmi_cpu_start, NULL, 0, 1);
 260         return 0;
 261 }
 262
 263
 264 static void nmi_cpu_stop(void * dummy)
 265 {
 266         struct op_msrs const * msrs = &cpu_msrs[smp_processor_id()];
 267         model->stop(msrs);
 268 }
 269
 270
 271 static void nmi_stop(void)
 272 {
 273         on_each_cpu(nmi_cpu_stop, NULL, 0, 1);
 274 }
 275
 276
 277 struct op_counter_config counter_config[OP_MAX_COUNTER];
 278
 279 static int nmi_create_files(struct super_block * sb, struct dentry * root)
 280 {
 281         unsigned int i;
 282
 283         for (i = 0; i < model->num_counters; ++i) {
 284                 struct dentry * dir;
 285                 char buf[4];
 286
 287                 snprintf(buf,  sizeof(buf), "%d", i);
 288                 dir = oprofilefs_mkdir(sb, root, buf);
 289                 oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
 290                 oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
 291                 oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
 292                 oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
 293                 oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
 294                 oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
 295         }
 296
 297         return 0;
 298 }
 299
 300 static int p4force;
 301 module_param(p4force, int, 0);
 302
 303 static int __init p4_init(char ** cpu_type)
 304 {
 305         __u8 cpu_model = boot_cpu_data.x86_model;
 306
 307         if (!p4force && (cpu_model > 6 || cpu_model == 5))
 308                 return 0;
 309
 310 #ifndef CONFIG_SMP
 311         *cpu_type = "i386/p4";
 312         model = &op_p4_spec;
 313         return 1;
 314 #else
 315         switch (smp_num_siblings) {
 316                 case 1:
 317                         *cpu_type = "i386/p4";
 318                         model = &op_p4_spec;
 319                         return 1;
 320
 321                 case 2:
 322                         *cpu_type = "i386/p4-ht";
 323                         model = &op_p4_ht2_spec;
 324                         return 1;
 325         }
 326 #endif
 327
 328         printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
 329         printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
 330         return 0;
 331 }
 332
 333
 334 static int __init ppro_init(char ** cpu_type)
 335 {
 336         __u8 cpu_model = boot_cpu_data.x86_model;
 337
 338         if (cpu_model == 14)
 339                 *cpu_type = "i386/core";
 340         else if (cpu_model > 0xd)
 341                 return 0;
 342         else if (cpu_model == 9) {
 343                 *cpu_type = "i386/p6_mobile";
 344         } else if (cpu_model > 5) {
 345                 *cpu_type = "i386/piii";
 346         } else if (cpu_model > 2) {
 347                 *cpu_type = "i386/pii";
 348         } else {
 349                 *cpu_type = "i386/ppro";
 350         }
 351
 352         model = &op_ppro_spec;
 353         return 1;
 354 }
 355
 356 /* in order to get driverfs right */
 357 static int using_nmi;
 358
 359 int __init op_nmi_init(struct oprofile_operations *ops)
 360 {
 361         __u8 vendor = boot_cpu_data.x86_vendor;
 362         __u8 family = boot_cpu_data.x86;
 363         char *cpu_type;
 364
 365         if (!cpu_has_apic)
 366                 return -ENODEV;
 367
 368         switch (vendor) {
 369                 case X86_VENDOR_AMD:
 370                         /* Needs to be at least an Athlon (or hammer in 32bit mode) */
 371
 372                         switch (family) {
 373                         default:
 374                                 return -ENODEV;
 375                         case 6:
 376                                 model = &op_athlon_spec;
 377                                 cpu_type = "i386/athlon";
 378                                 break;
 379                         case 0xf:
 380                                 model = &op_athlon_spec;
 381                                 /* Actually it could be i386/hammer too, but give
 382                                    user space an consistent name. */
 383                                 cpu_type = "x86-64/hammer";
 384                                 break;
 385                         }
 386                         break;
 387
 388                 case X86_VENDOR_INTEL:
 389                         switch (family) {
 390                                 /* Pentium IV */
 391                                 case 0xf:
 392                                         if (!p4_init(&cpu_type))
 393                                                 return -ENODEV;
 394                                         break;
 395
 396                                 /* A P6-class processor */
 397                                 case 6:
 398                                         if (!ppro_init(&cpu_type))
 399                                                 return -ENODEV;
 400                                         break;
 401
 402                                 default:
 403                                         return -ENODEV;
 404                         }
 405                         break;
 406
 407                 default:
 408                         return -ENODEV;
 409         }
 410
 411         init_driverfs();
 412         using_nmi = 1;
 413         ops->create_files = nmi_create_files;
 414         ops->setup = nmi_setup;
 415         ops->shutdown = nmi_shutdown;
 416         ops->start = nmi_start;
 417         ops->stop = nmi_stop;
 418         ops->cpu_type = cpu_type;
 419         printk(KERN_INFO "oprofile: using NMI interrupt.\n");
 420         return 0;
 421 }
 422
 423
 424 void op_nmi_exit(void)
 425 {
 426         if (using_nmi)
 427                 exit_driverfs();
 428 }