arch/i386/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/smp_lock.h>
  29 #include <linux/mc146818rtc.h>
  30 #include <linux/compiler.h>
  31 #include <linux/acpi.h>
  32 #include <linux/module.h>
  33 #include <linux/sysdev.h>
  34
  35 #include <asm/io.h>
  36 #include <asm/smp.h>
  37 #include <asm/desc.h>
  38 #include <asm/timer.h>
  39 #include <asm/i8259.h>
  40 #include <asm/nmi.h>
  41
  42 #include <mach_apic.h>
  43 #include <mach_apicdef.h>
  44
  45 #include "io_ports.h"
  46
  47 int (*ioapic_renumber_irq)(int ioapic, int irq);
  48 atomic_t irq_mis_count;
  49
  50 /* Where if anywhere is the i8259 connect in external int mode */
  51 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
  52
  53 static DEFINE_SPINLOCK(ioapic_lock);
  54 static DEFINE_SPINLOCK(vector_lock);
  55
  56 int timer_over_8254 __initdata = 1;
  57
  58 /*
  59  *      Is the SiS APIC rmw bug present ?
  60  *      -1 = don't know, 0 = no, 1 = yes
  61  */
  62 int sis_apic_bug = -1;
  63
  64 /*
  65  * # of IRQ routing registers
  66  */
  67 int nr_ioapic_registers[MAX_IO_APICS];
  68
  69 static int disable_timer_pin_1 __initdata;
  70
  71 /*
  72  * Rough estimation of how many shared IRQs there are, can
  73  * be changed anytime.
  74  */
  75 #define MAX_PLUS_SHARED_IRQS NR_IRQS
  76 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  77
  78 /*
  79  * This is performance-critical, we want to do it O(1)
  80  *
  81  * the indexing order of this array favors 1:1 mappings
  82  * between pins and IRQs.
  83  */
  84
  85 static struct irq_pin_list {
  86         int apic, pin, next;
  87 } irq_2_pin[PIN_MAP_SIZE];
  88
  89 int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
  90 #ifdef CONFIG_PCI_MSI
  91 #define vector_to_irq(vector)   \
  92         (platform_legacy_irq(vector) ? vector : vector_irq[vector])
  93 #else
  94 #define vector_to_irq(vector)   (vector)
  95 #endif
  96
  97
  98 union entry_union {
  99         struct { u32 w1, w2; };
 100         struct IO_APIC_route_entry entry;
 101 };
 102
 103 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
 104 {
 105         union entry_union eu;
 106         unsigned long flags;
 107         spin_lock_irqsave(&ioapic_lock, flags);
 108         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
 109         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
 110         spin_unlock_irqrestore(&ioapic_lock, flags);
 111         return eu.entry;
 112 }
 113
 114 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 115 {
 116         unsigned long flags;
 117         union entry_union eu;
 118         eu.entry = e;
 119         spin_lock_irqsave(&ioapic_lock, flags);
 120         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 121         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 122         spin_unlock_irqrestore(&ioapic_lock, flags);
 123 }
 124
 125 /*
 126  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 127  * shared ISA-space IRQs, so we have to support them. We are super
 128  * fast in the common case, and fast for shared ISA-space IRQs.
 129  */
 130 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 131 {
 132         static int first_free_entry = NR_IRQS;
 133         struct irq_pin_list *entry = irq_2_pin + irq;
 134
 135         while (entry->next)
 136                 entry = irq_2_pin + entry->next;
 137
 138         if (entry->pin != -1) {
 139                 entry->next = first_free_entry;
 140                 entry = irq_2_pin + entry->next;
 141                 if (++first_free_entry >= PIN_MAP_SIZE)
 142                         panic("io_apic.c: whoops");
 143         }
 144         entry->apic = apic;
 145         entry->pin = pin;
 146 }
 147
 148 /*
 149  * Reroute an IRQ to a different pin.
 150  */
 151 static void __init replace_pin_at_irq(unsigned int irq,
 152                                       int oldapic, int oldpin,
 153                                       int newapic, int newpin)
 154 {
 155         struct irq_pin_list *entry = irq_2_pin + irq;
 156
 157         while (1) {
 158                 if (entry->apic == oldapic && entry->pin == oldpin) {
 159                         entry->apic = newapic;
 160                         entry->pin = newpin;
 161                 }
 162                 if (!entry->next)
 163                         break;
 164                 entry = irq_2_pin + entry->next;
 165         }
 166 }
 167
 168 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
 169 {
 170         struct irq_pin_list *entry = irq_2_pin + irq;
 171         unsigned int pin, reg;
 172
 173         for (;;) {
 174                 pin = entry->pin;
 175                 if (pin == -1)
 176                         break;
 177                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
 178                 reg &= ~disable;
 179                 reg |= enable;
 180                 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
 181                 if (!entry->next)
 182                         break;
 183                 entry = irq_2_pin + entry->next;
 184         }
 185 }
 186
 187 /* mask = 1 */
 188 static void __mask_IO_APIC_irq (unsigned int irq)
 189 {
 190         __modify_IO_APIC_irq(irq, 0x00010000, 0);
 191 }
 192
 193 /* mask = 0 */
 194 static void __unmask_IO_APIC_irq (unsigned int irq)
 195 {
 196         __modify_IO_APIC_irq(irq, 0, 0x00010000);
 197 }
 198
 199 /* mask = 1, trigger = 0 */
 200 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
 201 {
 202         __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
 203 }
 204
 205 /* mask = 0, trigger = 1 */
 206 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
 207 {
 208         __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
 209 }
 210
 211 static void mask_IO_APIC_irq (unsigned int irq)
 212 {
 213         unsigned long flags;
 214
 215         spin_lock_irqsave(&ioapic_lock, flags);
 216         __mask_IO_APIC_irq(irq);
 217         spin_unlock_irqrestore(&ioapic_lock, flags);
 218 }
 219
 220 static void unmask_IO_APIC_irq (unsigned int irq)
 221 {
 222         unsigned long flags;
 223
 224         spin_lock_irqsave(&ioapic_lock, flags);
 225         __unmask_IO_APIC_irq(irq);
 226         spin_unlock_irqrestore(&ioapic_lock, flags);
 227 }
 228
 229 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 230 {
 231         struct IO_APIC_route_entry entry;
 232
 233         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 234         entry = ioapic_read_entry(apic, pin);
 235         if (entry.delivery_mode == dest_SMI)
 236                 return;
 237
 238         /*
 239          * Disable it in the IO-APIC irq-routing table:
 240          */
 241         memset(&entry, 0, sizeof(entry));
 242         entry.mask = 1;
 243         ioapic_write_entry(apic, pin, entry);
 244 }
 245
 246 static void clear_IO_APIC (void)
 247 {
 248         int apic, pin;
 249
 250         for (apic = 0; apic < nr_ioapics; apic++)
 251                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 252                         clear_IO_APIC_pin(apic, pin);
 253 }
 254
 255 #ifdef CONFIG_SMP
 256 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
 257 {
 258         unsigned long flags;
 259         int pin;
 260         struct irq_pin_list *entry = irq_2_pin + irq;
 261         unsigned int apicid_value;
 262         cpumask_t tmp;
 263
 264         cpus_and(tmp, cpumask, cpu_online_map);
 265         if (cpus_empty(tmp))
 266                 tmp = TARGET_CPUS;
 267
 268         cpus_and(cpumask, tmp, CPU_MASK_ALL);
 269
 270         apicid_value = cpu_mask_to_apicid(cpumask);
 271         /* Prepare to do the io_apic_write */
 272         apicid_value = apicid_value << 24;
 273         spin_lock_irqsave(&ioapic_lock, flags);
 274         for (;;) {
 275                 pin = entry->pin;
 276                 if (pin == -1)
 277                         break;
 278                 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
 279                 if (!entry->next)
 280                         break;
 281                 entry = irq_2_pin + entry->next;
 282         }
 283         set_irq_info(irq, cpumask);
 284         spin_unlock_irqrestore(&ioapic_lock, flags);
 285 }
 286
 287 #if defined(CONFIG_IRQBALANCE)
 288 # include <asm/processor.h>     /* kernel_thread() */
 289 # include <linux/kernel_stat.h> /* kstat */
 290 # include <linux/slab.h>                /* kmalloc() */
 291 # include <linux/timer.h>       /* time_after() */
 292
 293 #ifdef CONFIG_BALANCED_IRQ_DEBUG
 294 #  define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
 295 #  define Dprintk(x...) do { TDprintk(x); } while (0)
 296 # else
 297 #  define TDprintk(x...)
 298 #  define Dprintk(x...)
 299 # endif
 300
 301 #define IRQBALANCE_CHECK_ARCH -999
 302 #define MAX_BALANCED_IRQ_INTERVAL       (5*HZ)
 303 #define MIN_BALANCED_IRQ_INTERVAL       (HZ/2)
 304 #define BALANCED_IRQ_MORE_DELTA         (HZ/10)
 305 #define BALANCED_IRQ_LESS_DELTA         (HZ)
 306
 307 static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
 308 static int physical_balance __read_mostly;
 309 static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
 310
 311 static struct irq_cpu_info {
 312         unsigned long * last_irq;
 313         unsigned long * irq_delta;
 314         unsigned long irq;
 315 } irq_cpu_data[NR_CPUS];
 316
 317 #define CPU_IRQ(cpu)            (irq_cpu_data[cpu].irq)
 318 #define LAST_CPU_IRQ(cpu,irq)   (irq_cpu_data[cpu].last_irq[irq])
 319 #define IRQ_DELTA(cpu,irq)      (irq_cpu_data[cpu].irq_delta[irq])
 320
 321 #define IDLE_ENOUGH(cpu,now) \
 322         (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
 323
 324 #define IRQ_ALLOWED(cpu, allowed_mask)  cpu_isset(cpu, allowed_mask)
 325
 326 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
 327
 328 static cpumask_t balance_irq_affinity[NR_IRQS] = {
 329         [0 ... NR_IRQS-1] = CPU_MASK_ALL
 330 };
 331
 332 void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
 333 {
 334         balance_irq_affinity[irq] = mask;
 335 }
 336
 337 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
 338                         unsigned long now, int direction)
 339 {
 340         int search_idle = 1;
 341         int cpu = curr_cpu;
 342
 343         goto inside;
 344
 345         do {
 346                 if (unlikely(cpu == curr_cpu))
 347                         search_idle = 0;
 348 inside:
 349                 if (direction == 1) {
 350                         cpu++;
 351                         if (cpu >= NR_CPUS)
 352                                 cpu = 0;
 353                 } else {
 354                         cpu--;
 355                         if (cpu == -1)
 356                                 cpu = NR_CPUS-1;
 357                 }
 358         } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
 359                         (search_idle && !IDLE_ENOUGH(cpu,now)));
 360
 361         return cpu;
 362 }
 363
 364 static inline void balance_irq(int cpu, int irq)
 365 {
 366         unsigned long now = jiffies;
 367         cpumask_t allowed_mask;
 368         unsigned int new_cpu;
 369
 370         if (irqbalance_disabled)
 371                 return;
 372
 373         cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
 374         new_cpu = move(cpu, allowed_mask, now, 1);
 375         if (cpu != new_cpu) {
 376                 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
 377         }
 378 }
 379
 380 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
 381 {
 382         int i, j;
 383         Dprintk("Rotating IRQs among CPUs.\n");
 384         for_each_online_cpu(i) {
 385                 for (j = 0; j < NR_IRQS; j++) {
 386                         if (!irq_desc[j].action)
 387                                 continue;
 388                         /* Is it a significant load ?  */
 389                         if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
 390                                                 useful_load_threshold)
 391                                 continue;
 392                         balance_irq(i, j);
 393                 }
 394         }
 395         balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 396                 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 397         return;
 398 }
 399
 400 static void do_irq_balance(void)
 401 {
 402         int i, j;
 403         unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
 404         unsigned long move_this_load = 0;
 405         int max_loaded = 0, min_loaded = 0;
 406         int load;
 407         unsigned long useful_load_threshold = balanced_irq_interval + 10;
 408         int selected_irq;
 409         int tmp_loaded, first_attempt = 1;
 410         unsigned long tmp_cpu_irq;
 411         unsigned long imbalance = 0;
 412         cpumask_t allowed_mask, target_cpu_mask, tmp;
 413
 414         for_each_possible_cpu(i) {
 415                 int package_index;
 416                 CPU_IRQ(i) = 0;
 417                 if (!cpu_online(i))
 418                         continue;
 419                 package_index = CPU_TO_PACKAGEINDEX(i);
 420                 for (j = 0; j < NR_IRQS; j++) {
 421                         unsigned long value_now, delta;
 422                         /* Is this an active IRQ? */
 423                         if (!irq_desc[j].action)
 424                                 continue;
 425                         if ( package_index == i )
 426                                 IRQ_DELTA(package_index,j) = 0;
 427                         /* Determine the total count per processor per IRQ */
 428                         value_now = (unsigned long) kstat_cpu(i).irqs[j];
 429
 430                         /* Determine the activity per processor per IRQ */
 431                         delta = value_now - LAST_CPU_IRQ(i,j);
 432
 433                         /* Update last_cpu_irq[][] for the next time */
 434                         LAST_CPU_IRQ(i,j) = value_now;
 435
 436                         /* Ignore IRQs whose rate is less than the clock */
 437                         if (delta < useful_load_threshold)
 438                                 continue;
 439                         /* update the load for the processor or package total */
 440                         IRQ_DELTA(package_index,j) += delta;
 441
 442                         /* Keep track of the higher numbered sibling as well */
 443                         if (i != package_index)
 444                                 CPU_IRQ(i) += delta;
 445                         /*
 446                          * We have sibling A and sibling B in the package
 447                          *
 448                          * cpu_irq[A] = load for cpu A + load for cpu B
 449                          * cpu_irq[B] = load for cpu B
 450                          */
 451                         CPU_IRQ(package_index) += delta;
 452                 }
 453         }
 454         /* Find the least loaded processor package */
 455         for_each_online_cpu(i) {
 456                 if (i != CPU_TO_PACKAGEINDEX(i))
 457                         continue;
 458                 if (min_cpu_irq > CPU_IRQ(i)) {
 459                         min_cpu_irq = CPU_IRQ(i);
 460                         min_loaded = i;
 461                 }
 462         }
 463         max_cpu_irq = ULONG_MAX;
 464
 465 tryanothercpu:
 466         /* Look for heaviest loaded processor.
 467          * We may come back to get the next heaviest loaded processor.
 468          * Skip processors with trivial loads.
 469          */
 470         tmp_cpu_irq = 0;
 471         tmp_loaded = -1;
 472         for_each_online_cpu(i) {
 473                 if (i != CPU_TO_PACKAGEINDEX(i))
 474                         continue;
 475                 if (max_cpu_irq <= CPU_IRQ(i))
 476                         continue;
 477                 if (tmp_cpu_irq < CPU_IRQ(i)) {
 478                         tmp_cpu_irq = CPU_IRQ(i);
 479                         tmp_loaded = i;
 480                 }
 481         }
 482
 483         if (tmp_loaded == -1) {
 484          /* In the case of small number of heavy interrupt sources,
 485           * loading some of the cpus too much. We use Ingo's original
 486           * approach to rotate them around.
 487           */
 488                 if (!first_attempt && imbalance >= useful_load_threshold) {
 489                         rotate_irqs_among_cpus(useful_load_threshold);
 490                         return;
 491                 }
 492                 goto not_worth_the_effort;
 493         }
 494
 495         first_attempt = 0;              /* heaviest search */
 496         max_cpu_irq = tmp_cpu_irq;      /* load */
 497         max_loaded = tmp_loaded;        /* processor */
 498         imbalance = (max_cpu_irq - min_cpu_irq) / 2;
 499
 500         Dprintk("max_loaded cpu = %d\n", max_loaded);
 501         Dprintk("min_loaded cpu = %d\n", min_loaded);
 502         Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
 503         Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
 504         Dprintk("load imbalance = %lu\n", imbalance);
 505
 506         /* if imbalance is less than approx 10% of max load, then
 507          * observe diminishing returns action. - quit
 508          */
 509         if (imbalance < (max_cpu_irq >> 3)) {
 510                 Dprintk("Imbalance too trivial\n");
 511                 goto not_worth_the_effort;
 512         }
 513
 514 tryanotherirq:
 515         /* if we select an IRQ to move that can't go where we want, then
 516          * see if there is another one to try.
 517          */
 518         move_this_load = 0;
 519         selected_irq = -1;
 520         for (j = 0; j < NR_IRQS; j++) {
 521                 /* Is this an active IRQ? */
 522                 if (!irq_desc[j].action)
 523                         continue;
 524                 if (imbalance <= IRQ_DELTA(max_loaded,j))
 525                         continue;
 526                 /* Try to find the IRQ that is closest to the imbalance
 527                  * without going over.
 528                  */
 529                 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
 530                         move_this_load = IRQ_DELTA(max_loaded,j);
 531                         selected_irq = j;
 532                 }
 533         }
 534         if (selected_irq == -1) {
 535                 goto tryanothercpu;
 536         }
 537
 538         imbalance = move_this_load;
 539
 540         /* For physical_balance case, we accumlated both load
 541          * values in the one of the siblings cpu_irq[],
 542          * to use the same code for physical and logical processors
 543          * as much as possible.
 544          *
 545          * NOTE: the cpu_irq[] array holds the sum of the load for
 546          * sibling A and sibling B in the slot for the lowest numbered
 547          * sibling (A), _AND_ the load for sibling B in the slot for
 548          * the higher numbered sibling.
 549          *
 550          * We seek the least loaded sibling by making the comparison
 551          * (A+B)/2 vs B
 552          */
 553         load = CPU_IRQ(min_loaded) >> 1;
 554         for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
 555                 if (load > CPU_IRQ(j)) {
 556                         /* This won't change cpu_sibling_map[min_loaded] */
 557                         load = CPU_IRQ(j);
 558                         min_loaded = j;
 559                 }
 560         }
 561
 562         cpus_and(allowed_mask,
 563                 cpu_online_map,
 564                 balance_irq_affinity[selected_irq]);
 565         target_cpu_mask = cpumask_of_cpu(min_loaded);
 566         cpus_and(tmp, target_cpu_mask, allowed_mask);
 567
 568         if (!cpus_empty(tmp)) {
 569
 570                 Dprintk("irq = %d moved to cpu = %d\n",
 571                                 selected_irq, min_loaded);
 572                 /* mark for change destination */
 573                 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
 574
 575                 /* Since we made a change, come back sooner to
 576                  * check for more variation.
 577                  */
 578                 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 579                         balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 580                 return;
 581         }
 582         goto tryanotherirq;
 583
 584 not_worth_the_effort:
 585         /*
 586          * if we did not find an IRQ to move, then adjust the time interval
 587          * upward
 588          */
 589         balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
 590                 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
 591         Dprintk("IRQ worth rotating not found\n");
 592         return;
 593 }
 594
 595 static int balanced_irq(void *unused)
 596 {
 597         int i;
 598         unsigned long prev_balance_time = jiffies;
 599         long time_remaining = balanced_irq_interval;
 600
 601         daemonize("kirqd");
 602
 603         /* push everything to CPU 0 to give us a starting point.  */
 604         for (i = 0 ; i < NR_IRQS ; i++) {
 605                 irq_desc[i].pending_mask = cpumask_of_cpu(0);
 606                 set_pending_irq(i, cpumask_of_cpu(0));
 607         }
 608
 609         for ( ; ; ) {
 610                 time_remaining = schedule_timeout_interruptible(time_remaining);
 611                 try_to_freeze();
 612                 if (time_after(jiffies,
 613                                 prev_balance_time+balanced_irq_interval)) {
 614                         preempt_disable();
 615                         do_irq_balance();
 616                         prev_balance_time = jiffies;
 617                         time_remaining = balanced_irq_interval;
 618                         preempt_enable();
 619                 }
 620         }
 621         return 0;
 622 }
 623
 624 static int __init balanced_irq_init(void)
 625 {
 626         int i;
 627         struct cpuinfo_x86 *c;
 628         cpumask_t tmp;
 629
 630         cpus_shift_right(tmp, cpu_online_map, 2);
 631         c = &boot_cpu_data;
 632         /* When not overwritten by the command line ask subarchitecture. */
 633         if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
 634                 irqbalance_disabled = NO_BALANCE_IRQ;
 635         if (irqbalance_disabled)
 636                 return 0;
 637
 638          /* disable irqbalance completely if there is only one processor online */
 639         if (num_online_cpus() < 2) {
 640                 irqbalance_disabled = 1;
 641                 return 0;
 642         }
 643         /*
 644          * Enable physical balance only if more than 1 physical processor
 645          * is present
 646          */
 647         if (smp_num_siblings > 1 && !cpus_empty(tmp))
 648                 physical_balance = 1;
 649
 650         for_each_online_cpu(i) {
 651                 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 652                 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 653                 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
 654                         printk(KERN_ERR "balanced_irq_init: out of memory");
 655                         goto failed;
 656                 }
 657                 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
 658                 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
 659         }
 660
 661         printk(KERN_INFO "Starting balanced_irq\n");
 662         if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0)
 663                 return 0;
 664         else
 665                 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
 666 failed:
 667         for_each_possible_cpu(i) {
 668                 kfree(irq_cpu_data[i].irq_delta);
 669                 irq_cpu_data[i].irq_delta = NULL;
 670                 kfree(irq_cpu_data[i].last_irq);
 671                 irq_cpu_data[i].last_irq = NULL;
 672         }
 673         return 0;
 674 }
 675
 676 int __init irqbalance_disable(char *str)
 677 {
 678         irqbalance_disabled = 1;
 679         return 1;
 680 }
 681
 682 __setup("noirqbalance", irqbalance_disable);
 683
 684 late_initcall(balanced_irq_init);
 685 #endif /* CONFIG_IRQBALANCE */
 686 #endif /* CONFIG_SMP */
 687
 688 #ifndef CONFIG_SMP
 689 void fastcall send_IPI_self(int vector)
 690 {
 691         unsigned int cfg;
 692
 693         /*
 694          * Wait for idle.
 695          */
 696         apic_wait_icr_idle();
 697         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
 698         /*
 699          * Send the IPI. The write to APIC_ICR fires this off.
 700          */
 701         apic_write_around(APIC_ICR, cfg);
 702 }
 703 #endif /* !CONFIG_SMP */
 704
 705
 706 /*
 707  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 708  * specific CPU-side IRQs.
 709  */
 710
 711 #define MAX_PIRQS 8
 712 static int pirq_entries [MAX_PIRQS];
 713 static int pirqs_enabled;
 714 int skip_ioapic_setup;
 715
 716 static int __init ioapic_setup(char *str)
 717 {
 718         skip_ioapic_setup = 1;
 719         return 1;
 720 }
 721
 722 __setup("noapic", ioapic_setup);
 723
 724 static int __init ioapic_pirq_setup(char *str)
 725 {
 726         int i, max;
 727         int ints[MAX_PIRQS+1];
 728
 729         get_options(str, ARRAY_SIZE(ints), ints);
 730
 731         for (i = 0; i < MAX_PIRQS; i++)
 732                 pirq_entries[i] = -1;
 733
 734         pirqs_enabled = 1;
 735         apic_printk(APIC_VERBOSE, KERN_INFO
 736                         "PIRQ redirection, working around broken MP-BIOS.\n");
 737         max = MAX_PIRQS;
 738         if (ints[0] < MAX_PIRQS)
 739                 max = ints[0];
 740
 741         for (i = 0; i < max; i++) {
 742                 apic_printk(APIC_VERBOSE, KERN_DEBUG
 743                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 744                 /*
 745                  * PIRQs are mapped upside down, usually.
 746                  */
 747                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 748         }
 749         return 1;
 750 }
 751
 752 __setup("pirq=", ioapic_pirq_setup);
 753
 754 /*
 755  * Find the IRQ entry number of a certain pin.
 756  */
 757 static int find_irq_entry(int apic, int pin, int type)
 758 {
 759         int i;
 760
 761         for (i = 0; i < mp_irq_entries; i++)
 762                 if (mp_irqs[i].mpc_irqtype == type &&
 763                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 764                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 765                     mp_irqs[i].mpc_dstirq == pin)
 766                         return i;
 767
 768         return -1;
 769 }
 770
 771 /*
 772  * Find the pin to which IRQ[irq] (ISA) is connected
 773  */
 774 static int __init find_isa_irq_pin(int irq, int type)
 775 {
 776         int i;
 777
 778         for (i = 0; i < mp_irq_entries; i++) {
 779                 int lbus = mp_irqs[i].mpc_srcbus;
 780
 781                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 782                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 783                      mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
 784                      mp_bus_id_to_type[lbus] == MP_BUS_NEC98
 785                     ) &&
 786                     (mp_irqs[i].mpc_irqtype == type) &&
 787                     (mp_irqs[i].mpc_srcbusirq == irq))
 788
 789                         return mp_irqs[i].mpc_dstirq;
 790         }
 791         return -1;
 792 }
 793
 794 static int __init find_isa_irq_apic(int irq, int type)
 795 {
 796         int i;
 797
 798         for (i = 0; i < mp_irq_entries; i++) {
 799                 int lbus = mp_irqs[i].mpc_srcbus;
 800
 801                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 802                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 803                      mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
 804                      mp_bus_id_to_type[lbus] == MP_BUS_NEC98
 805                     ) &&
 806                     (mp_irqs[i].mpc_irqtype == type) &&
 807                     (mp_irqs[i].mpc_srcbusirq == irq))
 808                         break;
 809         }
 810         if (i < mp_irq_entries) {
 811                 int apic;
 812                 for(apic = 0; apic < nr_ioapics; apic++) {
 813                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
 814                                 return apic;
 815                 }
 816         }
 817
 818         return -1;
 819 }
 820
 821 /*
 822  * Find a specific PCI IRQ entry.
 823  * Not an __init, possibly needed by modules
 824  */
 825 static int pin_2_irq(int idx, int apic, int pin);
 826
 827 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 828 {
 829         int apic, i, best_guess = -1;
 830
 831         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
 832                 "slot:%d, pin:%d.\n", bus, slot, pin);
 833         if (mp_bus_id_to_pci_bus[bus] == -1) {
 834                 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 835                 return -1;
 836         }
 837         for (i = 0; i < mp_irq_entries; i++) {
 838                 int lbus = mp_irqs[i].mpc_srcbus;
 839
 840                 for (apic = 0; apic < nr_ioapics; apic++)
 841                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 842                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 843                                 break;
 844
 845                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
 846                     !mp_irqs[i].mpc_irqtype &&
 847                     (bus == lbus) &&
 848                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 849                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 850
 851                         if (!(apic || IO_APIC_IRQ(irq)))
 852                                 continue;
 853
 854                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 855                                 return irq;
 856                         /*
 857                          * Use the first all-but-pin matching entry as a
 858                          * best-guess fuzzy result for broken mptables.
 859                          */
 860                         if (best_guess < 0)
 861                                 best_guess = irq;
 862                 }
 863         }
 864         return best_guess;
 865 }
 866 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
 867
 868 /*
 869  * This function currently is only a helper for the i386 smp boot process where
 870  * we need to reprogram the ioredtbls to cater for the cpus which have come online
 871  * so mask in all cases should simply be TARGET_CPUS
 872  */
 873 #ifdef CONFIG_SMP
 874 void __init setup_ioapic_dest(void)
 875 {
 876         int pin, ioapic, irq, irq_entry;
 877
 878         if (skip_ioapic_setup == 1)
 879                 return;
 880
 881         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
 882                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
 883                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
 884                         if (irq_entry == -1)
 885                                 continue;
 886                         irq = pin_2_irq(irq_entry, ioapic, pin);
 887                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
 888                 }
 889
 890         }
 891 }
 892 #endif
 893
 894 /*
 895  * EISA Edge/Level control register, ELCR
 896  */
 897 static int EISA_ELCR(unsigned int irq)
 898 {
 899         if (irq < 16) {
 900                 unsigned int port = 0x4d0 + (irq >> 3);
 901                 return (inb(port) >> (irq & 7)) & 1;
 902         }
 903         apic_printk(APIC_VERBOSE, KERN_INFO
 904                         "Broken MPtable reports ISA irq %d\n", irq);
 905         return 0;
 906 }
 907
 908 /* EISA interrupts are always polarity zero and can be edge or level
 909  * trigger depending on the ELCR value.  If an interrupt is listed as
 910  * EISA conforming in the MP table, that means its trigger type must
 911  * be read in from the ELCR */
 912
 913 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
 914 #define default_EISA_polarity(idx)      (0)
 915
 916 /* ISA interrupts are always polarity zero edge triggered,
 917  * when listed as conforming in the MP table. */
 918
 919 #define default_ISA_trigger(idx)        (0)
 920 #define default_ISA_polarity(idx)       (0)
 921
 922 /* PCI interrupts are always polarity one level triggered,
 923  * when listed as conforming in the MP table. */
 924
 925 #define default_PCI_trigger(idx)        (1)
 926 #define default_PCI_polarity(idx)       (1)
 927
 928 /* MCA interrupts are always polarity zero level triggered,
 929  * when listed as conforming in the MP table. */
 930
 931 #define default_MCA_trigger(idx)        (1)
 932 #define default_MCA_polarity(idx)       (0)
 933
 934 /* NEC98 interrupts are always polarity zero edge triggered,
 935  * when listed as conforming in the MP table. */
 936
 937 #define default_NEC98_trigger(idx)     (0)
 938 #define default_NEC98_polarity(idx)    (0)
 939
 940 static int __init MPBIOS_polarity(int idx)
 941 {
 942         int bus = mp_irqs[idx].mpc_srcbus;
 943         int polarity;
 944
 945         /*
 946          * Determine IRQ line polarity (high active or low active):
 947          */
 948         switch (mp_irqs[idx].mpc_irqflag & 3)
 949         {
 950                 case 0: /* conforms, ie. bus-type dependent polarity */
 951                 {
 952                         switch (mp_bus_id_to_type[bus])
 953                         {
 954                                 case MP_BUS_ISA: /* ISA pin */
 955                                 {
 956                                         polarity = default_ISA_polarity(idx);
 957                                         break;
 958                                 }
 959                                 case MP_BUS_EISA: /* EISA pin */
 960                                 {
 961                                         polarity = default_EISA_polarity(idx);
 962                                         break;
 963                                 }
 964                                 case MP_BUS_PCI: /* PCI pin */
 965                                 {
 966                                         polarity = default_PCI_polarity(idx);
 967                                         break;
 968                                 }
 969                                 case MP_BUS_MCA: /* MCA pin */
 970                                 {
 971                                         polarity = default_MCA_polarity(idx);
 972                                         break;
 973                                 }
 974                                 case MP_BUS_NEC98: /* NEC 98 pin */
 975                                 {
 976                                         polarity = default_NEC98_polarity(idx);
 977                                         break;
 978                                 }
 979                                 default:
 980                                 {
 981                                         printk(KERN_WARNING "broken BIOS!!\n");
 982                                         polarity = 1;
 983                                         break;
 984                                 }
 985                         }
 986                         break;
 987                 }
 988                 case 1: /* high active */
 989                 {
 990                         polarity = 0;
 991                         break;
 992                 }
 993                 case 2: /* reserved */
 994                 {
 995                         printk(KERN_WARNING "broken BIOS!!\n");
 996                         polarity = 1;
 997                         break;
 998                 }
 999                 case 3: /* low active */
1000                 {
1001                         polarity = 1;
1002                         break;
1003                 }
1004                 default: /* invalid */
1005                 {
1006                         printk(KERN_WARNING "broken BIOS!!\n");
1007                         polarity = 1;
1008                         break;
1009                 }
1010         }
1011         return polarity;
1012 }
1013
1014 static int MPBIOS_trigger(int idx)
1015 {
1016         int bus = mp_irqs[idx].mpc_srcbus;
1017         int trigger;
1018
1019         /*
1020          * Determine IRQ trigger mode (edge or level sensitive):
1021          */
1022         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
1023         {
1024                 case 0: /* conforms, ie. bus-type dependent */
1025                 {
1026                         switch (mp_bus_id_to_type[bus])
1027                         {
1028                                 case MP_BUS_ISA: /* ISA pin */
1029                                 {
1030                                         trigger = default_ISA_trigger(idx);
1031                                         break;
1032                                 }
1033                                 case MP_BUS_EISA: /* EISA pin */
1034                                 {
1035                                         trigger = default_EISA_trigger(idx);
1036                                         break;
1037                                 }
1038                                 case MP_BUS_PCI: /* PCI pin */
1039                                 {
1040                                         trigger = default_PCI_trigger(idx);
1041                                         break;
1042                                 }
1043                                 case MP_BUS_MCA: /* MCA pin */
1044                                 {
1045                                         trigger = default_MCA_trigger(idx);
1046                                         break;
1047                                 }
1048                                 case MP_BUS_NEC98: /* NEC 98 pin */
1049                                 {
1050                                         trigger = default_NEC98_trigger(idx);
1051                                         break;
1052                                 }
1053                                 default:
1054                                 {
1055                                         printk(KERN_WARNING "broken BIOS!!\n");
1056                                         trigger = 1;
1057                                         break;
1058                                 }
1059                         }
1060                         break;
1061                 }
1062                 case 1: /* edge */
1063                 {
1064                         trigger = 0;
1065                         break;
1066                 }
1067                 case 2: /* reserved */
1068                 {
1069                         printk(KERN_WARNING "broken BIOS!!\n");
1070                         trigger = 1;
1071                         break;
1072                 }
1073                 case 3: /* level */
1074                 {
1075                         trigger = 1;
1076                         break;
1077                 }
1078                 default: /* invalid */
1079                 {
1080                         printk(KERN_WARNING "broken BIOS!!\n");
1081                         trigger = 0;
1082                         break;
1083                 }
1084         }
1085         return trigger;
1086 }
1087
1088 static inline int irq_polarity(int idx)
1089 {
1090         return MPBIOS_polarity(idx);
1091 }
1092
1093 static inline int irq_trigger(int idx)
1094 {
1095         return MPBIOS_trigger(idx);
1096 }
1097
1098 static int pin_2_irq(int idx, int apic, int pin)
1099 {
1100         int irq, i;
1101         int bus = mp_irqs[idx].mpc_srcbus;
1102
1103         /*
1104          * Debugging check, we are in big trouble if this message pops up!
1105          */
1106         if (mp_irqs[idx].mpc_dstirq != pin)
1107                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1108
1109         switch (mp_bus_id_to_type[bus])
1110         {
1111                 case MP_BUS_ISA: /* ISA pin */
1112                 case MP_BUS_EISA:
1113                 case MP_BUS_MCA:
1114                 case MP_BUS_NEC98:
1115                 {
1116                         irq = mp_irqs[idx].mpc_srcbusirq;
1117                         break;
1118                 }
1119                 case MP_BUS_PCI: /* PCI pin */
1120                 {
1121                         /*
1122                          * PCI IRQs are mapped in order
1123                          */
1124                         i = irq = 0;
1125                         while (i < apic)
1126                                 irq += nr_ioapic_registers[i++];
1127                         irq += pin;
1128
1129                         /*
1130                          * For MPS mode, so far only needed by ES7000 platform
1131                          */
1132                         if (ioapic_renumber_irq)
1133                                 irq = ioapic_renumber_irq(apic, irq);
1134
1135                         break;
1136                 }
1137                 default:
1138                 {
1139                         printk(KERN_ERR "unknown bus type %d.\n",bus);
1140                         irq = 0;
1141                         break;
1142                 }
1143         }
1144
1145         /*
1146          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1147          */
1148         if ((pin >= 16) && (pin <= 23)) {
1149                 if (pirq_entries[pin-16] != -1) {
1150                         if (!pirq_entries[pin-16]) {
1151                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1152                                                 "disabling PIRQ%d\n", pin-16);
1153                         } else {
1154                                 irq = pirq_entries[pin-16];
1155                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1156                                                 "using PIRQ%d -> IRQ %d\n",
1157                                                 pin-16, irq);
1158                         }
1159                 }
1160         }
1161         return irq;
1162 }
1163
1164 static inline int IO_APIC_irq_trigger(int irq)
1165 {
1166         int apic, idx, pin;
1167
1168         for (apic = 0; apic < nr_ioapics; apic++) {
1169                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1170                         idx = find_irq_entry(apic,pin,mp_INT);
1171                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1172                                 return irq_trigger(idx);
1173                 }
1174         }
1175         /*
1176          * nonexistent IRQs are edge default
1177          */
1178         return 0;
1179 }
1180
1181 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1182 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1183
1184 int assign_irq_vector(int irq)
1185 {
1186         static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
1187         unsigned long flags;
1188         int vector;
1189
1190         BUG_ON(irq != AUTO_ASSIGN && (unsigned)irq >= NR_IRQ_VECTORS);
1191
1192         spin_lock_irqsave(&vector_lock, flags);
1193
1194         if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0) {
1195                 spin_unlock_irqrestore(&vector_lock, flags);
1196                 return IO_APIC_VECTOR(irq);
1197         }
1198 next:
1199         current_vector += 8;
1200         if (current_vector == SYSCALL_VECTOR)
1201                 goto next;
1202
1203         if (current_vector >= FIRST_SYSTEM_VECTOR) {
1204                 offset++;
1205                 if (!(offset%8)) {
1206                         spin_unlock_irqrestore(&vector_lock, flags);
1207                         return -ENOSPC;
1208                 }
1209                 current_vector = FIRST_DEVICE_VECTOR + offset;
1210         }
1211
1212         vector = current_vector;
1213         vector_irq[vector] = irq;
1214         if (irq != AUTO_ASSIGN)
1215                 IO_APIC_VECTOR(irq) = vector;
1216
1217         spin_unlock_irqrestore(&vector_lock, flags);
1218
1219         return vector;
1220 }
1221
1222 static struct hw_interrupt_type ioapic_level_type;
1223 static struct hw_interrupt_type ioapic_edge_type;
1224
1225 #define IOAPIC_AUTO     -1
1226 #define IOAPIC_EDGE     0
1227 #define IOAPIC_LEVEL    1
1228
1229 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1230 {
1231         unsigned idx;
1232
1233         idx = use_pci_vector() && !platform_legacy_irq(irq) ? vector : irq;
1234
1235         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1236                         trigger == IOAPIC_LEVEL)
1237                 irq_desc[idx].chip = &ioapic_level_type;
1238         else
1239                 irq_desc[idx].chip = &ioapic_edge_type;
1240         set_intr_gate(vector, interrupt[idx]);
1241 }
1242
1243 static void __init setup_IO_APIC_irqs(void)
1244 {
1245         struct IO_APIC_route_entry entry;
1246         int apic, pin, idx, irq, first_notcon = 1, vector;
1247         unsigned long flags;
1248
1249         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1250
1251         for (apic = 0; apic < nr_ioapics; apic++) {
1252         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1253
1254                 /*
1255                  * add it to the IO-APIC irq-routing table:
1256                  */
1257                 memset(&entry,0,sizeof(entry));
1258
1259                 entry.delivery_mode = INT_DELIVERY_MODE;
1260                 entry.dest_mode = INT_DEST_MODE;
1261                 entry.mask = 0;                         /* enable IRQ */
1262                 entry.dest.logical.logical_dest =
1263                                         cpu_mask_to_apicid(TARGET_CPUS);
1264
1265                 idx = find_irq_entry(apic,pin,mp_INT);
1266                 if (idx == -1) {
1267                         if (first_notcon) {
1268                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1269                                                 " IO-APIC (apicid-pin) %d-%d",
1270                                                 mp_ioapics[apic].mpc_apicid,
1271                                                 pin);
1272                                 first_notcon = 0;
1273                         } else
1274                                 apic_printk(APIC_VERBOSE, ", %d-%d",
1275                                         mp_ioapics[apic].mpc_apicid, pin);
1276                         continue;
1277                 }
1278
1279                 entry.trigger = irq_trigger(idx);
1280                 entry.polarity = irq_polarity(idx);
1281
1282                 if (irq_trigger(idx)) {
1283                         entry.trigger = 1;
1284                         entry.mask = 1;
1285                 }
1286
1287                 irq = pin_2_irq(idx, apic, pin);
1288                 /*
1289                  * skip adding the timer int on secondary nodes, which causes
1290                  * a small but painful rift in the time-space continuum
1291                  */
1292                 if (multi_timer_check(apic, irq))
1293                         continue;
1294                 else
1295                         add_pin_to_irq(irq, apic, pin);
1296
1297                 if (!apic && !IO_APIC_IRQ(irq))
1298                         continue;
1299
1300                 if (IO_APIC_IRQ(irq)) {
1301                         vector = assign_irq_vector(irq);
1302                         entry.vector = vector;
1303                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1304
1305                         if (!apic && (irq < 16))
1306                                 disable_8259A_irq(irq);
1307                 }
1308                 ioapic_write_entry(apic, pin, entry);
1309                 spin_lock_irqsave(&ioapic_lock, flags);
1310                 set_native_irq_info(irq, TARGET_CPUS);
1311                 spin_unlock_irqrestore(&ioapic_lock, flags);
1312         }
1313         }
1314
1315         if (!first_notcon)
1316                 apic_printk(APIC_VERBOSE, " not connected.\n");
1317 }
1318
1319 /*
1320  * Set up the 8259A-master output pin:
1321  */
1322 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1323 {
1324         struct IO_APIC_route_entry entry;
1325
1326         memset(&entry,0,sizeof(entry));
1327
1328         disable_8259A_irq(0);
1329
1330         /* mask LVT0 */
1331         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1332
1333         /*
1334          * We use logical delivery to get the timer IRQ
1335          * to the first CPU.
1336          */
1337         entry.dest_mode = INT_DEST_MODE;
1338         entry.mask = 0;                                 /* unmask IRQ now */
1339         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1340         entry.delivery_mode = INT_DELIVERY_MODE;
1341         entry.polarity = 0;
1342         entry.trigger = 0;
1343         entry.vector = vector;
1344
1345         /*
1346          * The timer IRQ doesn't have to know that behind the
1347          * scene we have a 8259A-master in AEOI mode ...
1348          */
1349         irq_desc[0].chip = &ioapic_edge_type;
1350
1351         /*
1352          * Add it to the IO-APIC irq-routing table:
1353          */
1354         ioapic_write_entry(apic, pin, entry);
1355
1356         enable_8259A_irq(0);
1357 }
1358
1359 static inline void UNEXPECTED_IO_APIC(void)
1360 {
1361 }
1362
1363 void __init print_IO_APIC(void)
1364 {
1365         int apic, i;
1366         union IO_APIC_reg_00 reg_00;
1367         union IO_APIC_reg_01 reg_01;
1368         union IO_APIC_reg_02 reg_02;
1369         union IO_APIC_reg_03 reg_03;
1370         unsigned long flags;
1371
1372         if (apic_verbosity == APIC_QUIET)
1373                 return;
1374
1375         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1376         for (i = 0; i < nr_ioapics; i++)
1377                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1378                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1379
1380         /*
1381          * We are a bit conservative about what we expect.  We have to
1382          * know about every hardware change ASAP.
1383          */
1384         printk(KERN_INFO "testing the IO APIC.......................\n");
1385
1386         for (apic = 0; apic < nr_ioapics; apic++) {
1387
1388         spin_lock_irqsave(&ioapic_lock, flags);
1389         reg_00.raw = io_apic_read(apic, 0);
1390         reg_01.raw = io_apic_read(apic, 1);
1391         if (reg_01.bits.version >= 0x10)
1392                 reg_02.raw = io_apic_read(apic, 2);
1393         if (reg_01.bits.version >= 0x20)
1394                 reg_03.raw = io_apic_read(apic, 3);
1395         spin_unlock_irqrestore(&ioapic_lock, flags);
1396
1397         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1398         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1399         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1400         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1401         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1402         if (reg_00.bits.ID >= get_physical_broadcast())
1403                 UNEXPECTED_IO_APIC();
1404         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1405                 UNEXPECTED_IO_APIC();
1406
1407         printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1408         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1409         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1410                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1411                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1412                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1413                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1414                 (reg_01.bits.entries != 0x2E) &&
1415                 (reg_01.bits.entries != 0x3F)
1416         )
1417                 UNEXPECTED_IO_APIC();
1418
1419         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1420         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1421         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1422                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1423                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1424                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1425                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
1426         )
1427                 UNEXPECTED_IO_APIC();
1428         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1429                 UNEXPECTED_IO_APIC();
1430
1431         /*
1432          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1433          * but the value of reg_02 is read as the previous read register
1434          * value, so ignore it if reg_02 == reg_01.
1435          */
1436         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1437                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1438                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1439                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1440                         UNEXPECTED_IO_APIC();
1441         }
1442
1443         /*
1444          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1445          * or reg_03, but the value of reg_0[23] is read as the previous read
1446          * register value, so ignore it if reg_03 == reg_0[12].
1447          */
1448         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1449             reg_03.raw != reg_01.raw) {
1450                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1451                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1452                 if (reg_03.bits.__reserved_1)
1453                         UNEXPECTED_IO_APIC();
1454         }
1455
1456         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1457
1458         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1459                           " Stat Dest Deli Vect:   \n");
1460
1461         for (i = 0; i <= reg_01.bits.entries; i++) {
1462                 struct IO_APIC_route_entry entry;
1463
1464                 entry = ioapic_read_entry(apic, i);
1465
1466                 printk(KERN_DEBUG " %02x %03X %02X  ",
1467                         i,
1468                         entry.dest.logical.logical_dest,
1469                         entry.dest.physical.physical_dest
1470                 );
1471
1472                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1473                         entry.mask,
1474                         entry.trigger,
1475                         entry.irr,
1476                         entry.polarity,
1477                         entry.delivery_status,
1478                         entry.dest_mode,
1479                         entry.delivery_mode,
1480                         entry.vector
1481                 );
1482         }
1483         }
1484         if (use_pci_vector())
1485                 printk(KERN_INFO "Using vector-based indexing\n");
1486         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1487         for (i = 0; i < NR_IRQS; i++) {
1488                 struct irq_pin_list *entry = irq_2_pin + i;
1489                 if (entry->pin < 0)
1490                         continue;
1491                 if (use_pci_vector() && !platform_legacy_irq(i))
1492                         printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1493                 else
1494                         printk(KERN_DEBUG "IRQ%d ", i);
1495                 for (;;) {
1496                         printk("-> %d:%d", entry->apic, entry->pin);
1497                         if (!entry->next)
1498                                 break;
1499                         entry = irq_2_pin + entry->next;
1500                 }
1501                 printk("\n");
1502         }
1503
1504         printk(KERN_INFO ".................................... done.\n");
1505
1506         return;
1507 }
1508
1509 #if 0
1510
1511 static void print_APIC_bitfield (int base)
1512 {
1513         unsigned int v;
1514         int i, j;
1515
1516         if (apic_verbosity == APIC_QUIET)
1517                 return;
1518
1519         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1520         for (i = 0; i < 8; i++) {
1521                 v = apic_read(base + i*0x10);
1522                 for (j = 0; j < 32; j++) {
1523                         if (v & (1<<j))
1524                                 printk("1");
1525                         else
1526                                 printk("0");
1527                 }
1528                 printk("\n");
1529         }
1530 }
1531
1532 void /*__init*/ print_local_APIC(void * dummy)
1533 {
1534         unsigned int v, ver, maxlvt;
1535
1536         if (apic_verbosity == APIC_QUIET)
1537                 return;
1538
1539         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1540                 smp_processor_id(), hard_smp_processor_id());
1541         v = apic_read(APIC_ID);
1542         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1543         v = apic_read(APIC_LVR);
1544         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1545         ver = GET_APIC_VERSION(v);
1546         maxlvt = get_maxlvt();
1547
1548         v = apic_read(APIC_TASKPRI);
1549         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1550
1551         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1552                 v = apic_read(APIC_ARBPRI);
1553                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1554                         v & APIC_ARBPRI_MASK);
1555                 v = apic_read(APIC_PROCPRI);
1556                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1557         }
1558
1559         v = apic_read(APIC_EOI);
1560         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1561         v = apic_read(APIC_RRR);
1562         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1563         v = apic_read(APIC_LDR);
1564         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1565         v = apic_read(APIC_DFR);
1566         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1567         v = apic_read(APIC_SPIV);
1568         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1569
1570         printk(KERN_DEBUG "... APIC ISR field:\n");
1571         print_APIC_bitfield(APIC_ISR);
1572         printk(KERN_DEBUG "... APIC TMR field:\n");
1573         print_APIC_bitfield(APIC_TMR);
1574         printk(KERN_DEBUG "... APIC IRR field:\n");
1575         print_APIC_bitfield(APIC_IRR);
1576
1577         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1578                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1579                         apic_write(APIC_ESR, 0);
1580                 v = apic_read(APIC_ESR);
1581                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1582         }
1583
1584         v = apic_read(APIC_ICR);
1585         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1586         v = apic_read(APIC_ICR2);
1587         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1588
1589         v = apic_read(APIC_LVTT);
1590         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1591
1592         if (maxlvt > 3) {                       /* PC is LVT#4. */
1593                 v = apic_read(APIC_LVTPC);
1594                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1595         }
1596         v = apic_read(APIC_LVT0);
1597         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1598         v = apic_read(APIC_LVT1);
1599         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1600
1601         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1602                 v = apic_read(APIC_LVTERR);
1603                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1604         }
1605
1606         v = apic_read(APIC_TMICT);
1607         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1608         v = apic_read(APIC_TMCCT);
1609         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1610         v = apic_read(APIC_TDCR);
1611         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1612         printk("\n");
1613 }
1614
1615 void print_all_local_APICs (void)
1616 {
1617         on_each_cpu(print_local_APIC, NULL, 1, 1);
1618 }
1619
1620 void /*__init*/ print_PIC(void)
1621 {
1622         unsigned int v;
1623         unsigned long flags;
1624
1625         if (apic_verbosity == APIC_QUIET)
1626                 return;
1627
1628         printk(KERN_DEBUG "\nprinting PIC contents\n");
1629
1630         spin_lock_irqsave(&i8259A_lock, flags);
1631
1632         v = inb(0xa1) << 8 | inb(0x21);
1633         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1634
1635         v = inb(0xa0) << 8 | inb(0x20);
1636         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1637
1638         outb(0x0b,0xa0);
1639         outb(0x0b,0x20);
1640         v = inb(0xa0) << 8 | inb(0x20);
1641         outb(0x0a,0xa0);
1642         outb(0x0a,0x20);
1643
1644         spin_unlock_irqrestore(&i8259A_lock, flags);
1645
1646         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1647
1648         v = inb(0x4d1) << 8 | inb(0x4d0);
1649         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1650 }
1651
1652 #endif  /*  0  */
1653
1654 static void __init enable_IO_APIC(void)
1655 {
1656         union IO_APIC_reg_01 reg_01;
1657         int i8259_apic, i8259_pin;
1658         int i, apic;
1659         unsigned long flags;
1660
1661         for (i = 0; i < PIN_MAP_SIZE; i++) {
1662                 irq_2_pin[i].pin = -1;
1663                 irq_2_pin[i].next = 0;
1664         }
1665         if (!pirqs_enabled)
1666                 for (i = 0; i < MAX_PIRQS; i++)
1667                         pirq_entries[i] = -1;
1668
1669         /*
1670          * The number of IO-APIC IRQ registers (== #pins):
1671          */
1672         for (apic = 0; apic < nr_ioapics; apic++) {
1673                 spin_lock_irqsave(&ioapic_lock, flags);
1674                 reg_01.raw = io_apic_read(apic, 1);
1675                 spin_unlock_irqrestore(&ioapic_lock, flags);
1676                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1677         }
1678         for(apic = 0; apic < nr_ioapics; apic++) {
1679                 int pin;
1680                 /* See if any of the pins is in ExtINT mode */
1681                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1682                         struct IO_APIC_route_entry entry;
1683                         entry = ioapic_read_entry(apic, pin);
1684
1685
1686                         /* If the interrupt line is enabled and in ExtInt mode
1687                          * I have found the pin where the i8259 is connected.
1688                          */
1689                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1690                                 ioapic_i8259.apic = apic;
1691                                 ioapic_i8259.pin  = pin;
1692                                 goto found_i8259;
1693                         }
1694                 }
1695         }
1696  found_i8259:
1697         /* Look to see what if the MP table has reported the ExtINT */
1698         /* If we could not find the appropriate pin by looking at the ioapic
1699          * the i8259 probably is not connected the ioapic but give the
1700          * mptable a chance anyway.
1701          */
1702         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1703         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1704         /* Trust the MP table if nothing is setup in the hardware */
1705         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1706                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1707                 ioapic_i8259.pin  = i8259_pin;
1708                 ioapic_i8259.apic = i8259_apic;
1709         }
1710         /* Complain if the MP table and the hardware disagree */
1711         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1712                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1713         {
1714                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1715         }
1716
1717         /*
1718          * Do not trust the IO-APIC being empty at bootup
1719          */
1720         clear_IO_APIC();
1721 }
1722
1723 /*
1724  * Not an __init, needed by the reboot code
1725  */
1726 void disable_IO_APIC(void)
1727 {
1728         /*
1729          * Clear the IO-APIC before rebooting:
1730          */
1731         clear_IO_APIC();
1732
1733         /*
1734          * If the i8259 is routed through an IOAPIC
1735          * Put that IOAPIC in virtual wire mode
1736          * so legacy interrupts can be delivered.
1737          */
1738         if (ioapic_i8259.pin != -1) {
1739                 struct IO_APIC_route_entry entry;
1740
1741                 memset(&entry, 0, sizeof(entry));
1742                 entry.mask            = 0; /* Enabled */
1743                 entry.trigger         = 0; /* Edge */
1744                 entry.irr             = 0;
1745                 entry.polarity        = 0; /* High */
1746                 entry.delivery_status = 0;
1747                 entry.dest_mode       = 0; /* Physical */
1748                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1749                 entry.vector          = 0;
1750                 entry.dest.physical.physical_dest =
1751                                         GET_APIC_ID(apic_read(APIC_ID));
1752
1753                 /*
1754                  * Add it to the IO-APIC irq-routing table:
1755                  */
1756                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1757         }
1758         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1759 }
1760
1761 /*
1762  * function to set the IO-APIC physical IDs based on the
1763  * values stored in the MPC table.
1764  *
1765  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1766  */
1767
1768 #ifndef CONFIG_X86_NUMAQ
1769 static void __init setup_ioapic_ids_from_mpc(void)
1770 {
1771         union IO_APIC_reg_00 reg_00;
1772         physid_mask_t phys_id_present_map;
1773         int apic;
1774         int i;
1775         unsigned char old_id;
1776         unsigned long flags;
1777
1778         /*
1779          * Don't check I/O APIC IDs for xAPIC systems.  They have
1780          * no meaning without the serial APIC bus.
1781          */
1782         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1783                 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1784                 return;
1785         /*
1786          * This is broken; anything with a real cpu count has to
1787          * circumvent this idiocy regardless.
1788          */
1789         phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1790
1791         /*
1792          * Set the IOAPIC ID to the value stored in the MPC table.
1793          */
1794         for (apic = 0; apic < nr_ioapics; apic++) {
1795
1796                 /* Read the register 0 value */
1797                 spin_lock_irqsave(&ioapic_lock, flags);
1798                 reg_00.raw = io_apic_read(apic, 0);
1799                 spin_unlock_irqrestore(&ioapic_lock, flags);
1800
1801                 old_id = mp_ioapics[apic].mpc_apicid;
1802
1803                 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1804                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1805                                 apic, mp_ioapics[apic].mpc_apicid);
1806                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1807                                 reg_00.bits.ID);
1808                         mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1809                 }
1810
1811                 /*
1812                  * Sanity check, is the ID really free? Every APIC in a
1813                  * system must have a unique ID or we get lots of nice
1814                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1815                  */
1816                 if (check_apicid_used(phys_id_present_map,
1817                                         mp_ioapics[apic].mpc_apicid)) {
1818                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1819                                 apic, mp_ioapics[apic].mpc_apicid);
1820                         for (i = 0; i < get_physical_broadcast(); i++)
1821                                 if (!physid_isset(i, phys_id_present_map))
1822                                         break;
1823                         if (i >= get_physical_broadcast())
1824                                 panic("Max APIC ID exceeded!\n");
1825                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1826                                 i);
1827                         physid_set(i, phys_id_present_map);
1828                         mp_ioapics[apic].mpc_apicid = i;
1829                 } else {
1830                         physid_mask_t tmp;
1831                         tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1832                         apic_printk(APIC_VERBOSE, "Setting %d in the "
1833                                         "phys_id_present_map\n",
1834                                         mp_ioapics[apic].mpc_apicid);
1835                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
1836                 }
1837
1838
1839                 /*
1840                  * We need to adjust the IRQ routing table
1841                  * if the ID changed.
1842                  */
1843                 if (old_id != mp_ioapics[apic].mpc_apicid)
1844                         for (i = 0; i < mp_irq_entries; i++)
1845                                 if (mp_irqs[i].mpc_dstapic == old_id)
1846                                         mp_irqs[i].mpc_dstapic
1847                                                 = mp_ioapics[apic].mpc_apicid;
1848
1849                 /*
1850                  * Read the right value from the MPC table and
1851                  * write it into the ID register.
1852                  */
1853                 apic_printk(APIC_VERBOSE, KERN_INFO
1854                         "...changing IO-APIC physical APIC ID to %d ...",
1855                         mp_ioapics[apic].mpc_apicid);
1856
1857                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1858                 spin_lock_irqsave(&ioapic_lock, flags);
1859                 io_apic_write(apic, 0, reg_00.raw);
1860                 spin_unlock_irqrestore(&ioapic_lock, flags);
1861
1862                 /*
1863                  * Sanity check
1864                  */
1865                 spin_lock_irqsave(&ioapic_lock, flags);
1866                 reg_00.raw = io_apic_read(apic, 0);
1867                 spin_unlock_irqrestore(&ioapic_lock, flags);
1868                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1869                         printk("could not set ID!\n");
1870                 else
1871                         apic_printk(APIC_VERBOSE, " ok.\n");
1872         }
1873 }
1874 #else
1875 static void __init setup_ioapic_ids_from_mpc(void) { }
1876 #endif
1877
1878 /*
1879  * There is a nasty bug in some older SMP boards, their mptable lies
1880  * about the timer IRQ. We do the following to work around the situation:
1881  *
1882  *      - timer IRQ defaults to IO-APIC IRQ
1883  *      - if this function detects that timer IRQs are defunct, then we fall
1884  *        back to ISA timer IRQs
1885  */
1886 static int __init timer_irq_works(void)
1887 {
1888         unsigned long t1 = jiffies;
1889
1890         local_irq_enable();
1891         /* Let ten ticks pass... */
1892         mdelay((10 * 1000) / HZ);
1893
1894         /*
1895          * Expect a few ticks at least, to be sure some possible
1896          * glue logic does not lock up after one or two first
1897          * ticks in a non-ExtINT mode.  Also the local APIC
1898          * might have cached one ExtINT interrupt.  Finally, at
1899          * least one tick may be lost due to delays.
1900          */
1901         if (jiffies - t1 > 4)
1902                 return 1;
1903
1904         return 0;
1905 }
1906
1907 /*
1908  * In the SMP+IOAPIC case it might happen that there are an unspecified
1909  * number of pending IRQ events unhandled. These cases are very rare,
1910  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1911  * better to do it this way as thus we do not have to be aware of
1912  * 'pending' interrupts in the IRQ path, except at this point.
1913  */
1914 /*
1915  * Edge triggered needs to resend any interrupt
1916  * that was delayed but this is now handled in the device
1917  * independent code.
1918  */
1919
1920 /*
1921  * Starting up a edge-triggered IO-APIC interrupt is
1922  * nasty - we need to make sure that we get the edge.
1923  * If it is already asserted for some reason, we need
1924  * return 1 to indicate that is was pending.
1925  *
1926  * This is not complete - we should be able to fake
1927  * an edge even if it isn't on the 8259A...
1928  */
1929 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1930 {
1931         int was_pending = 0;
1932         unsigned long flags;
1933
1934         spin_lock_irqsave(&ioapic_lock, flags);
1935         if (irq < 16) {
1936                 disable_8259A_irq(irq);
1937                 if (i8259A_irq_pending(irq))
1938                         was_pending = 1;
1939         }
1940         __unmask_IO_APIC_irq(irq);
1941         spin_unlock_irqrestore(&ioapic_lock, flags);
1942
1943         return was_pending;
1944 }
1945
1946 /*
1947  * Once we have recorded IRQ_PENDING already, we can mask the
1948  * interrupt for real. This prevents IRQ storms from unhandled
1949  * devices.
1950  */
1951 static void ack_edge_ioapic_irq(unsigned int irq)
1952 {
1953         move_irq(irq);
1954         if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1955                                         == (IRQ_PENDING | IRQ_DISABLED))
1956                 mask_IO_APIC_irq(irq);
1957         ack_APIC_irq();
1958 }
1959
1960 /*
1961  * Level triggered interrupts can just be masked,
1962  * and shutting down and starting up the interrupt
1963  * is the same as enabling and disabling them -- except
1964  * with a startup need to return a "was pending" value.
1965  *
1966  * Level triggered interrupts are special because we
1967  * do not touch any IO-APIC register while handling
1968  * them. We ack the APIC in the end-IRQ handler, not
1969  * in the start-IRQ-handler. Protection against reentrance
1970  * from the same interrupt is still provided, both by the
1971  * generic IRQ layer and by the fact that an unacked local
1972  * APIC does not accept IRQs.
1973  */
1974 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1975 {
1976         unmask_IO_APIC_irq(irq);
1977
1978         return 0; /* don't check for pending */
1979 }
1980
1981 static void end_level_ioapic_irq (unsigned int irq)
1982 {
1983         unsigned long v;
1984         int i;
1985
1986         move_irq(irq);
1987 /*
1988  * It appears there is an erratum which affects at least version 0x11
1989  * of I/O APIC (that's the 82093AA and cores integrated into various
1990  * chipsets).  Under certain conditions a level-triggered interrupt is
1991  * erroneously delivered as edge-triggered one but the respective IRR
1992  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1993  * message but it will never arrive and further interrupts are blocked
1994  * from the source.  The exact reason is so far unknown, but the
1995  * phenomenon was observed when two consecutive interrupt requests
1996  * from a given source get delivered to the same CPU and the source is
1997  * temporarily disabled in between.
1998  *
1999  * A workaround is to simulate an EOI message manually.  We achieve it
2000  * by setting the trigger mode to edge and then to level when the edge
2001  * trigger mode gets detected in the TMR of a local APIC for a
2002  * level-triggered interrupt.  We mask the source for the time of the
2003  * operation to prevent an edge-triggered interrupt escaping meanwhile.
2004  * The idea is from Manfred Spraul.  --macro
2005  */
2006         i = IO_APIC_VECTOR(irq);
2007
2008         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2009
2010         ack_APIC_irq();
2011
2012         if (!(v & (1 << (i & 0x1f)))) {
2013                 atomic_inc(&irq_mis_count);
2014                 spin_lock(&ioapic_lock);
2015                 __mask_and_edge_IO_APIC_irq(irq);
2016                 __unmask_and_level_IO_APIC_irq(irq);
2017                 spin_unlock(&ioapic_lock);
2018         }
2019 }
2020
2021 #ifdef CONFIG_PCI_MSI
2022 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
2023 {
2024         int irq = vector_to_irq(vector);
2025
2026         return startup_edge_ioapic_irq(irq);
2027 }
2028
2029 static void ack_edge_ioapic_vector(unsigned int vector)
2030 {
2031         int irq = vector_to_irq(vector);
2032
2033         move_native_irq(vector);
2034         ack_edge_ioapic_irq(irq);
2035 }
2036
2037 static unsigned int startup_level_ioapic_vector (unsigned int vector)
2038 {
2039         int irq = vector_to_irq(vector);
2040
2041         return startup_level_ioapic_irq (irq);
2042 }
2043
2044 static void end_level_ioapic_vector (unsigned int vector)
2045 {
2046         int irq = vector_to_irq(vector);
2047
2048         move_native_irq(vector);
2049         end_level_ioapic_irq(irq);
2050 }
2051
2052 static void mask_IO_APIC_vector (unsigned int vector)
2053 {
2054         int irq = vector_to_irq(vector);
2055
2056         mask_IO_APIC_irq(irq);
2057 }
2058
2059 static void unmask_IO_APIC_vector (unsigned int vector)
2060 {
2061         int irq = vector_to_irq(vector);
2062
2063         unmask_IO_APIC_irq(irq);
2064 }
2065
2066 #ifdef CONFIG_SMP
2067 static void set_ioapic_affinity_vector (unsigned int vector,
2068                                         cpumask_t cpu_mask)
2069 {
2070         int irq = vector_to_irq(vector);
2071
2072         set_native_irq_info(vector, cpu_mask);
2073         set_ioapic_affinity_irq(irq, cpu_mask);
2074 }
2075 #endif
2076 #endif
2077
2078 static int ioapic_retrigger(unsigned int irq)
2079 {
2080         send_IPI_self(IO_APIC_VECTOR(irq));
2081
2082         return 1;
2083 }
2084
2085 /*
2086  * Level and edge triggered IO-APIC interrupts need different handling,
2087  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2088  * handled with the level-triggered descriptor, but that one has slightly
2089  * more overhead. Level-triggered interrupts cannot be handled with the
2090  * edge-triggered handler, without risking IRQ storms and other ugly
2091  * races.
2092  */
2093 static struct hw_interrupt_type ioapic_edge_type __read_mostly = {
2094         .typename       = "IO-APIC-edge",
2095         .startup        = startup_edge_ioapic,
2096         .shutdown       = shutdown_edge_ioapic,
2097         .enable         = enable_edge_ioapic,
2098         .disable        = disable_edge_ioapic,
2099         .ack            = ack_edge_ioapic,
2100         .end            = end_edge_ioapic,
2101 #ifdef CONFIG_SMP
2102         .set_affinity   = set_ioapic_affinity,
2103 #endif
2104         .retrigger      = ioapic_retrigger,
2105 };
2106
2107 static struct hw_interrupt_type ioapic_level_type __read_mostly = {
2108         .typename       = "IO-APIC-level",
2109         .startup        = startup_level_ioapic,
2110         .shutdown       = shutdown_level_ioapic,
2111         .enable         = enable_level_ioapic,
2112         .disable        = disable_level_ioapic,
2113         .ack            = mask_and_ack_level_ioapic,
2114         .end            = end_level_ioapic,
2115 #ifdef CONFIG_SMP
2116         .set_affinity   = set_ioapic_affinity,
2117 #endif
2118         .retrigger      = ioapic_retrigger,
2119 };
2120
2121 static inline void init_IO_APIC_traps(void)
2122 {
2123         int irq;
2124
2125         /*
2126          * NOTE! The local APIC isn't very good at handling
2127          * multiple interrupts at the same interrupt level.
2128          * As the interrupt level is determined by taking the
2129          * vector number and shifting that right by 4, we
2130          * want to spread these out a bit so that they don't
2131          * all fall in the same interrupt level.
2132          *
2133          * Also, we've got to be careful not to trash gate
2134          * 0x80, because int 0x80 is hm, kind of importantish. ;)
2135          */
2136         for (irq = 0; irq < NR_IRQS ; irq++) {
2137                 int tmp = irq;
2138                 if (use_pci_vector()) {
2139                         if (!platform_legacy_irq(tmp))
2140                                 if ((tmp = vector_to_irq(tmp)) == -1)
2141                                         continue;
2142                 }
2143                 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
2144                         /*
2145                          * Hmm.. We don't have an entry for this,
2146                          * so default to an old-fashioned 8259
2147                          * interrupt if we can..
2148                          */
2149                         if (irq < 16)
2150                                 make_8259A_irq(irq);
2151                         else
2152                                 /* Strange. Oh, well.. */
2153                                 irq_desc[irq].chip = &no_irq_type;
2154                 }
2155         }
2156 }
2157
2158 static void enable_lapic_irq (unsigned int irq)
2159 {
2160         unsigned long v;
2161
2162         v = apic_read(APIC_LVT0);
2163         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2164 }
2165
2166 static void disable_lapic_irq (unsigned int irq)
2167 {
2168         unsigned long v;
2169
2170         v = apic_read(APIC_LVT0);
2171         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2172 }
2173
2174 static void ack_lapic_irq (unsigned int irq)
2175 {
2176         ack_APIC_irq();
2177 }
2178
2179 static void end_lapic_irq (unsigned int i) { /* nothing */ }
2180
2181 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
2182         .typename       = "local-APIC-edge",
2183         .startup        = NULL, /* startup_irq() not used for IRQ0 */
2184         .shutdown       = NULL, /* shutdown_irq() not used for IRQ0 */
2185         .enable         = enable_lapic_irq,
2186         .disable        = disable_lapic_irq,
2187         .ack            = ack_lapic_irq,
2188         .end            = end_lapic_irq
2189 };
2190
2191 static void setup_nmi (void)
2192 {
2193         /*
2194          * Dirty trick to enable the NMI watchdog ...
2195          * We put the 8259A master into AEOI mode and
2196          * unmask on all local APICs LVT0 as NMI.
2197          *
2198          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2199          * is from Maciej W. Rozycki - so we do not have to EOI from
2200          * the NMI handler or the timer interrupt.
2201          */
2202         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2203
2204         on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
2205
2206         apic_printk(APIC_VERBOSE, " done.\n");
2207 }
2208
2209 /*
2210  * This looks a bit hackish but it's about the only one way of sending
2211  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2212  * not support the ExtINT mode, unfortunately.  We need to send these
2213  * cycles as some i82489DX-based boards have glue logic that keeps the
2214  * 8259A interrupt line asserted until INTA.  --macro
2215  */
2216 static inline void unlock_ExtINT_logic(void)
2217 {
2218         int apic, pin, i;
2219         struct IO_APIC_route_entry entry0, entry1;
2220         unsigned char save_control, save_freq_select;
2221
2222         pin  = find_isa_irq_pin(8, mp_INT);
2223         apic = find_isa_irq_apic(8, mp_INT);
2224         if (pin == -1)
2225                 return;
2226
2227         entry0 = ioapic_read_entry(apic, pin);
2228         clear_IO_APIC_pin(apic, pin);
2229
2230         memset(&entry1, 0, sizeof(entry1));
2231
2232         entry1.dest_mode = 0;                   /* physical delivery */
2233         entry1.mask = 0;                        /* unmask IRQ now */
2234         entry1.dest.physical.physical_dest = hard_smp_processor_id();
2235         entry1.delivery_mode = dest_ExtINT;
2236         entry1.polarity = entry0.polarity;
2237         entry1.trigger = 0;
2238         entry1.vector = 0;
2239
2240         ioapic_write_entry(apic, pin, entry1);
2241
2242         save_control = CMOS_READ(RTC_CONTROL);
2243         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2244         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2245                    RTC_FREQ_SELECT);
2246         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2247
2248         i = 100;
2249         while (i-- > 0) {
2250                 mdelay(10);
2251                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2252                         i -= 10;
2253         }
2254
2255         CMOS_WRITE(save_control, RTC_CONTROL);
2256         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2257         clear_IO_APIC_pin(apic, pin);
2258
2259         ioapic_write_entry(apic, pin, entry0);
2260 }
2261
2262 int timer_uses_ioapic_pin_0;
2263
2264 /*
2265  * This code may look a bit paranoid, but it's supposed to cooperate with
2266  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2267  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2268  * fanatically on his truly buggy board.
2269  */
2270 static inline void check_timer(void)
2271 {
2272         int apic1, pin1, apic2, pin2;
2273         int vector;
2274
2275         /*
2276          * get/set the timer IRQ vector:
2277          */
2278         disable_8259A_irq(0);
2279         vector = assign_irq_vector(0);
2280         set_intr_gate(vector, interrupt[0]);
2281
2282         /*
2283          * Subtle, code in do_timer_interrupt() expects an AEOI
2284          * mode for the 8259A whenever interrupts are routed
2285          * through I/O APICs.  Also IRQ0 has to be enabled in
2286          * the 8259A which implies the virtual wire has to be
2287          * disabled in the local APIC.
2288          */
2289         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2290         init_8259A(1);
2291         timer_ack = 1;
2292         if (timer_over_8254 > 0)
2293                 enable_8259A_irq(0);
2294
2295         pin1  = find_isa_irq_pin(0, mp_INT);
2296         apic1 = find_isa_irq_apic(0, mp_INT);
2297         pin2  = ioapic_i8259.pin;
2298         apic2 = ioapic_i8259.apic;
2299
2300         if (pin1 == 0)
2301                 timer_uses_ioapic_pin_0 = 1;
2302
2303         printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2304                 vector, apic1, pin1, apic2, pin2);
2305
2306         if (pin1 != -1) {
2307                 /*
2308                  * Ok, does IRQ0 through the IOAPIC work?
2309                  */
2310                 unmask_IO_APIC_irq(0);
2311                 if (timer_irq_works()) {
2312                         if (nmi_watchdog == NMI_IO_APIC) {
2313                                 disable_8259A_irq(0);
2314                                 setup_nmi();
2315                                 enable_8259A_irq(0);
2316                         }
2317                         if (disable_timer_pin_1 > 0)
2318                                 clear_IO_APIC_pin(0, pin1);
2319                         return;
2320                 }
2321                 clear_IO_APIC_pin(apic1, pin1);
2322                 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2323                                 "IO-APIC\n");
2324         }
2325
2326         printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2327         if (pin2 != -1) {
2328                 printk("\n..... (found pin %d) ...", pin2);
2329                 /*
2330                  * legacy devices should be connected to IO APIC #0
2331                  */
2332                 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
2333                 if (timer_irq_works()) {
2334                         printk("works.\n");
2335                         if (pin1 != -1)
2336                                 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2337                         else
2338                                 add_pin_to_irq(0, apic2, pin2);
2339                         if (nmi_watchdog == NMI_IO_APIC) {
2340                                 setup_nmi();
2341                         }
2342                         return;
2343                 }
2344                 /*
2345                  * Cleanup, just in case ...
2346                  */
2347                 clear_IO_APIC_pin(apic2, pin2);
2348         }
2349         printk(" failed.\n");
2350
2351         if (nmi_watchdog == NMI_IO_APIC) {
2352                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2353                 nmi_watchdog = 0;
2354         }
2355
2356         printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2357
2358         disable_8259A_irq(0);
2359         irq_desc[0].chip = &lapic_irq_type;
2360         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
2361         enable_8259A_irq(0);
2362
2363         if (timer_irq_works()) {
2364                 printk(" works.\n");
2365                 return;
2366         }
2367         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2368         printk(" failed.\n");
2369
2370         printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2371
2372         timer_ack = 0;
2373         init_8259A(0);
2374         make_8259A_irq(0);
2375         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2376
2377         unlock_ExtINT_logic();
2378
2379         if (timer_irq_works()) {
2380                 printk(" works.\n");
2381                 return;
2382         }
2383         printk(" failed :(.\n");
2384         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2385                 "report.  Then try booting with the 'noapic' option");
2386 }
2387
2388 /*
2389  *
2390  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2391  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2392  *   Linux doesn't really care, as it's not actually used
2393  *   for any interrupt handling anyway.
2394  */
2395 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
2396
2397 void __init setup_IO_APIC(void)
2398 {
2399         enable_IO_APIC();
2400
2401         if (acpi_ioapic)
2402                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
2403         else
2404                 io_apic_irqs = ~PIC_IRQS;
2405
2406         printk("ENABLING IO-APIC IRQs\n");
2407
2408         /*
2409          * Set up IO-APIC IRQ routing.
2410          */
2411         if (!acpi_ioapic)
2412                 setup_ioapic_ids_from_mpc();
2413         sync_Arb_IDs();
2414         setup_IO_APIC_irqs();
2415         init_IO_APIC_traps();
2416         check_timer();
2417         if (!acpi_ioapic)
2418                 print_IO_APIC();
2419 }
2420
2421 static int __init setup_disable_8254_timer(char *s)
2422 {
2423         timer_over_8254 = -1;
2424         return 1;
2425 }
2426 static int __init setup_enable_8254_timer(char *s)
2427 {
2428         timer_over_8254 = 2;
2429         return 1;
2430 }
2431
2432 __setup("disable_8254_timer", setup_disable_8254_timer);
2433 __setup("enable_8254_timer", setup_enable_8254_timer);
2434
2435 /*
2436  *      Called after all the initialization is done. If we didnt find any
2437  *      APIC bugs then we can allow the modify fast path
2438  */
2439
2440 static int __init io_apic_bug_finalize(void)
2441 {
2442         if(sis_apic_bug == -1)
2443                 sis_apic_bug = 0;
2444         return 0;
2445 }
2446
2447 late_initcall(io_apic_bug_finalize);
2448
2449 struct sysfs_ioapic_data {
2450         struct sys_device dev;
2451         struct IO_APIC_route_entry entry[0];
2452 };
2453 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2454
2455 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2456 {
2457         struct IO_APIC_route_entry *entry;
2458         struct sysfs_ioapic_data *data;
2459         int i;
2460
2461         data = container_of(dev, struct sysfs_ioapic_data, dev);
2462         entry = data->entry;
2463         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2464                 entry[i] = ioapic_read_entry(dev->id, i);
2465
2466         return 0;
2467 }
2468
2469 static int ioapic_resume(struct sys_device *dev)
2470 {
2471         struct IO_APIC_route_entry *entry;
2472         struct sysfs_ioapic_data *data;
2473         unsigned long flags;
2474         union IO_APIC_reg_00 reg_00;
2475         int i;
2476
2477         data = container_of(dev, struct sysfs_ioapic_data, dev);
2478         entry = data->entry;
2479
2480         spin_lock_irqsave(&ioapic_lock, flags);
2481         reg_00.raw = io_apic_read(dev->id, 0);
2482         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2483                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2484                 io_apic_write(dev->id, 0, reg_00.raw);
2485         }
2486         spin_unlock_irqrestore(&ioapic_lock, flags);
2487         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2488                 ioapic_write_entry(dev->id, i, entry[i]);
2489
2490         return 0;
2491 }
2492
2493 static struct sysdev_class ioapic_sysdev_class = {
2494         set_kset_name("ioapic"),
2495         .suspend = ioapic_suspend,
2496         .resume = ioapic_resume,
2497 };
2498
2499 static int __init ioapic_init_sysfs(void)
2500 {
2501         struct sys_device * dev;
2502         int i, size, error = 0;
2503
2504         error = sysdev_class_register(&ioapic_sysdev_class);
2505         if (error)
2506                 return error;
2507
2508         for (i = 0; i < nr_ioapics; i++ ) {
2509                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2510                         * sizeof(struct IO_APIC_route_entry);
2511                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2512                 if (!mp_ioapic_data[i]) {
2513                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2514                         continue;
2515                 }
2516                 memset(mp_ioapic_data[i], 0, size);
2517                 dev = &mp_ioapic_data[i]->dev;
2518                 dev->id = i;
2519                 dev->cls = &ioapic_sysdev_class;
2520                 error = sysdev_register(dev);
2521                 if (error) {
2522                         kfree(mp_ioapic_data[i]);
2523                         mp_ioapic_data[i] = NULL;
2524                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2525                         continue;
2526                 }
2527         }
2528
2529         return 0;
2530 }
2531
2532 device_initcall(ioapic_init_sysfs);
2533
2534 /* --------------------------------------------------------------------------
2535                           ACPI-based IOAPIC Configuration
2536    -------------------------------------------------------------------------- */
2537
2538 #ifdef CONFIG_ACPI
2539
2540 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2541 {
2542         union IO_APIC_reg_00 reg_00;
2543         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2544         physid_mask_t tmp;
2545         unsigned long flags;
2546         int i = 0;
2547
2548         /*
2549          * The P4 platform supports up to 256 APIC IDs on two separate APIC
2550          * buses (one for LAPICs, one for IOAPICs), where predecessors only
2551          * supports up to 16 on one shared APIC bus.
2552          *
2553          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2554          *      advantage of new APIC bus architecture.
2555          */
2556
2557         if (physids_empty(apic_id_map))
2558                 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2559
2560         spin_lock_irqsave(&ioapic_lock, flags);
2561         reg_00.raw = io_apic_read(ioapic, 0);
2562         spin_unlock_irqrestore(&ioapic_lock, flags);
2563
2564         if (apic_id >= get_physical_broadcast()) {
2565                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2566                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
2567                 apic_id = reg_00.bits.ID;
2568         }
2569
2570         /*
2571          * Every APIC in a system must have a unique ID or we get lots of nice
2572          * 'stuck on smp_invalidate_needed IPI wait' messages.
2573          */
2574         if (check_apicid_used(apic_id_map, apic_id)) {
2575
2576                 for (i = 0; i < get_physical_broadcast(); i++) {
2577                         if (!check_apicid_used(apic_id_map, i))
2578                                 break;
2579                 }
2580
2581                 if (i == get_physical_broadcast())
2582                         panic("Max apic_id exceeded!\n");
2583
2584                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2585                         "trying %d\n", ioapic, apic_id, i);
2586
2587                 apic_id = i;
2588         }
2589
2590         tmp = apicid_to_cpu_present(apic_id);
2591         physids_or(apic_id_map, apic_id_map, tmp);
2592
2593         if (reg_00.bits.ID != apic_id) {
2594                 reg_00.bits.ID = apic_id;
2595
2596                 spin_lock_irqsave(&ioapic_lock, flags);
2597                 io_apic_write(ioapic, 0, reg_00.raw);
2598                 reg_00.raw = io_apic_read(ioapic, 0);
2599                 spin_unlock_irqrestore(&ioapic_lock, flags);
2600
2601                 /* Sanity check */
2602                 if (reg_00.bits.ID != apic_id) {
2603                         printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2604                         return -1;
2605                 }
2606         }
2607
2608         apic_printk(APIC_VERBOSE, KERN_INFO
2609                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2610
2611         return apic_id;
2612 }
2613
2614
2615 int __init io_apic_get_version (int ioapic)
2616 {
2617         union IO_APIC_reg_01    reg_01;
2618         unsigned long flags;
2619
2620         spin_lock_irqsave(&ioapic_lock, flags);
2621         reg_01.raw = io_apic_read(ioapic, 1);
2622         spin_unlock_irqrestore(&ioapic_lock, flags);
2623
2624         return reg_01.bits.version;
2625 }
2626
2627
2628 int __init io_apic_get_redir_entries (int ioapic)
2629 {
2630         union IO_APIC_reg_01    reg_01;
2631         unsigned long flags;
2632
2633         spin_lock_irqsave(&ioapic_lock, flags);
2634         reg_01.raw = io_apic_read(ioapic, 1);
2635         spin_unlock_irqrestore(&ioapic_lock, flags);
2636
2637         return reg_01.bits.entries;
2638 }
2639
2640
2641 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2642 {
2643         struct IO_APIC_route_entry entry;
2644         unsigned long flags;
2645
2646         if (!IO_APIC_IRQ(irq)) {
2647                 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2648                         ioapic);
2649                 return -EINVAL;
2650         }
2651
2652         /*
2653          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2654          * Note that we mask (disable) IRQs now -- these get enabled when the
2655          * corresponding device driver registers for this IRQ.
2656          */
2657
2658         memset(&entry,0,sizeof(entry));
2659
2660         entry.delivery_mode = INT_DELIVERY_MODE;
2661         entry.dest_mode = INT_DEST_MODE;
2662         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2663         entry.trigger = edge_level;
2664         entry.polarity = active_high_low;
2665         entry.mask  = 1;
2666
2667         /*
2668          * IRQs < 16 are already in the irq_2_pin[] map
2669          */
2670         if (irq >= 16)
2671                 add_pin_to_irq(irq, ioapic, pin);
2672
2673         entry.vector = assign_irq_vector(irq);
2674
2675         apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2676                 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2677                 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2678                 edge_level, active_high_low);
2679
2680         ioapic_register_intr(irq, entry.vector, edge_level);
2681
2682         if (!ioapic && (irq < 16))
2683                 disable_8259A_irq(irq);
2684
2685         ioapic_write_entry(ioapic, pin, entry);
2686         spin_lock_irqsave(&ioapic_lock, flags);
2687         set_native_irq_info(use_pci_vector() ? entry.vector : irq, TARGET_CPUS);
2688         spin_unlock_irqrestore(&ioapic_lock, flags);
2689
2690         return 0;
2691 }
2692
2693 #endif /* CONFIG_ACPI */
2694
2695 static int __init parse_disable_timer_pin_1(char *arg)
2696 {
2697         disable_timer_pin_1 = 1;
2698         return 0;
2699 }
2700 early_param("disable_timer_pin_1", parse_disable_timer_pin_1);
2701
2702 static int __init parse_enable_timer_pin_1(char *arg)
2703 {
2704         disable_timer_pin_1 = -1;
2705         return 0;
2706 }
2707 early_param("enable_timer_pin_1", parse_enable_timer_pin_1);
2708
2709 static int __init parse_noapic(char *arg)
2710 {
2711         /* disable IO-APIC */
2712         disable_ioapic_setup();
2713         return 0;
2714 }
2715 early_param("noapic", parse_noapic);