arch/i386/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/config.h>
  29 #include <linux/smp_lock.h>
  30 #include <linux/mc146818rtc.h>
  31 #include <linux/compiler.h>
  32 #include <linux/acpi.h>
  33 #include <linux/module.h>
  34 #include <linux/sysdev.h>
  35
  36 #include <asm/io.h>
  37 #include <asm/smp.h>
  38 #include <asm/desc.h>
  39 #include <asm/timer.h>
  40 #include <asm/i8259.h>
  41
  42 #include <mach_apic.h>
  43
  44 #include "io_ports.h"
  45
  46 int (*ioapic_renumber_irq)(int ioapic, int irq);
  47 atomic_t irq_mis_count;
  48
  49 /* Where if anywhere is the i8259 connect in external int mode */
  50 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
  51
  52 static DEFINE_SPINLOCK(ioapic_lock);
  53
  54 int timer_over_8254 __initdata = 1;
  55
  56 /*
  57  *      Is the SiS APIC rmw bug present ?
  58  *      -1 = don't know, 0 = no, 1 = yes
  59  */
  60 int sis_apic_bug = -1;
  61
  62 /*
  63  * # of IRQ routing registers
  64  */
  65 int nr_ioapic_registers[MAX_IO_APICS];
  66
  67 int disable_timer_pin_1 __initdata;
  68
  69 /*
  70  * Rough estimation of how many shared IRQs there are, can
  71  * be changed anytime.
  72  */
  73 #define MAX_PLUS_SHARED_IRQS NR_IRQS
  74 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  75
  76 /*
  77  * This is performance-critical, we want to do it O(1)
  78  *
  79  * the indexing order of this array favors 1:1 mappings
  80  * between pins and IRQs.
  81  */
  82
  83 static struct irq_pin_list {
  84         int apic, pin, next;
  85 } irq_2_pin[PIN_MAP_SIZE];
  86
  87 int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
  88 #ifdef CONFIG_PCI_MSI
  89 #define vector_to_irq(vector)   \
  90         (platform_legacy_irq(vector) ? vector : vector_irq[vector])
  91 #else
  92 #define vector_to_irq(vector)   (vector)
  93 #endif
  94
  95 /*
  96  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
  97  * shared ISA-space IRQs, so we have to support them. We are super
  98  * fast in the common case, and fast for shared ISA-space IRQs.
  99  */
 100 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 101 {
 102         static int first_free_entry = NR_IRQS;
 103         struct irq_pin_list *entry = irq_2_pin + irq;
 104
 105         while (entry->next)
 106                 entry = irq_2_pin + entry->next;
 107
 108         if (entry->pin != -1) {
 109                 entry->next = first_free_entry;
 110                 entry = irq_2_pin + entry->next;
 111                 if (++first_free_entry >= PIN_MAP_SIZE)
 112                         panic("io_apic.c: whoops");
 113         }
 114         entry->apic = apic;
 115         entry->pin = pin;
 116 }
 117
 118 /*
 119  * Reroute an IRQ to a different pin.
 120  */
 121 static void __init replace_pin_at_irq(unsigned int irq,
 122                                       int oldapic, int oldpin,
 123                                       int newapic, int newpin)
 124 {
 125         struct irq_pin_list *entry = irq_2_pin + irq;
 126
 127         while (1) {
 128                 if (entry->apic == oldapic && entry->pin == oldpin) {
 129                         entry->apic = newapic;
 130                         entry->pin = newpin;
 131                 }
 132                 if (!entry->next)
 133                         break;
 134                 entry = irq_2_pin + entry->next;
 135         }
 136 }
 137
 138 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
 139 {
 140         struct irq_pin_list *entry = irq_2_pin + irq;
 141         unsigned int pin, reg;
 142
 143         for (;;) {
 144                 pin = entry->pin;
 145                 if (pin == -1)
 146                         break;
 147                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
 148                 reg &= ~disable;
 149                 reg |= enable;
 150                 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
 151                 if (!entry->next)
 152                         break;
 153                 entry = irq_2_pin + entry->next;
 154         }
 155 }
 156
 157 /* mask = 1 */
 158 static void __mask_IO_APIC_irq (unsigned int irq)
 159 {
 160         __modify_IO_APIC_irq(irq, 0x00010000, 0);
 161 }
 162
 163 /* mask = 0 */
 164 static void __unmask_IO_APIC_irq (unsigned int irq)
 165 {
 166         __modify_IO_APIC_irq(irq, 0, 0x00010000);
 167 }
 168
 169 /* mask = 1, trigger = 0 */
 170 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
 171 {
 172         __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
 173 }
 174
 175 /* mask = 0, trigger = 1 */
 176 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
 177 {
 178         __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
 179 }
 180
 181 static void mask_IO_APIC_irq (unsigned int irq)
 182 {
 183         unsigned long flags;
 184
 185         spin_lock_irqsave(&ioapic_lock, flags);
 186         __mask_IO_APIC_irq(irq);
 187         spin_unlock_irqrestore(&ioapic_lock, flags);
 188 }
 189
 190 static void unmask_IO_APIC_irq (unsigned int irq)
 191 {
 192         unsigned long flags;
 193
 194         spin_lock_irqsave(&ioapic_lock, flags);
 195         __unmask_IO_APIC_irq(irq);
 196         spin_unlock_irqrestore(&ioapic_lock, flags);
 197 }
 198
 199 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 200 {
 201         struct IO_APIC_route_entry entry;
 202         unsigned long flags;
 203
 204         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 205         spin_lock_irqsave(&ioapic_lock, flags);
 206         *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
 207         *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
 208         spin_unlock_irqrestore(&ioapic_lock, flags);
 209         if (entry.delivery_mode == dest_SMI)
 210                 return;
 211
 212         /*
 213          * Disable it in the IO-APIC irq-routing table:
 214          */
 215         memset(&entry, 0, sizeof(entry));
 216         entry.mask = 1;
 217         spin_lock_irqsave(&ioapic_lock, flags);
 218         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
 219         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
 220         spin_unlock_irqrestore(&ioapic_lock, flags);
 221 }
 222
 223 static void clear_IO_APIC (void)
 224 {
 225         int apic, pin;
 226
 227         for (apic = 0; apic < nr_ioapics; apic++)
 228                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 229                         clear_IO_APIC_pin(apic, pin);
 230 }
 231
 232 #ifdef CONFIG_SMP
 233 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
 234 {
 235         unsigned long flags;
 236         int pin;
 237         struct irq_pin_list *entry = irq_2_pin + irq;
 238         unsigned int apicid_value;
 239         cpumask_t tmp;
 240
 241         cpus_and(tmp, cpumask, cpu_online_map);
 242         if (cpus_empty(tmp))
 243                 tmp = TARGET_CPUS;
 244
 245         cpus_and(cpumask, tmp, CPU_MASK_ALL);
 246
 247         apicid_value = cpu_mask_to_apicid(cpumask);
 248         /* Prepare to do the io_apic_write */
 249         apicid_value = apicid_value << 24;
 250         spin_lock_irqsave(&ioapic_lock, flags);
 251         for (;;) {
 252                 pin = entry->pin;
 253                 if (pin == -1)
 254                         break;
 255                 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
 256                 if (!entry->next)
 257                         break;
 258                 entry = irq_2_pin + entry->next;
 259         }
 260         set_irq_info(irq, cpumask);
 261         spin_unlock_irqrestore(&ioapic_lock, flags);
 262 }
 263
 264 #if defined(CONFIG_IRQBALANCE)
 265 # include <asm/processor.h>     /* kernel_thread() */
 266 # include <linux/kernel_stat.h> /* kstat */
 267 # include <linux/slab.h>                /* kmalloc() */
 268 # include <linux/timer.h>       /* time_after() */
 269
 270 # ifdef CONFIG_BALANCED_IRQ_DEBUG
 271 #  define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
 272 #  define Dprintk(x...) do { TDprintk(x); } while (0)
 273 # else
 274 #  define TDprintk(x...)
 275 #  define Dprintk(x...)
 276 # endif
 277
 278
 279 #define IRQBALANCE_CHECK_ARCH -999
 280 static int irqbalance_disabled = IRQBALANCE_CHECK_ARCH;
 281 static int physical_balance = 0;
 282
 283 static struct irq_cpu_info {
 284         unsigned long * last_irq;
 285         unsigned long * irq_delta;
 286         unsigned long irq;
 287 } irq_cpu_data[NR_CPUS];
 288
 289 #define CPU_IRQ(cpu)            (irq_cpu_data[cpu].irq)
 290 #define LAST_CPU_IRQ(cpu,irq)   (irq_cpu_data[cpu].last_irq[irq])
 291 #define IRQ_DELTA(cpu,irq)      (irq_cpu_data[cpu].irq_delta[irq])
 292
 293 #define IDLE_ENOUGH(cpu,now) \
 294         (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
 295
 296 #define IRQ_ALLOWED(cpu, allowed_mask)  cpu_isset(cpu, allowed_mask)
 297
 298 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
 299
 300 #define MAX_BALANCED_IRQ_INTERVAL       (5*HZ)
 301 #define MIN_BALANCED_IRQ_INTERVAL       (HZ/2)
 302 #define BALANCED_IRQ_MORE_DELTA         (HZ/10)
 303 #define BALANCED_IRQ_LESS_DELTA         (HZ)
 304
 305 static long balanced_irq_interval = MAX_BALANCED_IRQ_INTERVAL;
 306
 307 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
 308                         unsigned long now, int direction)
 309 {
 310         int search_idle = 1;
 311         int cpu = curr_cpu;
 312
 313         goto inside;
 314
 315         do {
 316                 if (unlikely(cpu == curr_cpu))
 317                         search_idle = 0;
 318 inside:
 319                 if (direction == 1) {
 320                         cpu++;
 321                         if (cpu >= NR_CPUS)
 322                                 cpu = 0;
 323                 } else {
 324                         cpu--;
 325                         if (cpu == -1)
 326                                 cpu = NR_CPUS-1;
 327                 }
 328         } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
 329                         (search_idle && !IDLE_ENOUGH(cpu,now)));
 330
 331         return cpu;
 332 }
 333
 334 static inline void balance_irq(int cpu, int irq)
 335 {
 336         unsigned long now = jiffies;
 337         cpumask_t allowed_mask;
 338         unsigned int new_cpu;
 339
 340         if (irqbalance_disabled)
 341                 return;
 342
 343         cpus_and(allowed_mask, cpu_online_map, irq_affinity[irq]);
 344         new_cpu = move(cpu, allowed_mask, now, 1);
 345         if (cpu != new_cpu) {
 346                 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
 347         }
 348 }
 349
 350 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
 351 {
 352         int i, j;
 353         Dprintk("Rotating IRQs among CPUs.\n");
 354         for_each_online_cpu(i) {
 355                 for (j = 0; j < NR_IRQS; j++) {
 356                         if (!irq_desc[j].action)
 357                                 continue;
 358                         /* Is it a significant load ?  */
 359                         if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
 360                                                 useful_load_threshold)
 361                                 continue;
 362                         balance_irq(i, j);
 363                 }
 364         }
 365         balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 366                 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 367         return;
 368 }
 369
 370 static void do_irq_balance(void)
 371 {
 372         int i, j;
 373         unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
 374         unsigned long move_this_load = 0;
 375         int max_loaded = 0, min_loaded = 0;
 376         int load;
 377         unsigned long useful_load_threshold = balanced_irq_interval + 10;
 378         int selected_irq;
 379         int tmp_loaded, first_attempt = 1;
 380         unsigned long tmp_cpu_irq;
 381         unsigned long imbalance = 0;
 382         cpumask_t allowed_mask, target_cpu_mask, tmp;
 383
 384         for_each_possible_cpu(i) {
 385                 int package_index;
 386                 CPU_IRQ(i) = 0;
 387                 if (!cpu_online(i))
 388                         continue;
 389                 package_index = CPU_TO_PACKAGEINDEX(i);
 390                 for (j = 0; j < NR_IRQS; j++) {
 391                         unsigned long value_now, delta;
 392                         /* Is this an active IRQ? */
 393                         if (!irq_desc[j].action)
 394                                 continue;
 395                         if ( package_index == i )
 396                                 IRQ_DELTA(package_index,j) = 0;
 397                         /* Determine the total count per processor per IRQ */
 398                         value_now = (unsigned long) kstat_cpu(i).irqs[j];
 399
 400                         /* Determine the activity per processor per IRQ */
 401                         delta = value_now - LAST_CPU_IRQ(i,j);
 402
 403                         /* Update last_cpu_irq[][] for the next time */
 404                         LAST_CPU_IRQ(i,j) = value_now;
 405
 406                         /* Ignore IRQs whose rate is less than the clock */
 407                         if (delta < useful_load_threshold)
 408                                 continue;
 409                         /* update the load for the processor or package total */
 410                         IRQ_DELTA(package_index,j) += delta;
 411
 412                         /* Keep track of the higher numbered sibling as well */
 413                         if (i != package_index)
 414                                 CPU_IRQ(i) += delta;
 415                         /*
 416                          * We have sibling A and sibling B in the package
 417                          *
 418                          * cpu_irq[A] = load for cpu A + load for cpu B
 419                          * cpu_irq[B] = load for cpu B
 420                          */
 421                         CPU_IRQ(package_index) += delta;
 422                 }
 423         }
 424         /* Find the least loaded processor package */
 425         for_each_online_cpu(i) {
 426                 if (i != CPU_TO_PACKAGEINDEX(i))
 427                         continue;
 428                 if (min_cpu_irq > CPU_IRQ(i)) {
 429                         min_cpu_irq = CPU_IRQ(i);
 430                         min_loaded = i;
 431                 }
 432         }
 433         max_cpu_irq = ULONG_MAX;
 434
 435 tryanothercpu:
 436         /* Look for heaviest loaded processor.
 437          * We may come back to get the next heaviest loaded processor.
 438          * Skip processors with trivial loads.
 439          */
 440         tmp_cpu_irq = 0;
 441         tmp_loaded = -1;
 442         for_each_online_cpu(i) {
 443                 if (i != CPU_TO_PACKAGEINDEX(i))
 444                         continue;
 445                 if (max_cpu_irq <= CPU_IRQ(i))
 446                         continue;
 447                 if (tmp_cpu_irq < CPU_IRQ(i)) {
 448                         tmp_cpu_irq = CPU_IRQ(i);
 449                         tmp_loaded = i;
 450                 }
 451         }
 452
 453         if (tmp_loaded == -1) {
 454          /* In the case of small number of heavy interrupt sources,
 455           * loading some of the cpus too much. We use Ingo's original
 456           * approach to rotate them around.
 457           */
 458                 if (!first_attempt && imbalance >= useful_load_threshold) {
 459                         rotate_irqs_among_cpus(useful_load_threshold);
 460                         return;
 461                 }
 462                 goto not_worth_the_effort;
 463         }
 464
 465         first_attempt = 0;              /* heaviest search */
 466         max_cpu_irq = tmp_cpu_irq;      /* load */
 467         max_loaded = tmp_loaded;        /* processor */
 468         imbalance = (max_cpu_irq - min_cpu_irq) / 2;
 469
 470         Dprintk("max_loaded cpu = %d\n", max_loaded);
 471         Dprintk("min_loaded cpu = %d\n", min_loaded);
 472         Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
 473         Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
 474         Dprintk("load imbalance = %lu\n", imbalance);
 475
 476         /* if imbalance is less than approx 10% of max load, then
 477          * observe diminishing returns action. - quit
 478          */
 479         if (imbalance < (max_cpu_irq >> 3)) {
 480                 Dprintk("Imbalance too trivial\n");
 481                 goto not_worth_the_effort;
 482         }
 483
 484 tryanotherirq:
 485         /* if we select an IRQ to move that can't go where we want, then
 486          * see if there is another one to try.
 487          */
 488         move_this_load = 0;
 489         selected_irq = -1;
 490         for (j = 0; j < NR_IRQS; j++) {
 491                 /* Is this an active IRQ? */
 492                 if (!irq_desc[j].action)
 493                         continue;
 494                 if (imbalance <= IRQ_DELTA(max_loaded,j))
 495                         continue;
 496                 /* Try to find the IRQ that is closest to the imbalance
 497                  * without going over.
 498                  */
 499                 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
 500                         move_this_load = IRQ_DELTA(max_loaded,j);
 501                         selected_irq = j;
 502                 }
 503         }
 504         if (selected_irq == -1) {
 505                 goto tryanothercpu;
 506         }
 507
 508         imbalance = move_this_load;
 509
 510         /* For physical_balance case, we accumlated both load
 511          * values in the one of the siblings cpu_irq[],
 512          * to use the same code for physical and logical processors
 513          * as much as possible.
 514          *
 515          * NOTE: the cpu_irq[] array holds the sum of the load for
 516          * sibling A and sibling B in the slot for the lowest numbered
 517          * sibling (A), _AND_ the load for sibling B in the slot for
 518          * the higher numbered sibling.
 519          *
 520          * We seek the least loaded sibling by making the comparison
 521          * (A+B)/2 vs B
 522          */
 523         load = CPU_IRQ(min_loaded) >> 1;
 524         for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
 525                 if (load > CPU_IRQ(j)) {
 526                         /* This won't change cpu_sibling_map[min_loaded] */
 527                         load = CPU_IRQ(j);
 528                         min_loaded = j;
 529                 }
 530         }
 531
 532         cpus_and(allowed_mask, cpu_online_map, irq_affinity[selected_irq]);
 533         target_cpu_mask = cpumask_of_cpu(min_loaded);
 534         cpus_and(tmp, target_cpu_mask, allowed_mask);
 535
 536         if (!cpus_empty(tmp)) {
 537
 538                 Dprintk("irq = %d moved to cpu = %d\n",
 539                                 selected_irq, min_loaded);
 540                 /* mark for change destination */
 541                 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
 542
 543                 /* Since we made a change, come back sooner to
 544                  * check for more variation.
 545                  */
 546                 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 547                         balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 548                 return;
 549         }
 550         goto tryanotherirq;
 551
 552 not_worth_the_effort:
 553         /*
 554          * if we did not find an IRQ to move, then adjust the time interval
 555          * upward
 556          */
 557         balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
 558                 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
 559         Dprintk("IRQ worth rotating not found\n");
 560         return;
 561 }
 562
 563 static int balanced_irq(void *unused)
 564 {
 565         int i;
 566         unsigned long prev_balance_time = jiffies;
 567         long time_remaining = balanced_irq_interval;
 568
 569         daemonize("kirqd");
 570
 571         /* push everything to CPU 0 to give us a starting point.  */
 572         for (i = 0 ; i < NR_IRQS ; i++) {
 573                 pending_irq_cpumask[i] = cpumask_of_cpu(0);
 574                 set_pending_irq(i, cpumask_of_cpu(0));
 575         }
 576
 577         for ( ; ; ) {
 578                 time_remaining = schedule_timeout_interruptible(time_remaining);
 579                 try_to_freeze();
 580                 if (time_after(jiffies,
 581                                 prev_balance_time+balanced_irq_interval)) {
 582                         preempt_disable();
 583                         do_irq_balance();
 584                         prev_balance_time = jiffies;
 585                         time_remaining = balanced_irq_interval;
 586                         preempt_enable();
 587                 }
 588         }
 589         return 0;
 590 }
 591
 592 static int __init balanced_irq_init(void)
 593 {
 594         int i;
 595         struct cpuinfo_x86 *c;
 596         cpumask_t tmp;
 597
 598         cpus_shift_right(tmp, cpu_online_map, 2);
 599         c = &boot_cpu_data;
 600         /* When not overwritten by the command line ask subarchitecture. */
 601         if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
 602                 irqbalance_disabled = NO_BALANCE_IRQ;
 603         if (irqbalance_disabled)
 604                 return 0;
 605
 606          /* disable irqbalance completely if there is only one processor online */
 607         if (num_online_cpus() < 2) {
 608                 irqbalance_disabled = 1;
 609                 return 0;
 610         }
 611         /*
 612          * Enable physical balance only if more than 1 physical processor
 613          * is present
 614          */
 615         if (smp_num_siblings > 1 && !cpus_empty(tmp))
 616                 physical_balance = 1;
 617
 618         for_each_online_cpu(i) {
 619                 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 620                 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 621                 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
 622                         printk(KERN_ERR "balanced_irq_init: out of memory");
 623                         goto failed;
 624                 }
 625                 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
 626                 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
 627         }
 628
 629         printk(KERN_INFO "Starting balanced_irq\n");
 630         if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0)
 631                 return 0;
 632         else
 633                 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
 634 failed:
 635         for_each_possible_cpu(i) {
 636                 kfree(irq_cpu_data[i].irq_delta);
 637                 irq_cpu_data[i].irq_delta = NULL;
 638                 kfree(irq_cpu_data[i].last_irq);
 639                 irq_cpu_data[i].last_irq = NULL;
 640         }
 641         return 0;
 642 }
 643
 644 int __init irqbalance_disable(char *str)
 645 {
 646         irqbalance_disabled = 1;
 647         return 1;
 648 }
 649
 650 __setup("noirqbalance", irqbalance_disable);
 651
 652 late_initcall(balanced_irq_init);
 653 #endif /* CONFIG_IRQBALANCE */
 654 #endif /* CONFIG_SMP */
 655
 656 #ifndef CONFIG_SMP
 657 void fastcall send_IPI_self(int vector)
 658 {
 659         unsigned int cfg;
 660
 661         /*
 662          * Wait for idle.
 663          */
 664         apic_wait_icr_idle();
 665         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
 666         /*
 667          * Send the IPI. The write to APIC_ICR fires this off.
 668          */
 669         apic_write_around(APIC_ICR, cfg);
 670 }
 671 #endif /* !CONFIG_SMP */
 672
 673
 674 /*
 675  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 676  * specific CPU-side IRQs.
 677  */
 678
 679 #define MAX_PIRQS 8
 680 static int pirq_entries [MAX_PIRQS];
 681 static int pirqs_enabled;
 682 int skip_ioapic_setup;
 683
 684 static int __init ioapic_setup(char *str)
 685 {
 686         skip_ioapic_setup = 1;
 687         return 1;
 688 }
 689
 690 __setup("noapic", ioapic_setup);
 691
 692 static int __init ioapic_pirq_setup(char *str)
 693 {
 694         int i, max;
 695         int ints[MAX_PIRQS+1];
 696
 697         get_options(str, ARRAY_SIZE(ints), ints);
 698
 699         for (i = 0; i < MAX_PIRQS; i++)
 700                 pirq_entries[i] = -1;
 701
 702         pirqs_enabled = 1;
 703         apic_printk(APIC_VERBOSE, KERN_INFO
 704                         "PIRQ redirection, working around broken MP-BIOS.\n");
 705         max = MAX_PIRQS;
 706         if (ints[0] < MAX_PIRQS)
 707                 max = ints[0];
 708
 709         for (i = 0; i < max; i++) {
 710                 apic_printk(APIC_VERBOSE, KERN_DEBUG
 711                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 712                 /*
 713                  * PIRQs are mapped upside down, usually.
 714                  */
 715                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 716         }
 717         return 1;
 718 }
 719
 720 __setup("pirq=", ioapic_pirq_setup);
 721
 722 /*
 723  * Find the IRQ entry number of a certain pin.
 724  */
 725 static int find_irq_entry(int apic, int pin, int type)
 726 {
 727         int i;
 728
 729         for (i = 0; i < mp_irq_entries; i++)
 730                 if (mp_irqs[i].mpc_irqtype == type &&
 731                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 732                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 733                     mp_irqs[i].mpc_dstirq == pin)
 734                         return i;
 735
 736         return -1;
 737 }
 738
 739 /*
 740  * Find the pin to which IRQ[irq] (ISA) is connected
 741  */
 742 static int __init find_isa_irq_pin(int irq, int type)
 743 {
 744         int i;
 745
 746         for (i = 0; i < mp_irq_entries; i++) {
 747                 int lbus = mp_irqs[i].mpc_srcbus;
 748
 749                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 750                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 751                      mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
 752                      mp_bus_id_to_type[lbus] == MP_BUS_NEC98
 753                     ) &&
 754                     (mp_irqs[i].mpc_irqtype == type) &&
 755                     (mp_irqs[i].mpc_srcbusirq == irq))
 756
 757                         return mp_irqs[i].mpc_dstirq;
 758         }
 759         return -1;
 760 }
 761
 762 static int __init find_isa_irq_apic(int irq, int type)
 763 {
 764         int i;
 765
 766         for (i = 0; i < mp_irq_entries; i++) {
 767                 int lbus = mp_irqs[i].mpc_srcbus;
 768
 769                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 770                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 771                      mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
 772                      mp_bus_id_to_type[lbus] == MP_BUS_NEC98
 773                     ) &&
 774                     (mp_irqs[i].mpc_irqtype == type) &&
 775                     (mp_irqs[i].mpc_srcbusirq == irq))
 776                         break;
 777         }
 778         if (i < mp_irq_entries) {
 779                 int apic;
 780                 for(apic = 0; apic < nr_ioapics; apic++) {
 781                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
 782                                 return apic;
 783                 }
 784         }
 785
 786         return -1;
 787 }
 788
 789 /*
 790  * Find a specific PCI IRQ entry.
 791  * Not an __init, possibly needed by modules
 792  */
 793 static int pin_2_irq(int idx, int apic, int pin);
 794
 795 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 796 {
 797         int apic, i, best_guess = -1;
 798
 799         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
 800                 "slot:%d, pin:%d.\n", bus, slot, pin);
 801         if (mp_bus_id_to_pci_bus[bus] == -1) {
 802                 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 803                 return -1;
 804         }
 805         for (i = 0; i < mp_irq_entries; i++) {
 806                 int lbus = mp_irqs[i].mpc_srcbus;
 807
 808                 for (apic = 0; apic < nr_ioapics; apic++)
 809                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 810                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 811                                 break;
 812
 813                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
 814                     !mp_irqs[i].mpc_irqtype &&
 815                     (bus == lbus) &&
 816                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 817                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 818
 819                         if (!(apic || IO_APIC_IRQ(irq)))
 820                                 continue;
 821
 822                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 823                                 return irq;
 824                         /*
 825                          * Use the first all-but-pin matching entry as a
 826                          * best-guess fuzzy result for broken mptables.
 827                          */
 828                         if (best_guess < 0)
 829                                 best_guess = irq;
 830                 }
 831         }
 832         return best_guess;
 833 }
 834 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
 835
 836 /*
 837  * This function currently is only a helper for the i386 smp boot process where
 838  * we need to reprogram the ioredtbls to cater for the cpus which have come online
 839  * so mask in all cases should simply be TARGET_CPUS
 840  */
 841 #ifdef CONFIG_SMP
 842 void __init setup_ioapic_dest(void)
 843 {
 844         int pin, ioapic, irq, irq_entry;
 845
 846         if (skip_ioapic_setup == 1)
 847                 return;
 848
 849         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
 850                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
 851                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
 852                         if (irq_entry == -1)
 853                                 continue;
 854                         irq = pin_2_irq(irq_entry, ioapic, pin);
 855                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
 856                 }
 857
 858         }
 859 }
 860 #endif
 861
 862 /*
 863  * EISA Edge/Level control register, ELCR
 864  */
 865 static int EISA_ELCR(unsigned int irq)
 866 {
 867         if (irq < 16) {
 868                 unsigned int port = 0x4d0 + (irq >> 3);
 869                 return (inb(port) >> (irq & 7)) & 1;
 870         }
 871         apic_printk(APIC_VERBOSE, KERN_INFO
 872                         "Broken MPtable reports ISA irq %d\n", irq);
 873         return 0;
 874 }
 875
 876 /* EISA interrupts are always polarity zero and can be edge or level
 877  * trigger depending on the ELCR value.  If an interrupt is listed as
 878  * EISA conforming in the MP table, that means its trigger type must
 879  * be read in from the ELCR */
 880
 881 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
 882 #define default_EISA_polarity(idx)      (0)
 883
 884 /* ISA interrupts are always polarity zero edge triggered,
 885  * when listed as conforming in the MP table. */
 886
 887 #define default_ISA_trigger(idx)        (0)
 888 #define default_ISA_polarity(idx)       (0)
 889
 890 /* PCI interrupts are always polarity one level triggered,
 891  * when listed as conforming in the MP table. */
 892
 893 #define default_PCI_trigger(idx)        (1)
 894 #define default_PCI_polarity(idx)       (1)
 895
 896 /* MCA interrupts are always polarity zero level triggered,
 897  * when listed as conforming in the MP table. */
 898
 899 #define default_MCA_trigger(idx)        (1)
 900 #define default_MCA_polarity(idx)       (0)
 901
 902 /* NEC98 interrupts are always polarity zero edge triggered,
 903  * when listed as conforming in the MP table. */
 904
 905 #define default_NEC98_trigger(idx)     (0)
 906 #define default_NEC98_polarity(idx)    (0)
 907
 908 static int __init MPBIOS_polarity(int idx)
 909 {
 910         int bus = mp_irqs[idx].mpc_srcbus;
 911         int polarity;
 912
 913         /*
 914          * Determine IRQ line polarity (high active or low active):
 915          */
 916         switch (mp_irqs[idx].mpc_irqflag & 3)
 917         {
 918                 case 0: /* conforms, ie. bus-type dependent polarity */
 919                 {
 920                         switch (mp_bus_id_to_type[bus])
 921                         {
 922                                 case MP_BUS_ISA: /* ISA pin */
 923                                 {
 924                                         polarity = default_ISA_polarity(idx);
 925                                         break;
 926                                 }
 927                                 case MP_BUS_EISA: /* EISA pin */
 928                                 {
 929                                         polarity = default_EISA_polarity(idx);
 930                                         break;
 931                                 }
 932                                 case MP_BUS_PCI: /* PCI pin */
 933                                 {
 934                                         polarity = default_PCI_polarity(idx);
 935                                         break;
 936                                 }
 937                                 case MP_BUS_MCA: /* MCA pin */
 938                                 {
 939                                         polarity = default_MCA_polarity(idx);
 940                                         break;
 941                                 }
 942                                 case MP_BUS_NEC98: /* NEC 98 pin */
 943                                 {
 944                                         polarity = default_NEC98_polarity(idx);
 945                                         break;
 946                                 }
 947                                 default:
 948                                 {
 949                                         printk(KERN_WARNING "broken BIOS!!\n");
 950                                         polarity = 1;
 951                                         break;
 952                                 }
 953                         }
 954                         break;
 955                 }
 956                 case 1: /* high active */
 957                 {
 958                         polarity = 0;
 959                         break;
 960                 }
 961                 case 2: /* reserved */
 962                 {
 963                         printk(KERN_WARNING "broken BIOS!!\n");
 964                         polarity = 1;
 965                         break;
 966                 }
 967                 case 3: /* low active */
 968                 {
 969                         polarity = 1;
 970                         break;
 971                 }
 972                 default: /* invalid */
 973                 {
 974                         printk(KERN_WARNING "broken BIOS!!\n");
 975                         polarity = 1;
 976                         break;
 977                 }
 978         }
 979         return polarity;
 980 }
 981
 982 static int MPBIOS_trigger(int idx)
 983 {
 984         int bus = mp_irqs[idx].mpc_srcbus;
 985         int trigger;
 986
 987         /*
 988          * Determine IRQ trigger mode (edge or level sensitive):
 989          */
 990         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
 991         {
 992                 case 0: /* conforms, ie. bus-type dependent */
 993                 {
 994                         switch (mp_bus_id_to_type[bus])
 995                         {
 996                                 case MP_BUS_ISA: /* ISA pin */
 997                                 {
 998                                         trigger = default_ISA_trigger(idx);
 999                                         break;
1000                                 }
1001                                 case MP_BUS_EISA: /* EISA pin */
1002                                 {
1003                                         trigger = default_EISA_trigger(idx);
1004                                         break;
1005                                 }
1006                                 case MP_BUS_PCI: /* PCI pin */
1007                                 {
1008                                         trigger = default_PCI_trigger(idx);
1009                                         break;
1010                                 }
1011                                 case MP_BUS_MCA: /* MCA pin */
1012                                 {
1013                                         trigger = default_MCA_trigger(idx);
1014                                         break;
1015                                 }
1016                                 case MP_BUS_NEC98: /* NEC 98 pin */
1017                                 {
1018                                         trigger = default_NEC98_trigger(idx);
1019                                         break;
1020                                 }
1021                                 default:
1022                                 {
1023                                         printk(KERN_WARNING "broken BIOS!!\n");
1024                                         trigger = 1;
1025                                         break;
1026                                 }
1027                         }
1028                         break;
1029                 }
1030                 case 1: /* edge */
1031                 {
1032                         trigger = 0;
1033                         break;
1034                 }
1035                 case 2: /* reserved */
1036                 {
1037                         printk(KERN_WARNING "broken BIOS!!\n");
1038                         trigger = 1;
1039                         break;
1040                 }
1041                 case 3: /* level */
1042                 {
1043                         trigger = 1;
1044                         break;
1045                 }
1046                 default: /* invalid */
1047                 {
1048                         printk(KERN_WARNING "broken BIOS!!\n");
1049                         trigger = 0;
1050                         break;
1051                 }
1052         }
1053         return trigger;
1054 }
1055
1056 static inline int irq_polarity(int idx)
1057 {
1058         return MPBIOS_polarity(idx);
1059 }
1060
1061 static inline int irq_trigger(int idx)
1062 {
1063         return MPBIOS_trigger(idx);
1064 }
1065
1066 static int pin_2_irq(int idx, int apic, int pin)
1067 {
1068         int irq, i;
1069         int bus = mp_irqs[idx].mpc_srcbus;
1070
1071         /*
1072          * Debugging check, we are in big trouble if this message pops up!
1073          */
1074         if (mp_irqs[idx].mpc_dstirq != pin)
1075                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1076
1077         switch (mp_bus_id_to_type[bus])
1078         {
1079                 case MP_BUS_ISA: /* ISA pin */
1080                 case MP_BUS_EISA:
1081                 case MP_BUS_MCA:
1082                 case MP_BUS_NEC98:
1083                 {
1084                         irq = mp_irqs[idx].mpc_srcbusirq;
1085                         break;
1086                 }
1087                 case MP_BUS_PCI: /* PCI pin */
1088                 {
1089                         /*
1090                          * PCI IRQs are mapped in order
1091                          */
1092                         i = irq = 0;
1093                         while (i < apic)
1094                                 irq += nr_ioapic_registers[i++];
1095                         irq += pin;
1096
1097                         /*
1098                          * For MPS mode, so far only needed by ES7000 platform
1099                          */
1100                         if (ioapic_renumber_irq)
1101                                 irq = ioapic_renumber_irq(apic, irq);
1102
1103                         break;
1104                 }
1105                 default:
1106                 {
1107                         printk(KERN_ERR "unknown bus type %d.\n",bus);
1108                         irq = 0;
1109                         break;
1110                 }
1111         }
1112
1113         /*
1114          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1115          */
1116         if ((pin >= 16) && (pin <= 23)) {
1117                 if (pirq_entries[pin-16] != -1) {
1118                         if (!pirq_entries[pin-16]) {
1119                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1120                                                 "disabling PIRQ%d\n", pin-16);
1121                         } else {
1122                                 irq = pirq_entries[pin-16];
1123                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1124                                                 "using PIRQ%d -> IRQ %d\n",
1125                                                 pin-16, irq);
1126                         }
1127                 }
1128         }
1129         return irq;
1130 }
1131
1132 static inline int IO_APIC_irq_trigger(int irq)
1133 {
1134         int apic, idx, pin;
1135
1136         for (apic = 0; apic < nr_ioapics; apic++) {
1137                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1138                         idx = find_irq_entry(apic,pin,mp_INT);
1139                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1140                                 return irq_trigger(idx);
1141                 }
1142         }
1143         /*
1144          * nonexistent IRQs are edge default
1145          */
1146         return 0;
1147 }
1148
1149 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1150 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1151
1152 int assign_irq_vector(int irq)
1153 {
1154         static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
1155
1156         BUG_ON(irq >= NR_IRQ_VECTORS);
1157         if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0)
1158                 return IO_APIC_VECTOR(irq);
1159 next:
1160         current_vector += 8;
1161         if (current_vector == SYSCALL_VECTOR)
1162                 goto next;
1163
1164         if (current_vector >= FIRST_SYSTEM_VECTOR) {
1165                 offset++;
1166                 if (!(offset%8))
1167                         return -ENOSPC;
1168                 current_vector = FIRST_DEVICE_VECTOR + offset;
1169         }
1170
1171         vector_irq[current_vector] = irq;
1172         if (irq != AUTO_ASSIGN)
1173                 IO_APIC_VECTOR(irq) = current_vector;
1174
1175         return current_vector;
1176 }
1177
1178 static struct hw_interrupt_type ioapic_level_type;
1179 static struct hw_interrupt_type ioapic_edge_type;
1180
1181 #define IOAPIC_AUTO     -1
1182 #define IOAPIC_EDGE     0
1183 #define IOAPIC_LEVEL    1
1184
1185 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1186 {
1187         if (use_pci_vector() && !platform_legacy_irq(irq)) {
1188                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1189                                 trigger == IOAPIC_LEVEL)
1190                         irq_desc[vector].handler = &ioapic_level_type;
1191                 else
1192                         irq_desc[vector].handler = &ioapic_edge_type;
1193                 set_intr_gate(vector, interrupt[vector]);
1194         } else  {
1195                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1196                                 trigger == IOAPIC_LEVEL)
1197                         irq_desc[irq].handler = &ioapic_level_type;
1198                 else
1199                         irq_desc[irq].handler = &ioapic_edge_type;
1200                 set_intr_gate(vector, interrupt[irq]);
1201         }
1202 }
1203
1204 static void __init setup_IO_APIC_irqs(void)
1205 {
1206         struct IO_APIC_route_entry entry;
1207         int apic, pin, idx, irq, first_notcon = 1, vector;
1208         unsigned long flags;
1209
1210         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1211
1212         for (apic = 0; apic < nr_ioapics; apic++) {
1213         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1214
1215                 /*
1216                  * add it to the IO-APIC irq-routing table:
1217                  */
1218                 memset(&entry,0,sizeof(entry));
1219
1220                 entry.delivery_mode = INT_DELIVERY_MODE;
1221                 entry.dest_mode = INT_DEST_MODE;
1222                 entry.mask = 0;                         /* enable IRQ */
1223                 entry.dest.logical.logical_dest =
1224                                         cpu_mask_to_apicid(TARGET_CPUS);
1225
1226                 idx = find_irq_entry(apic,pin,mp_INT);
1227                 if (idx == -1) {
1228                         if (first_notcon) {
1229                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1230                                                 " IO-APIC (apicid-pin) %d-%d",
1231                                                 mp_ioapics[apic].mpc_apicid,
1232                                                 pin);
1233                                 first_notcon = 0;
1234                         } else
1235                                 apic_printk(APIC_VERBOSE, ", %d-%d",
1236                                         mp_ioapics[apic].mpc_apicid, pin);
1237                         continue;
1238                 }
1239
1240                 entry.trigger = irq_trigger(idx);
1241                 entry.polarity = irq_polarity(idx);
1242
1243                 if (irq_trigger(idx)) {
1244                         entry.trigger = 1;
1245                         entry.mask = 1;
1246                 }
1247
1248                 irq = pin_2_irq(idx, apic, pin);
1249                 /*
1250                  * skip adding the timer int on secondary nodes, which causes
1251                  * a small but painful rift in the time-space continuum
1252                  */
1253                 if (multi_timer_check(apic, irq))
1254                         continue;
1255                 else
1256                         add_pin_to_irq(irq, apic, pin);
1257
1258                 if (!apic && !IO_APIC_IRQ(irq))
1259                         continue;
1260
1261                 if (IO_APIC_IRQ(irq)) {
1262                         vector = assign_irq_vector(irq);
1263                         entry.vector = vector;
1264                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1265
1266                         if (!apic && (irq < 16))
1267                                 disable_8259A_irq(irq);
1268                 }
1269                 spin_lock_irqsave(&ioapic_lock, flags);
1270                 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1271                 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1272                 set_native_irq_info(irq, TARGET_CPUS);
1273                 spin_unlock_irqrestore(&ioapic_lock, flags);
1274         }
1275         }
1276
1277         if (!first_notcon)
1278                 apic_printk(APIC_VERBOSE, " not connected.\n");
1279 }
1280
1281 /*
1282  * Set up the 8259A-master output pin:
1283  */
1284 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1285 {
1286         struct IO_APIC_route_entry entry;
1287         unsigned long flags;
1288
1289         memset(&entry,0,sizeof(entry));
1290
1291         disable_8259A_irq(0);
1292
1293         /* mask LVT0 */
1294         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1295
1296         /*
1297          * We use logical delivery to get the timer IRQ
1298          * to the first CPU.
1299          */
1300         entry.dest_mode = INT_DEST_MODE;
1301         entry.mask = 0;                                 /* unmask IRQ now */
1302         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1303         entry.delivery_mode = INT_DELIVERY_MODE;
1304         entry.polarity = 0;
1305         entry.trigger = 0;
1306         entry.vector = vector;
1307
1308         /*
1309          * The timer IRQ doesn't have to know that behind the
1310          * scene we have a 8259A-master in AEOI mode ...
1311          */
1312         irq_desc[0].handler = &ioapic_edge_type;
1313
1314         /*
1315          * Add it to the IO-APIC irq-routing table:
1316          */
1317         spin_lock_irqsave(&ioapic_lock, flags);
1318         io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1319         io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1320         spin_unlock_irqrestore(&ioapic_lock, flags);
1321
1322         enable_8259A_irq(0);
1323 }
1324
1325 static inline void UNEXPECTED_IO_APIC(void)
1326 {
1327 }
1328
1329 void __init print_IO_APIC(void)
1330 {
1331         int apic, i;
1332         union IO_APIC_reg_00 reg_00;
1333         union IO_APIC_reg_01 reg_01;
1334         union IO_APIC_reg_02 reg_02;
1335         union IO_APIC_reg_03 reg_03;
1336         unsigned long flags;
1337
1338         if (apic_verbosity == APIC_QUIET)
1339                 return;
1340
1341         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1342         for (i = 0; i < nr_ioapics; i++)
1343                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1344                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1345
1346         /*
1347          * We are a bit conservative about what we expect.  We have to
1348          * know about every hardware change ASAP.
1349          */
1350         printk(KERN_INFO "testing the IO APIC.......................\n");
1351
1352         for (apic = 0; apic < nr_ioapics; apic++) {
1353
1354         spin_lock_irqsave(&ioapic_lock, flags);
1355         reg_00.raw = io_apic_read(apic, 0);
1356         reg_01.raw = io_apic_read(apic, 1);
1357         if (reg_01.bits.version >= 0x10)
1358                 reg_02.raw = io_apic_read(apic, 2);
1359         if (reg_01.bits.version >= 0x20)
1360                 reg_03.raw = io_apic_read(apic, 3);
1361         spin_unlock_irqrestore(&ioapic_lock, flags);
1362
1363         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1364         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1365         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1366         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1367         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1368         if (reg_00.bits.ID >= get_physical_broadcast())
1369                 UNEXPECTED_IO_APIC();
1370         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1371                 UNEXPECTED_IO_APIC();
1372
1373         printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1374         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1375         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1376                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1377                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1378                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1379                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1380                 (reg_01.bits.entries != 0x2E) &&
1381                 (reg_01.bits.entries != 0x3F)
1382         )
1383                 UNEXPECTED_IO_APIC();
1384
1385         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1386         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1387         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1388                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1389                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1390                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1391                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
1392         )
1393                 UNEXPECTED_IO_APIC();
1394         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1395                 UNEXPECTED_IO_APIC();
1396
1397         /*
1398          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1399          * but the value of reg_02 is read as the previous read register
1400          * value, so ignore it if reg_02 == reg_01.
1401          */
1402         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1403                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1404                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1405                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1406                         UNEXPECTED_IO_APIC();
1407         }
1408
1409         /*
1410          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1411          * or reg_03, but the value of reg_0[23] is read as the previous read
1412          * register value, so ignore it if reg_03 == reg_0[12].
1413          */
1414         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1415             reg_03.raw != reg_01.raw) {
1416                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1417                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1418                 if (reg_03.bits.__reserved_1)
1419                         UNEXPECTED_IO_APIC();
1420         }
1421
1422         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1423
1424         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1425                           " Stat Dest Deli Vect:   \n");
1426
1427         for (i = 0; i <= reg_01.bits.entries; i++) {
1428                 struct IO_APIC_route_entry entry;
1429
1430                 spin_lock_irqsave(&ioapic_lock, flags);
1431                 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
1432                 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
1433                 spin_unlock_irqrestore(&ioapic_lock, flags);
1434
1435                 printk(KERN_DEBUG " %02x %03X %02X  ",
1436                         i,
1437                         entry.dest.logical.logical_dest,
1438                         entry.dest.physical.physical_dest
1439                 );
1440
1441                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1442                         entry.mask,
1443                         entry.trigger,
1444                         entry.irr,
1445                         entry.polarity,
1446                         entry.delivery_status,
1447                         entry.dest_mode,
1448                         entry.delivery_mode,
1449                         entry.vector
1450                 );
1451         }
1452         }
1453         if (use_pci_vector())
1454                 printk(KERN_INFO "Using vector-based indexing\n");
1455         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1456         for (i = 0; i < NR_IRQS; i++) {
1457                 struct irq_pin_list *entry = irq_2_pin + i;
1458                 if (entry->pin < 0)
1459                         continue;
1460                 if (use_pci_vector() && !platform_legacy_irq(i))
1461                         printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1462                 else
1463                         printk(KERN_DEBUG "IRQ%d ", i);
1464                 for (;;) {
1465                         printk("-> %d:%d", entry->apic, entry->pin);
1466                         if (!entry->next)
1467                                 break;
1468                         entry = irq_2_pin + entry->next;
1469                 }
1470                 printk("\n");
1471         }
1472
1473         printk(KERN_INFO ".................................... done.\n");
1474
1475         return;
1476 }
1477
1478 #if 0
1479
1480 static void print_APIC_bitfield (int base)
1481 {
1482         unsigned int v;
1483         int i, j;
1484
1485         if (apic_verbosity == APIC_QUIET)
1486                 return;
1487
1488         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1489         for (i = 0; i < 8; i++) {
1490                 v = apic_read(base + i*0x10);
1491                 for (j = 0; j < 32; j++) {
1492                         if (v & (1<<j))
1493                                 printk("1");
1494                         else
1495                                 printk("0");
1496                 }
1497                 printk("\n");
1498         }
1499 }
1500
1501 void /*__init*/ print_local_APIC(void * dummy)
1502 {
1503         unsigned int v, ver, maxlvt;
1504
1505         if (apic_verbosity == APIC_QUIET)
1506                 return;
1507
1508         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1509                 smp_processor_id(), hard_smp_processor_id());
1510         v = apic_read(APIC_ID);
1511         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1512         v = apic_read(APIC_LVR);
1513         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1514         ver = GET_APIC_VERSION(v);
1515         maxlvt = get_maxlvt();
1516
1517         v = apic_read(APIC_TASKPRI);
1518         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1519
1520         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1521                 v = apic_read(APIC_ARBPRI);
1522                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1523                         v & APIC_ARBPRI_MASK);
1524                 v = apic_read(APIC_PROCPRI);
1525                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1526         }
1527
1528         v = apic_read(APIC_EOI);
1529         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1530         v = apic_read(APIC_RRR);
1531         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1532         v = apic_read(APIC_LDR);
1533         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1534         v = apic_read(APIC_DFR);
1535         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1536         v = apic_read(APIC_SPIV);
1537         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1538
1539         printk(KERN_DEBUG "... APIC ISR field:\n");
1540         print_APIC_bitfield(APIC_ISR);
1541         printk(KERN_DEBUG "... APIC TMR field:\n");
1542         print_APIC_bitfield(APIC_TMR);
1543         printk(KERN_DEBUG "... APIC IRR field:\n");
1544         print_APIC_bitfield(APIC_IRR);
1545
1546         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1547                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1548                         apic_write(APIC_ESR, 0);
1549                 v = apic_read(APIC_ESR);
1550                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1551         }
1552
1553         v = apic_read(APIC_ICR);
1554         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1555         v = apic_read(APIC_ICR2);
1556         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1557
1558         v = apic_read(APIC_LVTT);
1559         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1560
1561         if (maxlvt > 3) {                       /* PC is LVT#4. */
1562                 v = apic_read(APIC_LVTPC);
1563                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1564         }
1565         v = apic_read(APIC_LVT0);
1566         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1567         v = apic_read(APIC_LVT1);
1568         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1569
1570         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1571                 v = apic_read(APIC_LVTERR);
1572                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1573         }
1574
1575         v = apic_read(APIC_TMICT);
1576         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1577         v = apic_read(APIC_TMCCT);
1578         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1579         v = apic_read(APIC_TDCR);
1580         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1581         printk("\n");
1582 }
1583
1584 void print_all_local_APICs (void)
1585 {
1586         on_each_cpu(print_local_APIC, NULL, 1, 1);
1587 }
1588
1589 void /*__init*/ print_PIC(void)
1590 {
1591         unsigned int v;
1592         unsigned long flags;
1593
1594         if (apic_verbosity == APIC_QUIET)
1595                 return;
1596
1597         printk(KERN_DEBUG "\nprinting PIC contents\n");
1598
1599         spin_lock_irqsave(&i8259A_lock, flags);
1600
1601         v = inb(0xa1) << 8 | inb(0x21);
1602         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1603
1604         v = inb(0xa0) << 8 | inb(0x20);
1605         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1606
1607         outb(0x0b,0xa0);
1608         outb(0x0b,0x20);
1609         v = inb(0xa0) << 8 | inb(0x20);
1610         outb(0x0a,0xa0);
1611         outb(0x0a,0x20);
1612
1613         spin_unlock_irqrestore(&i8259A_lock, flags);
1614
1615         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1616
1617         v = inb(0x4d1) << 8 | inb(0x4d0);
1618         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1619 }
1620
1621 #endif  /*  0  */
1622
1623 static void __init enable_IO_APIC(void)
1624 {
1625         union IO_APIC_reg_01 reg_01;
1626         int i8259_apic, i8259_pin;
1627         int i, apic;
1628         unsigned long flags;
1629
1630         for (i = 0; i < PIN_MAP_SIZE; i++) {
1631                 irq_2_pin[i].pin = -1;
1632                 irq_2_pin[i].next = 0;
1633         }
1634         if (!pirqs_enabled)
1635                 for (i = 0; i < MAX_PIRQS; i++)
1636                         pirq_entries[i] = -1;
1637
1638         /*
1639          * The number of IO-APIC IRQ registers (== #pins):
1640          */
1641         for (apic = 0; apic < nr_ioapics; apic++) {
1642                 spin_lock_irqsave(&ioapic_lock, flags);
1643                 reg_01.raw = io_apic_read(apic, 1);
1644                 spin_unlock_irqrestore(&ioapic_lock, flags);
1645                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1646         }
1647         for(apic = 0; apic < nr_ioapics; apic++) {
1648                 int pin;
1649                 /* See if any of the pins is in ExtINT mode */
1650                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1651                         struct IO_APIC_route_entry entry;
1652                         spin_lock_irqsave(&ioapic_lock, flags);
1653                         *(((int *)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1654                         *(((int *)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1655                         spin_unlock_irqrestore(&ioapic_lock, flags);
1656
1657
1658                         /* If the interrupt line is enabled and in ExtInt mode
1659                          * I have found the pin where the i8259 is connected.
1660                          */
1661                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1662                                 ioapic_i8259.apic = apic;
1663                                 ioapic_i8259.pin  = pin;
1664                                 goto found_i8259;
1665                         }
1666                 }
1667         }
1668  found_i8259:
1669         /* Look to see what if the MP table has reported the ExtINT */
1670         /* If we could not find the appropriate pin by looking at the ioapic
1671          * the i8259 probably is not connected the ioapic but give the
1672          * mptable a chance anyway.
1673          */
1674         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1675         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1676         /* Trust the MP table if nothing is setup in the hardware */
1677         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1678                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1679                 ioapic_i8259.pin  = i8259_pin;
1680                 ioapic_i8259.apic = i8259_apic;
1681         }
1682         /* Complain if the MP table and the hardware disagree */
1683         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1684                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1685         {
1686                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1687         }
1688
1689         /*
1690          * Do not trust the IO-APIC being empty at bootup
1691          */
1692         clear_IO_APIC();
1693 }
1694
1695 /*
1696  * Not an __init, needed by the reboot code
1697  */
1698 void disable_IO_APIC(void)
1699 {
1700         /*
1701          * Clear the IO-APIC before rebooting:
1702          */
1703         clear_IO_APIC();
1704
1705         /*
1706          * If the i8259 is routed through an IOAPIC
1707          * Put that IOAPIC in virtual wire mode
1708          * so legacy interrupts can be delivered.
1709          */
1710         if (ioapic_i8259.pin != -1) {
1711                 struct IO_APIC_route_entry entry;
1712                 unsigned long flags;
1713
1714                 memset(&entry, 0, sizeof(entry));
1715                 entry.mask            = 0; /* Enabled */
1716                 entry.trigger         = 0; /* Edge */
1717                 entry.irr             = 0;
1718                 entry.polarity        = 0; /* High */
1719                 entry.delivery_status = 0;
1720                 entry.dest_mode       = 0; /* Physical */
1721                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1722                 entry.vector          = 0;
1723                 entry.dest.physical.physical_dest =
1724                                         GET_APIC_ID(apic_read(APIC_ID));
1725
1726                 /*
1727                  * Add it to the IO-APIC irq-routing table:
1728                  */
1729                 spin_lock_irqsave(&ioapic_lock, flags);
1730                 io_apic_write(ioapic_i8259.apic, 0x11+2*ioapic_i8259.pin,
1731                         *(((int *)&entry)+1));
1732                 io_apic_write(ioapic_i8259.apic, 0x10+2*ioapic_i8259.pin,
1733                         *(((int *)&entry)+0));
1734                 spin_unlock_irqrestore(&ioapic_lock, flags);
1735         }
1736         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1737 }
1738
1739 /*
1740  * function to set the IO-APIC physical IDs based on the
1741  * values stored in the MPC table.
1742  *
1743  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1744  */
1745
1746 #ifndef CONFIG_X86_NUMAQ
1747 static void __init setup_ioapic_ids_from_mpc(void)
1748 {
1749         union IO_APIC_reg_00 reg_00;
1750         physid_mask_t phys_id_present_map;
1751         int apic;
1752         int i;
1753         unsigned char old_id;
1754         unsigned long flags;
1755
1756         /*
1757          * Don't check I/O APIC IDs for xAPIC systems.  They have
1758          * no meaning without the serial APIC bus.
1759          */
1760         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1761                 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1762                 return;
1763         /*
1764          * This is broken; anything with a real cpu count has to
1765          * circumvent this idiocy regardless.
1766          */
1767         phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1768
1769         /*
1770          * Set the IOAPIC ID to the value stored in the MPC table.
1771          */
1772         for (apic = 0; apic < nr_ioapics; apic++) {
1773
1774                 /* Read the register 0 value */
1775                 spin_lock_irqsave(&ioapic_lock, flags);
1776                 reg_00.raw = io_apic_read(apic, 0);
1777                 spin_unlock_irqrestore(&ioapic_lock, flags);
1778
1779                 old_id = mp_ioapics[apic].mpc_apicid;
1780
1781                 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1782                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1783                                 apic, mp_ioapics[apic].mpc_apicid);
1784                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1785                                 reg_00.bits.ID);
1786                         mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1787                 }
1788
1789                 /*
1790                  * Sanity check, is the ID really free? Every APIC in a
1791                  * system must have a unique ID or we get lots of nice
1792                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1793                  */
1794                 if (check_apicid_used(phys_id_present_map,
1795                                         mp_ioapics[apic].mpc_apicid)) {
1796                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1797                                 apic, mp_ioapics[apic].mpc_apicid);
1798                         for (i = 0; i < get_physical_broadcast(); i++)
1799                                 if (!physid_isset(i, phys_id_present_map))
1800                                         break;
1801                         if (i >= get_physical_broadcast())
1802                                 panic("Max APIC ID exceeded!\n");
1803                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1804                                 i);
1805                         physid_set(i, phys_id_present_map);
1806                         mp_ioapics[apic].mpc_apicid = i;
1807                 } else {
1808                         physid_mask_t tmp;
1809                         tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1810                         apic_printk(APIC_VERBOSE, "Setting %d in the "
1811                                         "phys_id_present_map\n",
1812                                         mp_ioapics[apic].mpc_apicid);
1813                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
1814                 }
1815
1816
1817                 /*
1818                  * We need to adjust the IRQ routing table
1819                  * if the ID changed.
1820                  */
1821                 if (old_id != mp_ioapics[apic].mpc_apicid)
1822                         for (i = 0; i < mp_irq_entries; i++)
1823                                 if (mp_irqs[i].mpc_dstapic == old_id)
1824                                         mp_irqs[i].mpc_dstapic
1825                                                 = mp_ioapics[apic].mpc_apicid;
1826
1827                 /*
1828                  * Read the right value from the MPC table and
1829                  * write it into the ID register.
1830                  */
1831                 apic_printk(APIC_VERBOSE, KERN_INFO
1832                         "...changing IO-APIC physical APIC ID to %d ...",
1833                         mp_ioapics[apic].mpc_apicid);
1834
1835                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1836                 spin_lock_irqsave(&ioapic_lock, flags);
1837                 io_apic_write(apic, 0, reg_00.raw);
1838                 spin_unlock_irqrestore(&ioapic_lock, flags);
1839
1840                 /*
1841                  * Sanity check
1842                  */
1843                 spin_lock_irqsave(&ioapic_lock, flags);
1844                 reg_00.raw = io_apic_read(apic, 0);
1845                 spin_unlock_irqrestore(&ioapic_lock, flags);
1846                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1847                         printk("could not set ID!\n");
1848                 else
1849                         apic_printk(APIC_VERBOSE, " ok.\n");
1850         }
1851 }
1852 #else
1853 static void __init setup_ioapic_ids_from_mpc(void) { }
1854 #endif
1855
1856 /*
1857  * There is a nasty bug in some older SMP boards, their mptable lies
1858  * about the timer IRQ. We do the following to work around the situation:
1859  *
1860  *      - timer IRQ defaults to IO-APIC IRQ
1861  *      - if this function detects that timer IRQs are defunct, then we fall
1862  *        back to ISA timer IRQs
1863  */
1864 static int __init timer_irq_works(void)
1865 {
1866         unsigned long t1 = jiffies;
1867
1868         local_irq_enable();
1869         /* Let ten ticks pass... */
1870         mdelay((10 * 1000) / HZ);
1871
1872         /*
1873          * Expect a few ticks at least, to be sure some possible
1874          * glue logic does not lock up after one or two first
1875          * ticks in a non-ExtINT mode.  Also the local APIC
1876          * might have cached one ExtINT interrupt.  Finally, at
1877          * least one tick may be lost due to delays.
1878          */
1879         if (jiffies - t1 > 4)
1880                 return 1;
1881
1882         return 0;
1883 }
1884
1885 /*
1886  * In the SMP+IOAPIC case it might happen that there are an unspecified
1887  * number of pending IRQ events unhandled. These cases are very rare,
1888  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1889  * better to do it this way as thus we do not have to be aware of
1890  * 'pending' interrupts in the IRQ path, except at this point.
1891  */
1892 /*
1893  * Edge triggered needs to resend any interrupt
1894  * that was delayed but this is now handled in the device
1895  * independent code.
1896  */
1897
1898 /*
1899  * Starting up a edge-triggered IO-APIC interrupt is
1900  * nasty - we need to make sure that we get the edge.
1901  * If it is already asserted for some reason, we need
1902  * return 1 to indicate that is was pending.
1903  *
1904  * This is not complete - we should be able to fake
1905  * an edge even if it isn't on the 8259A...
1906  */
1907 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1908 {
1909         int was_pending = 0;
1910         unsigned long flags;
1911
1912         spin_lock_irqsave(&ioapic_lock, flags);
1913         if (irq < 16) {
1914                 disable_8259A_irq(irq);
1915                 if (i8259A_irq_pending(irq))
1916                         was_pending = 1;
1917         }
1918         __unmask_IO_APIC_irq(irq);
1919         spin_unlock_irqrestore(&ioapic_lock, flags);
1920
1921         return was_pending;
1922 }
1923
1924 /*
1925  * Once we have recorded IRQ_PENDING already, we can mask the
1926  * interrupt for real. This prevents IRQ storms from unhandled
1927  * devices.
1928  */
1929 static void ack_edge_ioapic_irq(unsigned int irq)
1930 {
1931         move_irq(irq);
1932         if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1933                                         == (IRQ_PENDING | IRQ_DISABLED))
1934                 mask_IO_APIC_irq(irq);
1935         ack_APIC_irq();
1936 }
1937
1938 /*
1939  * Level triggered interrupts can just be masked,
1940  * and shutting down and starting up the interrupt
1941  * is the same as enabling and disabling them -- except
1942  * with a startup need to return a "was pending" value.
1943  *
1944  * Level triggered interrupts are special because we
1945  * do not touch any IO-APIC register while handling
1946  * them. We ack the APIC in the end-IRQ handler, not
1947  * in the start-IRQ-handler. Protection against reentrance
1948  * from the same interrupt is still provided, both by the
1949  * generic IRQ layer and by the fact that an unacked local
1950  * APIC does not accept IRQs.
1951  */
1952 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1953 {
1954         unmask_IO_APIC_irq(irq);
1955
1956         return 0; /* don't check for pending */
1957 }
1958
1959 static void end_level_ioapic_irq (unsigned int irq)
1960 {
1961         unsigned long v;
1962         int i;
1963
1964         move_irq(irq);
1965 /*
1966  * It appears there is an erratum which affects at least version 0x11
1967  * of I/O APIC (that's the 82093AA and cores integrated into various
1968  * chipsets).  Under certain conditions a level-triggered interrupt is
1969  * erroneously delivered as edge-triggered one but the respective IRR
1970  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1971  * message but it will never arrive and further interrupts are blocked
1972  * from the source.  The exact reason is so far unknown, but the
1973  * phenomenon was observed when two consecutive interrupt requests
1974  * from a given source get delivered to the same CPU and the source is
1975  * temporarily disabled in between.
1976  *
1977  * A workaround is to simulate an EOI message manually.  We achieve it
1978  * by setting the trigger mode to edge and then to level when the edge
1979  * trigger mode gets detected in the TMR of a local APIC for a
1980  * level-triggered interrupt.  We mask the source for the time of the
1981  * operation to prevent an edge-triggered interrupt escaping meanwhile.
1982  * The idea is from Manfred Spraul.  --macro
1983  */
1984         i = IO_APIC_VECTOR(irq);
1985
1986         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1987
1988         ack_APIC_irq();
1989
1990         if (!(v & (1 << (i & 0x1f)))) {
1991                 atomic_inc(&irq_mis_count);
1992                 spin_lock(&ioapic_lock);
1993                 __mask_and_edge_IO_APIC_irq(irq);
1994                 __unmask_and_level_IO_APIC_irq(irq);
1995                 spin_unlock(&ioapic_lock);
1996         }
1997 }
1998
1999 #ifdef CONFIG_PCI_MSI
2000 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
2001 {
2002         int irq = vector_to_irq(vector);
2003
2004         return startup_edge_ioapic_irq(irq);
2005 }
2006
2007 static void ack_edge_ioapic_vector(unsigned int vector)
2008 {
2009         int irq = vector_to_irq(vector);
2010
2011         move_native_irq(vector);
2012         ack_edge_ioapic_irq(irq);
2013 }
2014
2015 static unsigned int startup_level_ioapic_vector (unsigned int vector)
2016 {
2017         int irq = vector_to_irq(vector);
2018
2019         return startup_level_ioapic_irq (irq);
2020 }
2021
2022 static void end_level_ioapic_vector (unsigned int vector)
2023 {
2024         int irq = vector_to_irq(vector);
2025
2026         move_native_irq(vector);
2027         end_level_ioapic_irq(irq);
2028 }
2029
2030 static void mask_IO_APIC_vector (unsigned int vector)
2031 {
2032         int irq = vector_to_irq(vector);
2033
2034         mask_IO_APIC_irq(irq);
2035 }
2036
2037 static void unmask_IO_APIC_vector (unsigned int vector)
2038 {
2039         int irq = vector_to_irq(vector);
2040
2041         unmask_IO_APIC_irq(irq);
2042 }
2043
2044 #ifdef CONFIG_SMP
2045 static void set_ioapic_affinity_vector (unsigned int vector,
2046                                         cpumask_t cpu_mask)
2047 {
2048         int irq = vector_to_irq(vector);
2049
2050         set_native_irq_info(vector, cpu_mask);
2051         set_ioapic_affinity_irq(irq, cpu_mask);
2052 }
2053 #endif
2054 #endif
2055
2056 /*
2057  * Level and edge triggered IO-APIC interrupts need different handling,
2058  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2059  * handled with the level-triggered descriptor, but that one has slightly
2060  * more overhead. Level-triggered interrupts cannot be handled with the
2061  * edge-triggered handler, without risking IRQ storms and other ugly
2062  * races.
2063  */
2064 static struct hw_interrupt_type ioapic_edge_type __read_mostly = {
2065         .typename       = "IO-APIC-edge",
2066         .startup        = startup_edge_ioapic,
2067         .shutdown       = shutdown_edge_ioapic,
2068         .enable         = enable_edge_ioapic,
2069         .disable        = disable_edge_ioapic,
2070         .ack            = ack_edge_ioapic,
2071         .end            = end_edge_ioapic,
2072 #ifdef CONFIG_SMP
2073         .set_affinity   = set_ioapic_affinity,
2074 #endif
2075 };
2076
2077 static struct hw_interrupt_type ioapic_level_type __read_mostly = {
2078         .typename       = "IO-APIC-level",
2079         .startup        = startup_level_ioapic,
2080         .shutdown       = shutdown_level_ioapic,
2081         .enable         = enable_level_ioapic,
2082         .disable        = disable_level_ioapic,
2083         .ack            = mask_and_ack_level_ioapic,
2084         .end            = end_level_ioapic,
2085 #ifdef CONFIG_SMP
2086         .set_affinity   = set_ioapic_affinity,
2087 #endif
2088 };
2089
2090 static inline void init_IO_APIC_traps(void)
2091 {
2092         int irq;
2093
2094         /*
2095          * NOTE! The local APIC isn't very good at handling
2096          * multiple interrupts at the same interrupt level.
2097          * As the interrupt level is determined by taking the
2098          * vector number and shifting that right by 4, we
2099          * want to spread these out a bit so that they don't
2100          * all fall in the same interrupt level.
2101          *
2102          * Also, we've got to be careful not to trash gate
2103          * 0x80, because int 0x80 is hm, kind of importantish. ;)
2104          */
2105         for (irq = 0; irq < NR_IRQS ; irq++) {
2106                 int tmp = irq;
2107                 if (use_pci_vector()) {
2108                         if (!platform_legacy_irq(tmp))
2109                                 if ((tmp = vector_to_irq(tmp)) == -1)
2110                                         continue;
2111                 }
2112                 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
2113                         /*
2114                          * Hmm.. We don't have an entry for this,
2115                          * so default to an old-fashioned 8259
2116                          * interrupt if we can..
2117                          */
2118                         if (irq < 16)
2119                                 make_8259A_irq(irq);
2120                         else
2121                                 /* Strange. Oh, well.. */
2122                                 irq_desc[irq].handler = &no_irq_type;
2123                 }
2124         }
2125 }
2126
2127 static void enable_lapic_irq (unsigned int irq)
2128 {
2129         unsigned long v;
2130
2131         v = apic_read(APIC_LVT0);
2132         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2133 }
2134
2135 static void disable_lapic_irq (unsigned int irq)
2136 {
2137         unsigned long v;
2138
2139         v = apic_read(APIC_LVT0);
2140         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2141 }
2142
2143 static void ack_lapic_irq (unsigned int irq)
2144 {
2145         ack_APIC_irq();
2146 }
2147
2148 static void end_lapic_irq (unsigned int i) { /* nothing */ }
2149
2150 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
2151         .typename       = "local-APIC-edge",
2152         .startup        = NULL, /* startup_irq() not used for IRQ0 */
2153         .shutdown       = NULL, /* shutdown_irq() not used for IRQ0 */
2154         .enable         = enable_lapic_irq,
2155         .disable        = disable_lapic_irq,
2156         .ack            = ack_lapic_irq,
2157         .end            = end_lapic_irq
2158 };
2159
2160 static void setup_nmi (void)
2161 {
2162         /*
2163          * Dirty trick to enable the NMI watchdog ...
2164          * We put the 8259A master into AEOI mode and
2165          * unmask on all local APICs LVT0 as NMI.
2166          *
2167          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2168          * is from Maciej W. Rozycki - so we do not have to EOI from
2169          * the NMI handler or the timer interrupt.
2170          */
2171         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2172
2173         on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
2174
2175         apic_printk(APIC_VERBOSE, " done.\n");
2176 }
2177
2178 /*
2179  * This looks a bit hackish but it's about the only one way of sending
2180  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2181  * not support the ExtINT mode, unfortunately.  We need to send these
2182  * cycles as some i82489DX-based boards have glue logic that keeps the
2183  * 8259A interrupt line asserted until INTA.  --macro
2184  */
2185 static inline void unlock_ExtINT_logic(void)
2186 {
2187         int apic, pin, i;
2188         struct IO_APIC_route_entry entry0, entry1;
2189         unsigned char save_control, save_freq_select;
2190         unsigned long flags;
2191
2192         pin  = find_isa_irq_pin(8, mp_INT);
2193         apic = find_isa_irq_apic(8, mp_INT);
2194         if (pin == -1)
2195                 return;
2196
2197         spin_lock_irqsave(&ioapic_lock, flags);
2198         *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
2199         *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
2200         spin_unlock_irqrestore(&ioapic_lock, flags);
2201         clear_IO_APIC_pin(apic, pin);
2202
2203         memset(&entry1, 0, sizeof(entry1));
2204
2205         entry1.dest_mode = 0;                   /* physical delivery */
2206         entry1.mask = 0;                        /* unmask IRQ now */
2207         entry1.dest.physical.physical_dest = hard_smp_processor_id();
2208         entry1.delivery_mode = dest_ExtINT;
2209         entry1.polarity = entry0.polarity;
2210         entry1.trigger = 0;
2211         entry1.vector = 0;
2212
2213         spin_lock_irqsave(&ioapic_lock, flags);
2214         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
2215         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
2216         spin_unlock_irqrestore(&ioapic_lock, flags);
2217
2218         save_control = CMOS_READ(RTC_CONTROL);
2219         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2220         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2221                    RTC_FREQ_SELECT);
2222         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2223
2224         i = 100;
2225         while (i-- > 0) {
2226                 mdelay(10);
2227                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2228                         i -= 10;
2229         }
2230
2231         CMOS_WRITE(save_control, RTC_CONTROL);
2232         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2233         clear_IO_APIC_pin(apic, pin);
2234
2235         spin_lock_irqsave(&ioapic_lock, flags);
2236         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
2237         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
2238         spin_unlock_irqrestore(&ioapic_lock, flags);
2239 }
2240
2241 int timer_uses_ioapic_pin_0;
2242
2243 /*
2244  * This code may look a bit paranoid, but it's supposed to cooperate with
2245  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2246  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2247  * fanatically on his truly buggy board.
2248  */
2249 static inline void check_timer(void)
2250 {
2251         int apic1, pin1, apic2, pin2;
2252         int vector;
2253
2254         /*
2255          * get/set the timer IRQ vector:
2256          */
2257         disable_8259A_irq(0);
2258         vector = assign_irq_vector(0);
2259         set_intr_gate(vector, interrupt[0]);
2260
2261         /*
2262          * Subtle, code in do_timer_interrupt() expects an AEOI
2263          * mode for the 8259A whenever interrupts are routed
2264          * through I/O APICs.  Also IRQ0 has to be enabled in
2265          * the 8259A which implies the virtual wire has to be
2266          * disabled in the local APIC.
2267          */
2268         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2269         init_8259A(1);
2270         timer_ack = 1;
2271         if (timer_over_8254 > 0)
2272                 enable_8259A_irq(0);
2273
2274         pin1  = find_isa_irq_pin(0, mp_INT);
2275         apic1 = find_isa_irq_apic(0, mp_INT);
2276         pin2  = ioapic_i8259.pin;
2277         apic2 = ioapic_i8259.apic;
2278
2279         if (pin1 == 0)
2280                 timer_uses_ioapic_pin_0 = 1;
2281
2282         printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2283                 vector, apic1, pin1, apic2, pin2);
2284
2285         if (pin1 != -1) {
2286                 /*
2287                  * Ok, does IRQ0 through the IOAPIC work?
2288                  */
2289                 unmask_IO_APIC_irq(0);
2290                 if (timer_irq_works()) {
2291                         if (nmi_watchdog == NMI_IO_APIC) {
2292                                 disable_8259A_irq(0);
2293                                 setup_nmi();
2294                                 enable_8259A_irq(0);
2295                         }
2296                         if (disable_timer_pin_1 > 0)
2297                                 clear_IO_APIC_pin(0, pin1);
2298                         return;
2299                 }
2300                 clear_IO_APIC_pin(apic1, pin1);
2301                 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2302                                 "IO-APIC\n");
2303         }
2304
2305         printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2306         if (pin2 != -1) {
2307                 printk("\n..... (found pin %d) ...", pin2);
2308                 /*
2309                  * legacy devices should be connected to IO APIC #0
2310                  */
2311                 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
2312                 if (timer_irq_works()) {
2313                         printk("works.\n");
2314                         if (pin1 != -1)
2315                                 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2316                         else
2317                                 add_pin_to_irq(0, apic2, pin2);
2318                         if (nmi_watchdog == NMI_IO_APIC) {
2319                                 setup_nmi();
2320                         }
2321                         return;
2322                 }
2323                 /*
2324                  * Cleanup, just in case ...
2325                  */
2326                 clear_IO_APIC_pin(apic2, pin2);
2327         }
2328         printk(" failed.\n");
2329
2330         if (nmi_watchdog == NMI_IO_APIC) {
2331                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2332                 nmi_watchdog = 0;
2333         }
2334
2335         printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2336
2337         disable_8259A_irq(0);
2338         irq_desc[0].handler = &lapic_irq_type;
2339         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
2340         enable_8259A_irq(0);
2341
2342         if (timer_irq_works()) {
2343                 printk(" works.\n");
2344                 return;
2345         }
2346         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2347         printk(" failed.\n");
2348
2349         printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2350
2351         timer_ack = 0;
2352         init_8259A(0);
2353         make_8259A_irq(0);
2354         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2355
2356         unlock_ExtINT_logic();
2357
2358         if (timer_irq_works()) {
2359                 printk(" works.\n");
2360                 return;
2361         }
2362         printk(" failed :(.\n");
2363         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2364                 "report.  Then try booting with the 'noapic' option");
2365 }
2366
2367 /*
2368  *
2369  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2370  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2371  *   Linux doesn't really care, as it's not actually used
2372  *   for any interrupt handling anyway.
2373  */
2374 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
2375
2376 void __init setup_IO_APIC(void)
2377 {
2378         enable_IO_APIC();
2379
2380         if (acpi_ioapic)
2381                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
2382         else
2383                 io_apic_irqs = ~PIC_IRQS;
2384
2385         printk("ENABLING IO-APIC IRQs\n");
2386
2387         /*
2388          * Set up IO-APIC IRQ routing.
2389          */
2390         if (!acpi_ioapic)
2391                 setup_ioapic_ids_from_mpc();
2392         sync_Arb_IDs();
2393         setup_IO_APIC_irqs();
2394         init_IO_APIC_traps();
2395         check_timer();
2396         if (!acpi_ioapic)
2397                 print_IO_APIC();
2398 }
2399
2400 static int __init setup_disable_8254_timer(char *s)
2401 {
2402         timer_over_8254 = -1;
2403         return 1;
2404 }
2405 static int __init setup_enable_8254_timer(char *s)
2406 {
2407         timer_over_8254 = 2;
2408         return 1;
2409 }
2410
2411 __setup("disable_8254_timer", setup_disable_8254_timer);
2412 __setup("enable_8254_timer", setup_enable_8254_timer);
2413
2414 /*
2415  *      Called after all the initialization is done. If we didnt find any
2416  *      APIC bugs then we can allow the modify fast path
2417  */
2418
2419 static int __init io_apic_bug_finalize(void)
2420 {
2421         if(sis_apic_bug == -1)
2422                 sis_apic_bug = 0;
2423         return 0;
2424 }
2425
2426 late_initcall(io_apic_bug_finalize);
2427
2428 struct sysfs_ioapic_data {
2429         struct sys_device dev;
2430         struct IO_APIC_route_entry entry[0];
2431 };
2432 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2433
2434 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2435 {
2436         struct IO_APIC_route_entry *entry;
2437         struct sysfs_ioapic_data *data;
2438         unsigned long flags;
2439         int i;
2440
2441         data = container_of(dev, struct sysfs_ioapic_data, dev);
2442         entry = data->entry;
2443         spin_lock_irqsave(&ioapic_lock, flags);
2444         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2445                 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
2446                 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
2447         }
2448         spin_unlock_irqrestore(&ioapic_lock, flags);
2449
2450         return 0;
2451 }
2452
2453 static int ioapic_resume(struct sys_device *dev)
2454 {
2455         struct IO_APIC_route_entry *entry;
2456         struct sysfs_ioapic_data *data;
2457         unsigned long flags;
2458         union IO_APIC_reg_00 reg_00;
2459         int i;
2460
2461         data = container_of(dev, struct sysfs_ioapic_data, dev);
2462         entry = data->entry;
2463
2464         spin_lock_irqsave(&ioapic_lock, flags);
2465         reg_00.raw = io_apic_read(dev->id, 0);
2466         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2467                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2468                 io_apic_write(dev->id, 0, reg_00.raw);
2469         }
2470         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2471                 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
2472                 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
2473         }
2474         spin_unlock_irqrestore(&ioapic_lock, flags);
2475
2476         return 0;
2477 }
2478
2479 static struct sysdev_class ioapic_sysdev_class = {
2480         set_kset_name("ioapic"),
2481         .suspend = ioapic_suspend,
2482         .resume = ioapic_resume,
2483 };
2484
2485 static int __init ioapic_init_sysfs(void)
2486 {
2487         struct sys_device * dev;
2488         int i, size, error = 0;
2489
2490         error = sysdev_class_register(&ioapic_sysdev_class);
2491         if (error)
2492                 return error;
2493
2494         for (i = 0; i < nr_ioapics; i++ ) {
2495                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2496                         * sizeof(struct IO_APIC_route_entry);
2497                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2498                 if (!mp_ioapic_data[i]) {
2499                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2500                         continue;
2501                 }
2502                 memset(mp_ioapic_data[i], 0, size);
2503                 dev = &mp_ioapic_data[i]->dev;
2504                 dev->id = i;
2505                 dev->cls = &ioapic_sysdev_class;
2506                 error = sysdev_register(dev);
2507                 if (error) {
2508                         kfree(mp_ioapic_data[i]);
2509                         mp_ioapic_data[i] = NULL;
2510                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2511                         continue;
2512                 }
2513         }
2514
2515         return 0;
2516 }
2517
2518 device_initcall(ioapic_init_sysfs);
2519
2520 /* --------------------------------------------------------------------------
2521                           ACPI-based IOAPIC Configuration
2522    -------------------------------------------------------------------------- */
2523
2524 #ifdef CONFIG_ACPI
2525
2526 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2527 {
2528         union IO_APIC_reg_00 reg_00;
2529         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2530         physid_mask_t tmp;
2531         unsigned long flags;
2532         int i = 0;
2533
2534         /*
2535          * The P4 platform supports up to 256 APIC IDs on two separate APIC
2536          * buses (one for LAPICs, one for IOAPICs), where predecessors only
2537          * supports up to 16 on one shared APIC bus.
2538          *
2539          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2540          *      advantage of new APIC bus architecture.
2541          */
2542
2543         if (physids_empty(apic_id_map))
2544                 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2545
2546         spin_lock_irqsave(&ioapic_lock, flags);
2547         reg_00.raw = io_apic_read(ioapic, 0);
2548         spin_unlock_irqrestore(&ioapic_lock, flags);
2549
2550         if (apic_id >= get_physical_broadcast()) {
2551                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2552                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
2553                 apic_id = reg_00.bits.ID;
2554         }
2555
2556         /*
2557          * Every APIC in a system must have a unique ID or we get lots of nice
2558          * 'stuck on smp_invalidate_needed IPI wait' messages.
2559          */
2560         if (check_apicid_used(apic_id_map, apic_id)) {
2561
2562                 for (i = 0; i < get_physical_broadcast(); i++) {
2563                         if (!check_apicid_used(apic_id_map, i))
2564                                 break;
2565                 }
2566
2567                 if (i == get_physical_broadcast())
2568                         panic("Max apic_id exceeded!\n");
2569
2570                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2571                         "trying %d\n", ioapic, apic_id, i);
2572
2573                 apic_id = i;
2574         }
2575
2576         tmp = apicid_to_cpu_present(apic_id);
2577         physids_or(apic_id_map, apic_id_map, tmp);
2578
2579         if (reg_00.bits.ID != apic_id) {
2580                 reg_00.bits.ID = apic_id;
2581
2582                 spin_lock_irqsave(&ioapic_lock, flags);
2583                 io_apic_write(ioapic, 0, reg_00.raw);
2584                 reg_00.raw = io_apic_read(ioapic, 0);
2585                 spin_unlock_irqrestore(&ioapic_lock, flags);
2586
2587                 /* Sanity check */
2588                 if (reg_00.bits.ID != apic_id) {
2589                         printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2590                         return -1;
2591                 }
2592         }
2593
2594         apic_printk(APIC_VERBOSE, KERN_INFO
2595                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2596
2597         return apic_id;
2598 }
2599
2600
2601 int __init io_apic_get_version (int ioapic)
2602 {
2603         union IO_APIC_reg_01    reg_01;
2604         unsigned long flags;
2605
2606         spin_lock_irqsave(&ioapic_lock, flags);
2607         reg_01.raw = io_apic_read(ioapic, 1);
2608         spin_unlock_irqrestore(&ioapic_lock, flags);
2609
2610         return reg_01.bits.version;
2611 }
2612
2613
2614 int __init io_apic_get_redir_entries (int ioapic)
2615 {
2616         union IO_APIC_reg_01    reg_01;
2617         unsigned long flags;
2618
2619         spin_lock_irqsave(&ioapic_lock, flags);
2620         reg_01.raw = io_apic_read(ioapic, 1);
2621         spin_unlock_irqrestore(&ioapic_lock, flags);
2622
2623         return reg_01.bits.entries;
2624 }
2625
2626
2627 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2628 {
2629         struct IO_APIC_route_entry entry;
2630         unsigned long flags;
2631
2632         if (!IO_APIC_IRQ(irq)) {
2633                 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2634                         ioapic);
2635                 return -EINVAL;
2636         }
2637
2638         /*
2639          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2640          * Note that we mask (disable) IRQs now -- these get enabled when the
2641          * corresponding device driver registers for this IRQ.
2642          */
2643
2644         memset(&entry,0,sizeof(entry));
2645
2646         entry.delivery_mode = INT_DELIVERY_MODE;
2647         entry.dest_mode = INT_DEST_MODE;
2648         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2649         entry.trigger = edge_level;
2650         entry.polarity = active_high_low;
2651         entry.mask  = 1;
2652
2653         /*
2654          * IRQs < 16 are already in the irq_2_pin[] map
2655          */
2656         if (irq >= 16)
2657                 add_pin_to_irq(irq, ioapic, pin);
2658
2659         entry.vector = assign_irq_vector(irq);
2660
2661         apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2662                 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2663                 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2664                 edge_level, active_high_low);
2665
2666         ioapic_register_intr(irq, entry.vector, edge_level);
2667
2668         if (!ioapic && (irq < 16))
2669                 disable_8259A_irq(irq);
2670
2671         spin_lock_irqsave(&ioapic_lock, flags);
2672         io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2673         io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2674         set_native_irq_info(use_pci_vector() ? entry.vector : irq, TARGET_CPUS);
2675         spin_unlock_irqrestore(&ioapic_lock, flags);
2676
2677         return 0;
2678 }
2679
2680 #endif /* CONFIG_ACPI */