arch/i386/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/irq.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/init.h>
  27 #include <linux/delay.h>
  28 #include <linux/sched.h>
  29 #include <linux/config.h>
  30 #include <linux/smp_lock.h>
  31 #include <linux/mc146818rtc.h>
  32 #include <linux/compiler.h>
  33 #include <linux/acpi.h>
  34
  35 #include <linux/sysdev.h>
  36 #include <asm/io.h>
  37 #include <asm/smp.h>
  38 #include <asm/desc.h>
  39 #include <asm/timer.h>
  40
  41 #include <mach_apic.h>
  42
  43 #include "io_ports.h"
  44
  45 int (*ioapic_renumber_irq)(int ioapic, int irq);
  46 atomic_t irq_mis_count;
  47
  48 static DEFINE_SPINLOCK(ioapic_lock);
  49
  50 /*
  51  *      Is the SiS APIC rmw bug present ?
  52  *      -1 = don't know, 0 = no, 1 = yes
  53  */
  54 int sis_apic_bug = -1;
  55
  56 /*
  57  * # of IRQ routing registers
  58  */
  59 int nr_ioapic_registers[MAX_IO_APICS];
  60
  61 /*
  62  * Rough estimation of how many shared IRQs there are, can
  63  * be changed anytime.
  64  */
  65 #define MAX_PLUS_SHARED_IRQS NR_IRQS
  66 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  67
  68 /*
  69  * This is performance-critical, we want to do it O(1)
  70  *
  71  * the indexing order of this array favors 1:1 mappings
  72  * between pins and IRQs.
  73  */
  74
  75 static struct irq_pin_list {
  76         int apic, pin, next;
  77 } irq_2_pin[PIN_MAP_SIZE];
  78
  79 int vector_irq[NR_VECTORS] = { [0 ... NR_VECTORS - 1] = -1};
  80 #ifdef CONFIG_PCI_MSI
  81 #define vector_to_irq(vector)   \
  82         (platform_legacy_irq(vector) ? vector : vector_irq[vector])
  83 #else
  84 #define vector_to_irq(vector)   (vector)
  85 #endif
  86
  87 /*
  88  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
  89  * shared ISA-space IRQs, so we have to support them. We are super
  90  * fast in the common case, and fast for shared ISA-space IRQs.
  91  */
  92 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
  93 {
  94         static int first_free_entry = NR_IRQS;
  95         struct irq_pin_list *entry = irq_2_pin + irq;
  96
  97         while (entry->next)
  98                 entry = irq_2_pin + entry->next;
  99
 100         if (entry->pin != -1) {
 101                 entry->next = first_free_entry;
 102                 entry = irq_2_pin + entry->next;
 103                 if (++first_free_entry >= PIN_MAP_SIZE)
 104                         panic("io_apic.c: whoops");
 105         }
 106         entry->apic = apic;
 107         entry->pin = pin;
 108 }
 109
 110 /*
 111  * Reroute an IRQ to a different pin.
 112  */
 113 static void __init replace_pin_at_irq(unsigned int irq,
 114                                       int oldapic, int oldpin,
 115                                       int newapic, int newpin)
 116 {
 117         struct irq_pin_list *entry = irq_2_pin + irq;
 118
 119         while (1) {
 120                 if (entry->apic == oldapic && entry->pin == oldpin) {
 121                         entry->apic = newapic;
 122                         entry->pin = newpin;
 123                 }
 124                 if (!entry->next)
 125                         break;
 126                 entry = irq_2_pin + entry->next;
 127         }
 128 }
 129
 130 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
 131 {
 132         struct irq_pin_list *entry = irq_2_pin + irq;
 133         unsigned int pin, reg;
 134
 135         for (;;) {
 136                 pin = entry->pin;
 137                 if (pin == -1)
 138                         break;
 139                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
 140                 reg &= ~disable;
 141                 reg |= enable;
 142                 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
 143                 if (!entry->next)
 144                         break;
 145                 entry = irq_2_pin + entry->next;
 146         }
 147 }
 148
 149 /* mask = 1 */
 150 static void __mask_IO_APIC_irq (unsigned int irq)
 151 {
 152         __modify_IO_APIC_irq(irq, 0x00010000, 0);
 153 }
 154
 155 /* mask = 0 */
 156 static void __unmask_IO_APIC_irq (unsigned int irq)
 157 {
 158         __modify_IO_APIC_irq(irq, 0, 0x00010000);
 159 }
 160
 161 /* mask = 1, trigger = 0 */
 162 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
 163 {
 164         __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
 165 }
 166
 167 /* mask = 0, trigger = 1 */
 168 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
 169 {
 170         __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
 171 }
 172
 173 static void mask_IO_APIC_irq (unsigned int irq)
 174 {
 175         unsigned long flags;
 176
 177         spin_lock_irqsave(&ioapic_lock, flags);
 178         __mask_IO_APIC_irq(irq);
 179         spin_unlock_irqrestore(&ioapic_lock, flags);
 180 }
 181
 182 static void unmask_IO_APIC_irq (unsigned int irq)
 183 {
 184         unsigned long flags;
 185
 186         spin_lock_irqsave(&ioapic_lock, flags);
 187         __unmask_IO_APIC_irq(irq);
 188         spin_unlock_irqrestore(&ioapic_lock, flags);
 189 }
 190
 191 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 192 {
 193         struct IO_APIC_route_entry entry;
 194         unsigned long flags;
 195
 196         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 197         spin_lock_irqsave(&ioapic_lock, flags);
 198         *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
 199         *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
 200         spin_unlock_irqrestore(&ioapic_lock, flags);
 201         if (entry.delivery_mode == dest_SMI)
 202                 return;
 203
 204         /*
 205          * Disable it in the IO-APIC irq-routing table:
 206          */
 207         memset(&entry, 0, sizeof(entry));
 208         entry.mask = 1;
 209         spin_lock_irqsave(&ioapic_lock, flags);
 210         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
 211         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
 212         spin_unlock_irqrestore(&ioapic_lock, flags);
 213 }
 214
 215 static void clear_IO_APIC (void)
 216 {
 217         int apic, pin;
 218
 219         for (apic = 0; apic < nr_ioapics; apic++)
 220                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 221                         clear_IO_APIC_pin(apic, pin);
 222 }
 223
 224 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
 225 {
 226         unsigned long flags;
 227         int pin;
 228         struct irq_pin_list *entry = irq_2_pin + irq;
 229         unsigned int apicid_value;
 230
 231         apicid_value = cpu_mask_to_apicid(cpumask);
 232         /* Prepare to do the io_apic_write */
 233         apicid_value = apicid_value << 24;
 234         spin_lock_irqsave(&ioapic_lock, flags);
 235         for (;;) {
 236                 pin = entry->pin;
 237                 if (pin == -1)
 238                         break;
 239                 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
 240                 if (!entry->next)
 241                         break;
 242                 entry = irq_2_pin + entry->next;
 243         }
 244         spin_unlock_irqrestore(&ioapic_lock, flags);
 245 }
 246
 247 #if defined(CONFIG_IRQBALANCE)
 248 # include <asm/processor.h>     /* kernel_thread() */
 249 # include <linux/kernel_stat.h> /* kstat */
 250 # include <linux/slab.h>                /* kmalloc() */
 251 # include <linux/timer.h>       /* time_after() */
 252
 253 # ifdef CONFIG_BALANCED_IRQ_DEBUG
 254 #  define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
 255 #  define Dprintk(x...) do { TDprintk(x); } while (0)
 256 # else
 257 #  define TDprintk(x...)
 258 #  define Dprintk(x...)
 259 # endif
 260
 261 cpumask_t __cacheline_aligned pending_irq_balance_cpumask[NR_IRQS];
 262
 263 #define IRQBALANCE_CHECK_ARCH -999
 264 static int irqbalance_disabled = IRQBALANCE_CHECK_ARCH;
 265 static int physical_balance = 0;
 266
 267 static struct irq_cpu_info {
 268         unsigned long * last_irq;
 269         unsigned long * irq_delta;
 270         unsigned long irq;
 271 } irq_cpu_data[NR_CPUS];
 272
 273 #define CPU_IRQ(cpu)            (irq_cpu_data[cpu].irq)
 274 #define LAST_CPU_IRQ(cpu,irq)   (irq_cpu_data[cpu].last_irq[irq])
 275 #define IRQ_DELTA(cpu,irq)      (irq_cpu_data[cpu].irq_delta[irq])
 276
 277 #define IDLE_ENOUGH(cpu,now) \
 278         (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
 279
 280 #define IRQ_ALLOWED(cpu, allowed_mask)  cpu_isset(cpu, allowed_mask)
 281
 282 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
 283
 284 #define MAX_BALANCED_IRQ_INTERVAL       (5*HZ)
 285 #define MIN_BALANCED_IRQ_INTERVAL       (HZ/2)
 286 #define BALANCED_IRQ_MORE_DELTA         (HZ/10)
 287 #define BALANCED_IRQ_LESS_DELTA         (HZ)
 288
 289 static long balanced_irq_interval = MAX_BALANCED_IRQ_INTERVAL;
 290
 291 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
 292                         unsigned long now, int direction)
 293 {
 294         int search_idle = 1;
 295         int cpu = curr_cpu;
 296
 297         goto inside;
 298
 299         do {
 300                 if (unlikely(cpu == curr_cpu))
 301                         search_idle = 0;
 302 inside:
 303                 if (direction == 1) {
 304                         cpu++;
 305                         if (cpu >= NR_CPUS)
 306                                 cpu = 0;
 307                 } else {
 308                         cpu--;
 309                         if (cpu == -1)
 310                                 cpu = NR_CPUS-1;
 311                 }
 312         } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
 313                         (search_idle && !IDLE_ENOUGH(cpu,now)));
 314
 315         return cpu;
 316 }
 317
 318 static inline void balance_irq(int cpu, int irq)
 319 {
 320         unsigned long now = jiffies;
 321         cpumask_t allowed_mask;
 322         unsigned int new_cpu;
 323
 324         if (irqbalance_disabled)
 325                 return;
 326
 327         cpus_and(allowed_mask, cpu_online_map, irq_affinity[irq]);
 328         new_cpu = move(cpu, allowed_mask, now, 1);
 329         if (cpu != new_cpu) {
 330                 irq_desc_t *desc = irq_desc + irq;
 331                 unsigned long flags;
 332
 333                 spin_lock_irqsave(&desc->lock, flags);
 334                 pending_irq_balance_cpumask[irq] = cpumask_of_cpu(new_cpu);
 335                 spin_unlock_irqrestore(&desc->lock, flags);
 336         }
 337 }
 338
 339 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
 340 {
 341         int i, j;
 342         Dprintk("Rotating IRQs among CPUs.\n");
 343         for (i = 0; i < NR_CPUS; i++) {
 344                 for (j = 0; cpu_online(i) && (j < NR_IRQS); j++) {
 345                         if (!irq_desc[j].action)
 346                                 continue;
 347                         /* Is it a significant load ?  */
 348                         if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
 349                                                 useful_load_threshold)
 350                                 continue;
 351                         balance_irq(i, j);
 352                 }
 353         }
 354         balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 355                 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 356         return;
 357 }
 358
 359 static void do_irq_balance(void)
 360 {
 361         int i, j;
 362         unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
 363         unsigned long move_this_load = 0;
 364         int max_loaded = 0, min_loaded = 0;
 365         int load;
 366         unsigned long useful_load_threshold = balanced_irq_interval + 10;
 367         int selected_irq;
 368         int tmp_loaded, first_attempt = 1;
 369         unsigned long tmp_cpu_irq;
 370         unsigned long imbalance = 0;
 371         cpumask_t allowed_mask, target_cpu_mask, tmp;
 372
 373         for (i = 0; i < NR_CPUS; i++) {
 374                 int package_index;
 375                 CPU_IRQ(i) = 0;
 376                 if (!cpu_online(i))
 377                         continue;
 378                 package_index = CPU_TO_PACKAGEINDEX(i);
 379                 for (j = 0; j < NR_IRQS; j++) {
 380                         unsigned long value_now, delta;
 381                         /* Is this an active IRQ? */
 382                         if (!irq_desc[j].action)
 383                                 continue;
 384                         if ( package_index == i )
 385                                 IRQ_DELTA(package_index,j) = 0;
 386                         /* Determine the total count per processor per IRQ */
 387                         value_now = (unsigned long) kstat_cpu(i).irqs[j];
 388
 389                         /* Determine the activity per processor per IRQ */
 390                         delta = value_now - LAST_CPU_IRQ(i,j);
 391
 392                         /* Update last_cpu_irq[][] for the next time */
 393                         LAST_CPU_IRQ(i,j) = value_now;
 394
 395                         /* Ignore IRQs whose rate is less than the clock */
 396                         if (delta < useful_load_threshold)
 397                                 continue;
 398                         /* update the load for the processor or package total */
 399                         IRQ_DELTA(package_index,j) += delta;
 400
 401                         /* Keep track of the higher numbered sibling as well */
 402                         if (i != package_index)
 403                                 CPU_IRQ(i) += delta;
 404                         /*
 405                          * We have sibling A and sibling B in the package
 406                          *
 407                          * cpu_irq[A] = load for cpu A + load for cpu B
 408                          * cpu_irq[B] = load for cpu B
 409                          */
 410                         CPU_IRQ(package_index) += delta;
 411                 }
 412         }
 413         /* Find the least loaded processor package */
 414         for (i = 0; i < NR_CPUS; i++) {
 415                 if (!cpu_online(i))
 416                         continue;
 417                 if (i != CPU_TO_PACKAGEINDEX(i))
 418                         continue;
 419                 if (min_cpu_irq > CPU_IRQ(i)) {
 420                         min_cpu_irq = CPU_IRQ(i);
 421                         min_loaded = i;
 422                 }
 423         }
 424         max_cpu_irq = ULONG_MAX;
 425
 426 tryanothercpu:
 427         /* Look for heaviest loaded processor.
 428          * We may come back to get the next heaviest loaded processor.
 429          * Skip processors with trivial loads.
 430          */
 431         tmp_cpu_irq = 0;
 432         tmp_loaded = -1;
 433         for (i = 0; i < NR_CPUS; i++) {
 434                 if (!cpu_online(i))
 435                         continue;
 436                 if (i != CPU_TO_PACKAGEINDEX(i))
 437                         continue;
 438                 if (max_cpu_irq <= CPU_IRQ(i))
 439                         continue;
 440                 if (tmp_cpu_irq < CPU_IRQ(i)) {
 441                         tmp_cpu_irq = CPU_IRQ(i);
 442                         tmp_loaded = i;
 443                 }
 444         }
 445
 446         if (tmp_loaded == -1) {
 447          /* In the case of small number of heavy interrupt sources,
 448           * loading some of the cpus too much. We use Ingo's original
 449           * approach to rotate them around.
 450           */
 451                 if (!first_attempt && imbalance >= useful_load_threshold) {
 452                         rotate_irqs_among_cpus(useful_load_threshold);
 453                         return;
 454                 }
 455                 goto not_worth_the_effort;
 456         }
 457
 458         first_attempt = 0;              /* heaviest search */
 459         max_cpu_irq = tmp_cpu_irq;      /* load */
 460         max_loaded = tmp_loaded;        /* processor */
 461         imbalance = (max_cpu_irq - min_cpu_irq) / 2;
 462
 463         Dprintk("max_loaded cpu = %d\n", max_loaded);
 464         Dprintk("min_loaded cpu = %d\n", min_loaded);
 465         Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
 466         Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
 467         Dprintk("load imbalance = %lu\n", imbalance);
 468
 469         /* if imbalance is less than approx 10% of max load, then
 470          * observe diminishing returns action. - quit
 471          */
 472         if (imbalance < (max_cpu_irq >> 3)) {
 473                 Dprintk("Imbalance too trivial\n");
 474                 goto not_worth_the_effort;
 475         }
 476
 477 tryanotherirq:
 478         /* if we select an IRQ to move that can't go where we want, then
 479          * see if there is another one to try.
 480          */
 481         move_this_load = 0;
 482         selected_irq = -1;
 483         for (j = 0; j < NR_IRQS; j++) {
 484                 /* Is this an active IRQ? */
 485                 if (!irq_desc[j].action)
 486                         continue;
 487                 if (imbalance <= IRQ_DELTA(max_loaded,j))
 488                         continue;
 489                 /* Try to find the IRQ that is closest to the imbalance
 490                  * without going over.
 491                  */
 492                 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
 493                         move_this_load = IRQ_DELTA(max_loaded,j);
 494                         selected_irq = j;
 495                 }
 496         }
 497         if (selected_irq == -1) {
 498                 goto tryanothercpu;
 499         }
 500
 501         imbalance = move_this_load;
 502
 503         /* For physical_balance case, we accumlated both load
 504          * values in the one of the siblings cpu_irq[],
 505          * to use the same code for physical and logical processors
 506          * as much as possible.
 507          *
 508          * NOTE: the cpu_irq[] array holds the sum of the load for
 509          * sibling A and sibling B in the slot for the lowest numbered
 510          * sibling (A), _AND_ the load for sibling B in the slot for
 511          * the higher numbered sibling.
 512          *
 513          * We seek the least loaded sibling by making the comparison
 514          * (A+B)/2 vs B
 515          */
 516         load = CPU_IRQ(min_loaded) >> 1;
 517         for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
 518                 if (load > CPU_IRQ(j)) {
 519                         /* This won't change cpu_sibling_map[min_loaded] */
 520                         load = CPU_IRQ(j);
 521                         min_loaded = j;
 522                 }
 523         }
 524
 525         cpus_and(allowed_mask, cpu_online_map, irq_affinity[selected_irq]);
 526         target_cpu_mask = cpumask_of_cpu(min_loaded);
 527         cpus_and(tmp, target_cpu_mask, allowed_mask);
 528
 529         if (!cpus_empty(tmp)) {
 530                 irq_desc_t *desc = irq_desc + selected_irq;
 531                 unsigned long flags;
 532
 533                 Dprintk("irq = %d moved to cpu = %d\n",
 534                                 selected_irq, min_loaded);
 535                 /* mark for change destination */
 536                 spin_lock_irqsave(&desc->lock, flags);
 537                 pending_irq_balance_cpumask[selected_irq] =
 538                                         cpumask_of_cpu(min_loaded);
 539                 spin_unlock_irqrestore(&desc->lock, flags);
 540                 /* Since we made a change, come back sooner to
 541                  * check for more variation.
 542                  */
 543                 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 544                         balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 545                 return;
 546         }
 547         goto tryanotherirq;
 548
 549 not_worth_the_effort:
 550         /*
 551          * if we did not find an IRQ to move, then adjust the time interval
 552          * upward
 553          */
 554         balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
 555                 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
 556         Dprintk("IRQ worth rotating not found\n");
 557         return;
 558 }
 559
 560 static int balanced_irq(void *unused)
 561 {
 562         int i;
 563         unsigned long prev_balance_time = jiffies;
 564         long time_remaining = balanced_irq_interval;
 565
 566         daemonize("kirqd");
 567
 568         /* push everything to CPU 0 to give us a starting point.  */
 569         for (i = 0 ; i < NR_IRQS ; i++) {
 570                 pending_irq_balance_cpumask[i] = cpumask_of_cpu(0);
 571         }
 572
 573         for ( ; ; ) {
 574                 set_current_state(TASK_INTERRUPTIBLE);
 575                 time_remaining = schedule_timeout(time_remaining);
 576                 try_to_freeze(PF_FREEZE);
 577                 if (time_after(jiffies,
 578                                 prev_balance_time+balanced_irq_interval)) {
 579                         do_irq_balance();
 580                         prev_balance_time = jiffies;
 581                         time_remaining = balanced_irq_interval;
 582                 }
 583         }
 584         return 0;
 585 }
 586
 587 static int __init balanced_irq_init(void)
 588 {
 589         int i;
 590         struct cpuinfo_x86 *c;
 591         cpumask_t tmp;
 592
 593         cpus_shift_right(tmp, cpu_online_map, 2);
 594         c = &boot_cpu_data;
 595         /* When not overwritten by the command line ask subarchitecture. */
 596         if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
 597                 irqbalance_disabled = NO_BALANCE_IRQ;
 598         if (irqbalance_disabled)
 599                 return 0;
 600
 601          /* disable irqbalance completely if there is only one processor online */
 602         if (num_online_cpus() < 2) {
 603                 irqbalance_disabled = 1;
 604                 return 0;
 605         }
 606         /*
 607          * Enable physical balance only if more than 1 physical processor
 608          * is present
 609          */
 610         if (smp_num_siblings > 1 && !cpus_empty(tmp))
 611                 physical_balance = 1;
 612
 613         for (i = 0; i < NR_CPUS; i++) {
 614                 if (!cpu_online(i))
 615                         continue;
 616                 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 617                 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 618                 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
 619                         printk(KERN_ERR "balanced_irq_init: out of memory");
 620                         goto failed;
 621                 }
 622                 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
 623                 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
 624         }
 625
 626         printk(KERN_INFO "Starting balanced_irq\n");
 627         if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0)
 628                 return 0;
 629         else
 630                 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
 631 failed:
 632         for (i = 0; i < NR_CPUS; i++) {
 633                 if(irq_cpu_data[i].irq_delta)
 634                         kfree(irq_cpu_data[i].irq_delta);
 635                 if(irq_cpu_data[i].last_irq)
 636                         kfree(irq_cpu_data[i].last_irq);
 637         }
 638         return 0;
 639 }
 640
 641 int __init irqbalance_disable(char *str)
 642 {
 643         irqbalance_disabled = 1;
 644         return 0;
 645 }
 646
 647 __setup("noirqbalance", irqbalance_disable);
 648
 649 static inline void move_irq(int irq)
 650 {
 651         /* note - we hold the desc->lock */
 652         if (unlikely(!cpus_empty(pending_irq_balance_cpumask[irq]))) {
 653                 set_ioapic_affinity_irq(irq, pending_irq_balance_cpumask[irq]);
 654                 cpus_clear(pending_irq_balance_cpumask[irq]);
 655         }
 656 }
 657
 658 late_initcall(balanced_irq_init);
 659
 660 #else /* !CONFIG_IRQBALANCE */
 661 static inline void move_irq(int irq) { }
 662 #endif /* CONFIG_IRQBALANCE */
 663
 664 #ifndef CONFIG_SMP
 665 void fastcall send_IPI_self(int vector)
 666 {
 667         unsigned int cfg;
 668
 669         /*
 670          * Wait for idle.
 671          */
 672         apic_wait_icr_idle();
 673         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
 674         /*
 675          * Send the IPI. The write to APIC_ICR fires this off.
 676          */
 677         apic_write_around(APIC_ICR, cfg);
 678 }
 679 #endif /* !CONFIG_SMP */
 680
 681
 682 /*
 683  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 684  * specific CPU-side IRQs.
 685  */
 686
 687 #define MAX_PIRQS 8
 688 static int pirq_entries [MAX_PIRQS];
 689 static int pirqs_enabled;
 690 int skip_ioapic_setup;
 691
 692 static int __init ioapic_setup(char *str)
 693 {
 694         skip_ioapic_setup = 1;
 695         return 1;
 696 }
 697
 698 __setup("noapic", ioapic_setup);
 699
 700 static int __init ioapic_pirq_setup(char *str)
 701 {
 702         int i, max;
 703         int ints[MAX_PIRQS+1];
 704
 705         get_options(str, ARRAY_SIZE(ints), ints);
 706
 707         for (i = 0; i < MAX_PIRQS; i++)
 708                 pirq_entries[i] = -1;
 709
 710         pirqs_enabled = 1;
 711         apic_printk(APIC_VERBOSE, KERN_INFO
 712                         "PIRQ redirection, working around broken MP-BIOS.\n");
 713         max = MAX_PIRQS;
 714         if (ints[0] < MAX_PIRQS)
 715                 max = ints[0];
 716
 717         for (i = 0; i < max; i++) {
 718                 apic_printk(APIC_VERBOSE, KERN_DEBUG
 719                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 720                 /*
 721                  * PIRQs are mapped upside down, usually.
 722                  */
 723                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 724         }
 725         return 1;
 726 }
 727
 728 __setup("pirq=", ioapic_pirq_setup);
 729
 730 /*
 731  * Find the IRQ entry number of a certain pin.
 732  */
 733 static int find_irq_entry(int apic, int pin, int type)
 734 {
 735         int i;
 736
 737         for (i = 0; i < mp_irq_entries; i++)
 738                 if (mp_irqs[i].mpc_irqtype == type &&
 739                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 740                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 741                     mp_irqs[i].mpc_dstirq == pin)
 742                         return i;
 743
 744         return -1;
 745 }
 746
 747 /*
 748  * Find the pin to which IRQ[irq] (ISA) is connected
 749  */
 750 static int find_isa_irq_pin(int irq, int type)
 751 {
 752         int i;
 753
 754         for (i = 0; i < mp_irq_entries; i++) {
 755                 int lbus = mp_irqs[i].mpc_srcbus;
 756
 757                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 758                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 759                      mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
 760                      mp_bus_id_to_type[lbus] == MP_BUS_NEC98
 761                     ) &&
 762                     (mp_irqs[i].mpc_irqtype == type) &&
 763                     (mp_irqs[i].mpc_srcbusirq == irq))
 764
 765                         return mp_irqs[i].mpc_dstirq;
 766         }
 767         return -1;
 768 }
 769
 770 /*
 771  * Find a specific PCI IRQ entry.
 772  * Not an __init, possibly needed by modules
 773  */
 774 static int pin_2_irq(int idx, int apic, int pin);
 775
 776 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 777 {
 778         int apic, i, best_guess = -1;
 779
 780         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
 781                 "slot:%d, pin:%d.\n", bus, slot, pin);
 782         if (mp_bus_id_to_pci_bus[bus] == -1) {
 783                 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 784                 return -1;
 785         }
 786         for (i = 0; i < mp_irq_entries; i++) {
 787                 int lbus = mp_irqs[i].mpc_srcbus;
 788
 789                 for (apic = 0; apic < nr_ioapics; apic++)
 790                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 791                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 792                                 break;
 793
 794                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
 795                     !mp_irqs[i].mpc_irqtype &&
 796                     (bus == lbus) &&
 797                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 798                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 799
 800                         if (!(apic || IO_APIC_IRQ(irq)))
 801                                 continue;
 802
 803                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 804                                 return irq;
 805                         /*
 806                          * Use the first all-but-pin matching entry as a
 807                          * best-guess fuzzy result for broken mptables.
 808                          */
 809                         if (best_guess < 0)
 810                                 best_guess = irq;
 811                 }
 812         }
 813         return best_guess;
 814 }
 815
 816 /*
 817  * This function currently is only a helper for the i386 smp boot process where
 818  * we need to reprogram the ioredtbls to cater for the cpus which have come online
 819  * so mask in all cases should simply be TARGET_CPUS
 820  */
 821 void __init setup_ioapic_dest(void)
 822 {
 823         int pin, ioapic, irq, irq_entry;
 824
 825         if (skip_ioapic_setup == 1)
 826                 return;
 827
 828         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
 829                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
 830                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
 831                         if (irq_entry == -1)
 832                                 continue;
 833                         irq = pin_2_irq(irq_entry, ioapic, pin);
 834                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
 835                 }
 836
 837         }
 838 }
 839
 840 /*
 841  * EISA Edge/Level control register, ELCR
 842  */
 843 static int EISA_ELCR(unsigned int irq)
 844 {
 845         if (irq < 16) {
 846                 unsigned int port = 0x4d0 + (irq >> 3);
 847                 return (inb(port) >> (irq & 7)) & 1;
 848         }
 849         apic_printk(APIC_VERBOSE, KERN_INFO
 850                         "Broken MPtable reports ISA irq %d\n", irq);
 851         return 0;
 852 }
 853
 854 /* EISA interrupts are always polarity zero and can be edge or level
 855  * trigger depending on the ELCR value.  If an interrupt is listed as
 856  * EISA conforming in the MP table, that means its trigger type must
 857  * be read in from the ELCR */
 858
 859 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
 860 #define default_EISA_polarity(idx)      (0)
 861
 862 /* ISA interrupts are always polarity zero edge triggered,
 863  * when listed as conforming in the MP table. */
 864
 865 #define default_ISA_trigger(idx)        (0)
 866 #define default_ISA_polarity(idx)       (0)
 867
 868 /* PCI interrupts are always polarity one level triggered,
 869  * when listed as conforming in the MP table. */
 870
 871 #define default_PCI_trigger(idx)        (1)
 872 #define default_PCI_polarity(idx)       (1)
 873
 874 /* MCA interrupts are always polarity zero level triggered,
 875  * when listed as conforming in the MP table. */
 876
 877 #define default_MCA_trigger(idx)        (1)
 878 #define default_MCA_polarity(idx)       (0)
 879
 880 /* NEC98 interrupts are always polarity zero edge triggered,
 881  * when listed as conforming in the MP table. */
 882
 883 #define default_NEC98_trigger(idx)     (0)
 884 #define default_NEC98_polarity(idx)    (0)
 885
 886 static int __init MPBIOS_polarity(int idx)
 887 {
 888         int bus = mp_irqs[idx].mpc_srcbus;
 889         int polarity;
 890
 891         /*
 892          * Determine IRQ line polarity (high active or low active):
 893          */
 894         switch (mp_irqs[idx].mpc_irqflag & 3)
 895         {
 896                 case 0: /* conforms, ie. bus-type dependent polarity */
 897                 {
 898                         switch (mp_bus_id_to_type[bus])
 899                         {
 900                                 case MP_BUS_ISA: /* ISA pin */
 901                                 {
 902                                         polarity = default_ISA_polarity(idx);
 903                                         break;
 904                                 }
 905                                 case MP_BUS_EISA: /* EISA pin */
 906                                 {
 907                                         polarity = default_EISA_polarity(idx);
 908                                         break;
 909                                 }
 910                                 case MP_BUS_PCI: /* PCI pin */
 911                                 {
 912                                         polarity = default_PCI_polarity(idx);
 913                                         break;
 914                                 }
 915                                 case MP_BUS_MCA: /* MCA pin */
 916                                 {
 917                                         polarity = default_MCA_polarity(idx);
 918                                         break;
 919                                 }
 920                                 case MP_BUS_NEC98: /* NEC 98 pin */
 921                                 {
 922                                         polarity = default_NEC98_polarity(idx);
 923                                         break;
 924                                 }
 925                                 default:
 926                                 {
 927                                         printk(KERN_WARNING "broken BIOS!!\n");
 928                                         polarity = 1;
 929                                         break;
 930                                 }
 931                         }
 932                         break;
 933                 }
 934                 case 1: /* high active */
 935                 {
 936                         polarity = 0;
 937                         break;
 938                 }
 939                 case 2: /* reserved */
 940                 {
 941                         printk(KERN_WARNING "broken BIOS!!\n");
 942                         polarity = 1;
 943                         break;
 944                 }
 945                 case 3: /* low active */
 946                 {
 947                         polarity = 1;
 948                         break;
 949                 }
 950                 default: /* invalid */
 951                 {
 952                         printk(KERN_WARNING "broken BIOS!!\n");
 953                         polarity = 1;
 954                         break;
 955                 }
 956         }
 957         return polarity;
 958 }
 959
 960 static int MPBIOS_trigger(int idx)
 961 {
 962         int bus = mp_irqs[idx].mpc_srcbus;
 963         int trigger;
 964
 965         /*
 966          * Determine IRQ trigger mode (edge or level sensitive):
 967          */
 968         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
 969         {
 970                 case 0: /* conforms, ie. bus-type dependent */
 971                 {
 972                         switch (mp_bus_id_to_type[bus])
 973                         {
 974                                 case MP_BUS_ISA: /* ISA pin */
 975                                 {
 976                                         trigger = default_ISA_trigger(idx);
 977                                         break;
 978                                 }
 979                                 case MP_BUS_EISA: /* EISA pin */
 980                                 {
 981                                         trigger = default_EISA_trigger(idx);
 982                                         break;
 983                                 }
 984                                 case MP_BUS_PCI: /* PCI pin */
 985                                 {
 986                                         trigger = default_PCI_trigger(idx);
 987                                         break;
 988                                 }
 989                                 case MP_BUS_MCA: /* MCA pin */
 990                                 {
 991                                         trigger = default_MCA_trigger(idx);
 992                                         break;
 993                                 }
 994                                 case MP_BUS_NEC98: /* NEC 98 pin */
 995                                 {
 996                                         trigger = default_NEC98_trigger(idx);
 997                                         break;
 998                                 }
 999                                 default:
1000                                 {
1001                                         printk(KERN_WARNING "broken BIOS!!\n");
1002                                         trigger = 1;
1003                                         break;
1004                                 }
1005                         }
1006                         break;
1007                 }
1008                 case 1: /* edge */
1009                 {
1010                         trigger = 0;
1011                         break;
1012                 }
1013                 case 2: /* reserved */
1014                 {
1015                         printk(KERN_WARNING "broken BIOS!!\n");
1016                         trigger = 1;
1017                         break;
1018                 }
1019                 case 3: /* level */
1020                 {
1021                         trigger = 1;
1022                         break;
1023                 }
1024                 default: /* invalid */
1025                 {
1026                         printk(KERN_WARNING "broken BIOS!!\n");
1027                         trigger = 0;
1028                         break;
1029                 }
1030         }
1031         return trigger;
1032 }
1033
1034 static inline int irq_polarity(int idx)
1035 {
1036         return MPBIOS_polarity(idx);
1037 }
1038
1039 static inline int irq_trigger(int idx)
1040 {
1041         return MPBIOS_trigger(idx);
1042 }
1043
1044 static int pin_2_irq(int idx, int apic, int pin)
1045 {
1046         int irq, i;
1047         int bus = mp_irqs[idx].mpc_srcbus;
1048
1049         /*
1050          * Debugging check, we are in big trouble if this message pops up!
1051          */
1052         if (mp_irqs[idx].mpc_dstirq != pin)
1053                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1054
1055         switch (mp_bus_id_to_type[bus])
1056         {
1057                 case MP_BUS_ISA: /* ISA pin */
1058                 case MP_BUS_EISA:
1059                 case MP_BUS_MCA:
1060                 case MP_BUS_NEC98:
1061                 {
1062                         irq = mp_irqs[idx].mpc_srcbusirq;
1063                         break;
1064                 }
1065                 case MP_BUS_PCI: /* PCI pin */
1066                 {
1067                         /*
1068                          * PCI IRQs are mapped in order
1069                          */
1070                         i = irq = 0;
1071                         while (i < apic)
1072                                 irq += nr_ioapic_registers[i++];
1073                         irq += pin;
1074
1075                         /*
1076                          * For MPS mode, so far only needed by ES7000 platform
1077                          */
1078                         if (ioapic_renumber_irq)
1079                                 irq = ioapic_renumber_irq(apic, irq);
1080
1081                         break;
1082                 }
1083                 default:
1084                 {
1085                         printk(KERN_ERR "unknown bus type %d.\n",bus);
1086                         irq = 0;
1087                         break;
1088                 }
1089         }
1090
1091         /*
1092          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1093          */
1094         if ((pin >= 16) && (pin <= 23)) {
1095                 if (pirq_entries[pin-16] != -1) {
1096                         if (!pirq_entries[pin-16]) {
1097                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1098                                                 "disabling PIRQ%d\n", pin-16);
1099                         } else {
1100                                 irq = pirq_entries[pin-16];
1101                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1102                                                 "using PIRQ%d -> IRQ %d\n",
1103                                                 pin-16, irq);
1104                         }
1105                 }
1106         }
1107         return irq;
1108 }
1109
1110 static inline int IO_APIC_irq_trigger(int irq)
1111 {
1112         int apic, idx, pin;
1113
1114         for (apic = 0; apic < nr_ioapics; apic++) {
1115                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1116                         idx = find_irq_entry(apic,pin,mp_INT);
1117                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1118                                 return irq_trigger(idx);
1119                 }
1120         }
1121         /*
1122          * nonexistent IRQs are edge default
1123          */
1124         return 0;
1125 }
1126
1127 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1128 u8 irq_vector[NR_IRQ_VECTORS] = { FIRST_DEVICE_VECTOR , 0 };
1129
1130 int assign_irq_vector(int irq)
1131 {
1132         static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
1133
1134         BUG_ON(irq >= NR_IRQ_VECTORS);
1135         if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0)
1136                 return IO_APIC_VECTOR(irq);
1137 next:
1138         current_vector += 8;
1139         if (current_vector == SYSCALL_VECTOR)
1140                 goto next;
1141
1142         if (current_vector >= FIRST_SYSTEM_VECTOR) {
1143                 offset++;
1144                 if (!(offset%8))
1145                         return -ENOSPC;
1146                 current_vector = FIRST_DEVICE_VECTOR + offset;
1147         }
1148
1149         vector_irq[current_vector] = irq;
1150         if (irq != AUTO_ASSIGN)
1151                 IO_APIC_VECTOR(irq) = current_vector;
1152
1153         return current_vector;
1154 }
1155
1156 static struct hw_interrupt_type ioapic_level_type;
1157 static struct hw_interrupt_type ioapic_edge_type;
1158
1159 #define IOAPIC_AUTO     -1
1160 #define IOAPIC_EDGE     0
1161 #define IOAPIC_LEVEL    1
1162
1163 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1164 {
1165         if (use_pci_vector() && !platform_legacy_irq(irq)) {
1166                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1167                                 trigger == IOAPIC_LEVEL)
1168                         irq_desc[vector].handler = &ioapic_level_type;
1169                 else
1170                         irq_desc[vector].handler = &ioapic_edge_type;
1171                 set_intr_gate(vector, interrupt[vector]);
1172         } else  {
1173                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1174                                 trigger == IOAPIC_LEVEL)
1175                         irq_desc[irq].handler = &ioapic_level_type;
1176                 else
1177                         irq_desc[irq].handler = &ioapic_edge_type;
1178                 set_intr_gate(vector, interrupt[irq]);
1179         }
1180 }
1181
1182 static void __init setup_IO_APIC_irqs(void)
1183 {
1184         struct IO_APIC_route_entry entry;
1185         int apic, pin, idx, irq, first_notcon = 1, vector;
1186         unsigned long flags;
1187
1188         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1189
1190         for (apic = 0; apic < nr_ioapics; apic++) {
1191         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1192
1193                 /*
1194                  * add it to the IO-APIC irq-routing table:
1195                  */
1196                 memset(&entry,0,sizeof(entry));
1197
1198                 entry.delivery_mode = INT_DELIVERY_MODE;
1199                 entry.dest_mode = INT_DEST_MODE;
1200                 entry.mask = 0;                         /* enable IRQ */
1201                 entry.dest.logical.logical_dest =
1202                                         cpu_mask_to_apicid(TARGET_CPUS);
1203
1204                 idx = find_irq_entry(apic,pin,mp_INT);
1205                 if (idx == -1) {
1206                         if (first_notcon) {
1207                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1208                                                 " IO-APIC (apicid-pin) %d-%d",
1209                                                 mp_ioapics[apic].mpc_apicid,
1210                                                 pin);
1211                                 first_notcon = 0;
1212                         } else
1213                                 apic_printk(APIC_VERBOSE, ", %d-%d",
1214                                         mp_ioapics[apic].mpc_apicid, pin);
1215                         continue;
1216                 }
1217
1218                 entry.trigger = irq_trigger(idx);
1219                 entry.polarity = irq_polarity(idx);
1220
1221                 if (irq_trigger(idx)) {
1222                         entry.trigger = 1;
1223                         entry.mask = 1;
1224                 }
1225
1226                 irq = pin_2_irq(idx, apic, pin);
1227                 /*
1228                  * skip adding the timer int on secondary nodes, which causes
1229                  * a small but painful rift in the time-space continuum
1230                  */
1231                 if (multi_timer_check(apic, irq))
1232                         continue;
1233                 else
1234                         add_pin_to_irq(irq, apic, pin);
1235
1236                 if (!apic && !IO_APIC_IRQ(irq))
1237                         continue;
1238
1239                 if (IO_APIC_IRQ(irq)) {
1240                         vector = assign_irq_vector(irq);
1241                         entry.vector = vector;
1242                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1243
1244                         if (!apic && (irq < 16))
1245                                 disable_8259A_irq(irq);
1246                 }
1247                 spin_lock_irqsave(&ioapic_lock, flags);
1248                 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1249                 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1250                 spin_unlock_irqrestore(&ioapic_lock, flags);
1251         }
1252         }
1253
1254         if (!first_notcon)
1255                 apic_printk(APIC_VERBOSE, " not connected.\n");
1256 }
1257
1258 /*
1259  * Set up the 8259A-master output pin:
1260  */
1261 static void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
1262 {
1263         struct IO_APIC_route_entry entry;
1264         unsigned long flags;
1265
1266         memset(&entry,0,sizeof(entry));
1267
1268         disable_8259A_irq(0);
1269
1270         /* mask LVT0 */
1271         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1272
1273         /*
1274          * We use logical delivery to get the timer IRQ
1275          * to the first CPU.
1276          */
1277         entry.dest_mode = INT_DEST_MODE;
1278         entry.mask = 0;                                 /* unmask IRQ now */
1279         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1280         entry.delivery_mode = INT_DELIVERY_MODE;
1281         entry.polarity = 0;
1282         entry.trigger = 0;
1283         entry.vector = vector;
1284
1285         /*
1286          * The timer IRQ doesn't have to know that behind the
1287          * scene we have a 8259A-master in AEOI mode ...
1288          */
1289         irq_desc[0].handler = &ioapic_edge_type;
1290
1291         /*
1292          * Add it to the IO-APIC irq-routing table:
1293          */
1294         spin_lock_irqsave(&ioapic_lock, flags);
1295         io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
1296         io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
1297         spin_unlock_irqrestore(&ioapic_lock, flags);
1298
1299         enable_8259A_irq(0);
1300 }
1301
1302 static inline void UNEXPECTED_IO_APIC(void)
1303 {
1304 }
1305
1306 void __init print_IO_APIC(void)
1307 {
1308         int apic, i;
1309         union IO_APIC_reg_00 reg_00;
1310         union IO_APIC_reg_01 reg_01;
1311         union IO_APIC_reg_02 reg_02;
1312         union IO_APIC_reg_03 reg_03;
1313         unsigned long flags;
1314
1315         if (apic_verbosity == APIC_QUIET)
1316                 return;
1317
1318         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1319         for (i = 0; i < nr_ioapics; i++)
1320                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1321                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1322
1323         /*
1324          * We are a bit conservative about what we expect.  We have to
1325          * know about every hardware change ASAP.
1326          */
1327         printk(KERN_INFO "testing the IO APIC.......................\n");
1328
1329         for (apic = 0; apic < nr_ioapics; apic++) {
1330
1331         spin_lock_irqsave(&ioapic_lock, flags);
1332         reg_00.raw = io_apic_read(apic, 0);
1333         reg_01.raw = io_apic_read(apic, 1);
1334         if (reg_01.bits.version >= 0x10)
1335                 reg_02.raw = io_apic_read(apic, 2);
1336         if (reg_01.bits.version >= 0x20)
1337                 reg_03.raw = io_apic_read(apic, 3);
1338         spin_unlock_irqrestore(&ioapic_lock, flags);
1339
1340         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1341         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1342         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1343         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1344         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1345         if (reg_00.bits.ID >= get_physical_broadcast())
1346                 UNEXPECTED_IO_APIC();
1347         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1348                 UNEXPECTED_IO_APIC();
1349
1350         printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1351         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1352         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1353                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1354                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1355                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1356                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1357                 (reg_01.bits.entries != 0x2E) &&
1358                 (reg_01.bits.entries != 0x3F)
1359         )
1360                 UNEXPECTED_IO_APIC();
1361
1362         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1363         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1364         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1365                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1366                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1367                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1368                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
1369         )
1370                 UNEXPECTED_IO_APIC();
1371         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1372                 UNEXPECTED_IO_APIC();
1373
1374         /*
1375          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1376          * but the value of reg_02 is read as the previous read register
1377          * value, so ignore it if reg_02 == reg_01.
1378          */
1379         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1380                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1381                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1382                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1383                         UNEXPECTED_IO_APIC();
1384         }
1385
1386         /*
1387          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1388          * or reg_03, but the value of reg_0[23] is read as the previous read
1389          * register value, so ignore it if reg_03 == reg_0[12].
1390          */
1391         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1392             reg_03.raw != reg_01.raw) {
1393                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1394                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1395                 if (reg_03.bits.__reserved_1)
1396                         UNEXPECTED_IO_APIC();
1397         }
1398
1399         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1400
1401         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1402                           " Stat Dest Deli Vect:   \n");
1403
1404         for (i = 0; i <= reg_01.bits.entries; i++) {
1405                 struct IO_APIC_route_entry entry;
1406
1407                 spin_lock_irqsave(&ioapic_lock, flags);
1408                 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
1409                 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
1410                 spin_unlock_irqrestore(&ioapic_lock, flags);
1411
1412                 printk(KERN_DEBUG " %02x %03X %02X  ",
1413                         i,
1414                         entry.dest.logical.logical_dest,
1415                         entry.dest.physical.physical_dest
1416                 );
1417
1418                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1419                         entry.mask,
1420                         entry.trigger,
1421                         entry.irr,
1422                         entry.polarity,
1423                         entry.delivery_status,
1424                         entry.dest_mode,
1425                         entry.delivery_mode,
1426                         entry.vector
1427                 );
1428         }
1429         }
1430         if (use_pci_vector())
1431                 printk(KERN_INFO "Using vector-based indexing\n");
1432         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1433         for (i = 0; i < NR_IRQS; i++) {
1434                 struct irq_pin_list *entry = irq_2_pin + i;
1435                 if (entry->pin < 0)
1436                         continue;
1437                 if (use_pci_vector() && !platform_legacy_irq(i))
1438                         printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1439                 else
1440                         printk(KERN_DEBUG "IRQ%d ", i);
1441                 for (;;) {
1442                         printk("-> %d:%d", entry->apic, entry->pin);
1443                         if (!entry->next)
1444                                 break;
1445                         entry = irq_2_pin + entry->next;
1446                 }
1447                 printk("\n");
1448         }
1449
1450         printk(KERN_INFO ".................................... done.\n");
1451
1452         return;
1453 }
1454
1455 #if 0
1456
1457 static void print_APIC_bitfield (int base)
1458 {
1459         unsigned int v;
1460         int i, j;
1461
1462         if (apic_verbosity == APIC_QUIET)
1463                 return;
1464
1465         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1466         for (i = 0; i < 8; i++) {
1467                 v = apic_read(base + i*0x10);
1468                 for (j = 0; j < 32; j++) {
1469                         if (v & (1<<j))
1470                                 printk("1");
1471                         else
1472                                 printk("0");
1473                 }
1474                 printk("\n");
1475         }
1476 }
1477
1478 void /*__init*/ print_local_APIC(void * dummy)
1479 {
1480         unsigned int v, ver, maxlvt;
1481
1482         if (apic_verbosity == APIC_QUIET)
1483                 return;
1484
1485         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1486                 smp_processor_id(), hard_smp_processor_id());
1487         v = apic_read(APIC_ID);
1488         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1489         v = apic_read(APIC_LVR);
1490         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1491         ver = GET_APIC_VERSION(v);
1492         maxlvt = get_maxlvt();
1493
1494         v = apic_read(APIC_TASKPRI);
1495         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1496
1497         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1498                 v = apic_read(APIC_ARBPRI);
1499                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1500                         v & APIC_ARBPRI_MASK);
1501                 v = apic_read(APIC_PROCPRI);
1502                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1503         }
1504
1505         v = apic_read(APIC_EOI);
1506         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1507         v = apic_read(APIC_RRR);
1508         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1509         v = apic_read(APIC_LDR);
1510         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1511         v = apic_read(APIC_DFR);
1512         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1513         v = apic_read(APIC_SPIV);
1514         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1515
1516         printk(KERN_DEBUG "... APIC ISR field:\n");
1517         print_APIC_bitfield(APIC_ISR);
1518         printk(KERN_DEBUG "... APIC TMR field:\n");
1519         print_APIC_bitfield(APIC_TMR);
1520         printk(KERN_DEBUG "... APIC IRR field:\n");
1521         print_APIC_bitfield(APIC_IRR);
1522
1523         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1524                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1525                         apic_write(APIC_ESR, 0);
1526                 v = apic_read(APIC_ESR);
1527                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1528         }
1529
1530         v = apic_read(APIC_ICR);
1531         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1532         v = apic_read(APIC_ICR2);
1533         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1534
1535         v = apic_read(APIC_LVTT);
1536         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1537
1538         if (maxlvt > 3) {                       /* PC is LVT#4. */
1539                 v = apic_read(APIC_LVTPC);
1540                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1541         }
1542         v = apic_read(APIC_LVT0);
1543         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1544         v = apic_read(APIC_LVT1);
1545         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1546
1547         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1548                 v = apic_read(APIC_LVTERR);
1549                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1550         }
1551
1552         v = apic_read(APIC_TMICT);
1553         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1554         v = apic_read(APIC_TMCCT);
1555         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1556         v = apic_read(APIC_TDCR);
1557         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1558         printk("\n");
1559 }
1560
1561 void print_all_local_APICs (void)
1562 {
1563         on_each_cpu(print_local_APIC, NULL, 1, 1);
1564 }
1565
1566 void /*__init*/ print_PIC(void)
1567 {
1568         extern spinlock_t i8259A_lock;
1569         unsigned int v;
1570         unsigned long flags;
1571
1572         if (apic_verbosity == APIC_QUIET)
1573                 return;
1574
1575         printk(KERN_DEBUG "\nprinting PIC contents\n");
1576
1577         spin_lock_irqsave(&i8259A_lock, flags);
1578
1579         v = inb(0xa1) << 8 | inb(0x21);
1580         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1581
1582         v = inb(0xa0) << 8 | inb(0x20);
1583         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1584
1585         outb(0x0b,0xa0);
1586         outb(0x0b,0x20);
1587         v = inb(0xa0) << 8 | inb(0x20);
1588         outb(0x0a,0xa0);
1589         outb(0x0a,0x20);
1590
1591         spin_unlock_irqrestore(&i8259A_lock, flags);
1592
1593         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1594
1595         v = inb(0x4d1) << 8 | inb(0x4d0);
1596         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1597 }
1598
1599 #endif  /*  0  */
1600
1601 static void __init enable_IO_APIC(void)
1602 {
1603         union IO_APIC_reg_01 reg_01;
1604         int i;
1605         unsigned long flags;
1606
1607         for (i = 0; i < PIN_MAP_SIZE; i++) {
1608                 irq_2_pin[i].pin = -1;
1609                 irq_2_pin[i].next = 0;
1610         }
1611         if (!pirqs_enabled)
1612                 for (i = 0; i < MAX_PIRQS; i++)
1613                         pirq_entries[i] = -1;
1614
1615         /*
1616          * The number of IO-APIC IRQ registers (== #pins):
1617          */
1618         for (i = 0; i < nr_ioapics; i++) {
1619                 spin_lock_irqsave(&ioapic_lock, flags);
1620                 reg_01.raw = io_apic_read(i, 1);
1621                 spin_unlock_irqrestore(&ioapic_lock, flags);
1622                 nr_ioapic_registers[i] = reg_01.bits.entries+1;
1623         }
1624
1625         /*
1626          * Do not trust the IO-APIC being empty at bootup
1627          */
1628         clear_IO_APIC();
1629 }
1630
1631 /*
1632  * Not an __init, needed by the reboot code
1633  */
1634 void disable_IO_APIC(void)
1635 {
1636         /*
1637          * Clear the IO-APIC before rebooting:
1638          */
1639         clear_IO_APIC();
1640
1641         disconnect_bsp_APIC();
1642 }
1643
1644 /*
1645  * function to set the IO-APIC physical IDs based on the
1646  * values stored in the MPC table.
1647  *
1648  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1649  */
1650
1651 #ifndef CONFIG_X86_NUMAQ
1652 static void __init setup_ioapic_ids_from_mpc(void)
1653 {
1654         union IO_APIC_reg_00 reg_00;
1655         physid_mask_t phys_id_present_map;
1656         int apic;
1657         int i;
1658         unsigned char old_id;
1659         unsigned long flags;
1660
1661         /*
1662          * This is broken; anything with a real cpu count has to
1663          * circumvent this idiocy regardless.
1664          */
1665         phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1666
1667         /*
1668          * Set the IOAPIC ID to the value stored in the MPC table.
1669          */
1670         for (apic = 0; apic < nr_ioapics; apic++) {
1671
1672                 /* Read the register 0 value */
1673                 spin_lock_irqsave(&ioapic_lock, flags);
1674                 reg_00.raw = io_apic_read(apic, 0);
1675                 spin_unlock_irqrestore(&ioapic_lock, flags);
1676
1677                 old_id = mp_ioapics[apic].mpc_apicid;
1678
1679                 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1680                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1681                                 apic, mp_ioapics[apic].mpc_apicid);
1682                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1683                                 reg_00.bits.ID);
1684                         mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1685                 }
1686
1687                 /* Don't check I/O APIC IDs for some xAPIC systems.  They have
1688                  * no meaning without the serial APIC bus. */
1689                 if (NO_IOAPIC_CHECK)
1690                         continue;
1691                 /*
1692                  * Sanity check, is the ID really free? Every APIC in a
1693                  * system must have a unique ID or we get lots of nice
1694                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1695                  */
1696                 if (check_apicid_used(phys_id_present_map,
1697                                         mp_ioapics[apic].mpc_apicid)) {
1698                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1699                                 apic, mp_ioapics[apic].mpc_apicid);
1700                         for (i = 0; i < get_physical_broadcast(); i++)
1701                                 if (!physid_isset(i, phys_id_present_map))
1702                                         break;
1703                         if (i >= get_physical_broadcast())
1704                                 panic("Max APIC ID exceeded!\n");
1705                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1706                                 i);
1707                         physid_set(i, phys_id_present_map);
1708                         mp_ioapics[apic].mpc_apicid = i;
1709                 } else {
1710                         physid_mask_t tmp;
1711                         tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1712                         apic_printk(APIC_VERBOSE, "Setting %d in the "
1713                                         "phys_id_present_map\n",
1714                                         mp_ioapics[apic].mpc_apicid);
1715                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
1716                 }
1717
1718
1719                 /*
1720                  * We need to adjust the IRQ routing table
1721                  * if the ID changed.
1722                  */
1723                 if (old_id != mp_ioapics[apic].mpc_apicid)
1724                         for (i = 0; i < mp_irq_entries; i++)
1725                                 if (mp_irqs[i].mpc_dstapic == old_id)
1726                                         mp_irqs[i].mpc_dstapic
1727                                                 = mp_ioapics[apic].mpc_apicid;
1728
1729                 /*
1730                  * Read the right value from the MPC table and
1731                  * write it into the ID register.
1732                  */
1733                 apic_printk(APIC_VERBOSE, KERN_INFO
1734                         "...changing IO-APIC physical APIC ID to %d ...",
1735                         mp_ioapics[apic].mpc_apicid);
1736
1737                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1738                 spin_lock_irqsave(&ioapic_lock, flags);
1739                 io_apic_write(apic, 0, reg_00.raw);
1740                 spin_unlock_irqrestore(&ioapic_lock, flags);
1741
1742                 /*
1743                  * Sanity check
1744                  */
1745                 spin_lock_irqsave(&ioapic_lock, flags);
1746                 reg_00.raw = io_apic_read(apic, 0);
1747                 spin_unlock_irqrestore(&ioapic_lock, flags);
1748                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1749                         printk("could not set ID!\n");
1750                 else
1751                         apic_printk(APIC_VERBOSE, " ok.\n");
1752         }
1753 }
1754 #else
1755 static void __init setup_ioapic_ids_from_mpc(void) { }
1756 #endif
1757
1758 /*
1759  * There is a nasty bug in some older SMP boards, their mptable lies
1760  * about the timer IRQ. We do the following to work around the situation:
1761  *
1762  *      - timer IRQ defaults to IO-APIC IRQ
1763  *      - if this function detects that timer IRQs are defunct, then we fall
1764  *        back to ISA timer IRQs
1765  */
1766 static int __init timer_irq_works(void)
1767 {
1768         unsigned long t1 = jiffies;
1769
1770         local_irq_enable();
1771         /* Let ten ticks pass... */
1772         mdelay((10 * 1000) / HZ);
1773
1774         /*
1775          * Expect a few ticks at least, to be sure some possible
1776          * glue logic does not lock up after one or two first
1777          * ticks in a non-ExtINT mode.  Also the local APIC
1778          * might have cached one ExtINT interrupt.  Finally, at
1779          * least one tick may be lost due to delays.
1780          */
1781         if (jiffies - t1 > 4)
1782                 return 1;
1783
1784         return 0;
1785 }
1786
1787 /*
1788  * In the SMP+IOAPIC case it might happen that there are an unspecified
1789  * number of pending IRQ events unhandled. These cases are very rare,
1790  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1791  * better to do it this way as thus we do not have to be aware of
1792  * 'pending' interrupts in the IRQ path, except at this point.
1793  */
1794 /*
1795  * Edge triggered needs to resend any interrupt
1796  * that was delayed but this is now handled in the device
1797  * independent code.
1798  */
1799
1800 /*
1801  * Starting up a edge-triggered IO-APIC interrupt is
1802  * nasty - we need to make sure that we get the edge.
1803  * If it is already asserted for some reason, we need
1804  * return 1 to indicate that is was pending.
1805  *
1806  * This is not complete - we should be able to fake
1807  * an edge even if it isn't on the 8259A...
1808  */
1809 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1810 {
1811         int was_pending = 0;
1812         unsigned long flags;
1813
1814         spin_lock_irqsave(&ioapic_lock, flags);
1815         if (irq < 16) {
1816                 disable_8259A_irq(irq);
1817                 if (i8259A_irq_pending(irq))
1818                         was_pending = 1;
1819         }
1820         __unmask_IO_APIC_irq(irq);
1821         spin_unlock_irqrestore(&ioapic_lock, flags);
1822
1823         return was_pending;
1824 }
1825
1826 /*
1827  * Once we have recorded IRQ_PENDING already, we can mask the
1828  * interrupt for real. This prevents IRQ storms from unhandled
1829  * devices.
1830  */
1831 static void ack_edge_ioapic_irq(unsigned int irq)
1832 {
1833         move_irq(irq);
1834         if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1835                                         == (IRQ_PENDING | IRQ_DISABLED))
1836                 mask_IO_APIC_irq(irq);
1837         ack_APIC_irq();
1838 }
1839
1840 /*
1841  * Level triggered interrupts can just be masked,
1842  * and shutting down and starting up the interrupt
1843  * is the same as enabling and disabling them -- except
1844  * with a startup need to return a "was pending" value.
1845  *
1846  * Level triggered interrupts are special because we
1847  * do not touch any IO-APIC register while handling
1848  * them. We ack the APIC in the end-IRQ handler, not
1849  * in the start-IRQ-handler. Protection against reentrance
1850  * from the same interrupt is still provided, both by the
1851  * generic IRQ layer and by the fact that an unacked local
1852  * APIC does not accept IRQs.
1853  */
1854 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1855 {
1856         unmask_IO_APIC_irq(irq);
1857
1858         return 0; /* don't check for pending */
1859 }
1860
1861 static void end_level_ioapic_irq (unsigned int irq)
1862 {
1863         unsigned long v;
1864         int i;
1865
1866         move_irq(irq);
1867 /*
1868  * It appears there is an erratum which affects at least version 0x11
1869  * of I/O APIC (that's the 82093AA and cores integrated into various
1870  * chipsets).  Under certain conditions a level-triggered interrupt is
1871  * erroneously delivered as edge-triggered one but the respective IRR
1872  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1873  * message but it will never arrive and further interrupts are blocked
1874  * from the source.  The exact reason is so far unknown, but the
1875  * phenomenon was observed when two consecutive interrupt requests
1876  * from a given source get delivered to the same CPU and the source is
1877  * temporarily disabled in between.
1878  *
1879  * A workaround is to simulate an EOI message manually.  We achieve it
1880  * by setting the trigger mode to edge and then to level when the edge
1881  * trigger mode gets detected in the TMR of a local APIC for a
1882  * level-triggered interrupt.  We mask the source for the time of the
1883  * operation to prevent an edge-triggered interrupt escaping meanwhile.
1884  * The idea is from Manfred Spraul.  --macro
1885  */
1886         i = IO_APIC_VECTOR(irq);
1887
1888         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1889
1890         ack_APIC_irq();
1891
1892         if (!(v & (1 << (i & 0x1f)))) {
1893                 atomic_inc(&irq_mis_count);
1894                 spin_lock(&ioapic_lock);
1895                 __mask_and_edge_IO_APIC_irq(irq);
1896                 __unmask_and_level_IO_APIC_irq(irq);
1897                 spin_unlock(&ioapic_lock);
1898         }
1899 }
1900
1901 #ifdef CONFIG_PCI_MSI
1902 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1903 {
1904         int irq = vector_to_irq(vector);
1905
1906         return startup_edge_ioapic_irq(irq);
1907 }
1908
1909 static void ack_edge_ioapic_vector(unsigned int vector)
1910 {
1911         int irq = vector_to_irq(vector);
1912
1913         ack_edge_ioapic_irq(irq);
1914 }
1915
1916 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1917 {
1918         int irq = vector_to_irq(vector);
1919
1920         return startup_level_ioapic_irq (irq);
1921 }
1922
1923 static void end_level_ioapic_vector (unsigned int vector)
1924 {
1925         int irq = vector_to_irq(vector);
1926
1927         end_level_ioapic_irq(irq);
1928 }
1929
1930 static void mask_IO_APIC_vector (unsigned int vector)
1931 {
1932         int irq = vector_to_irq(vector);
1933
1934         mask_IO_APIC_irq(irq);
1935 }
1936
1937 static void unmask_IO_APIC_vector (unsigned int vector)
1938 {
1939         int irq = vector_to_irq(vector);
1940
1941         unmask_IO_APIC_irq(irq);
1942 }
1943
1944 static void set_ioapic_affinity_vector (unsigned int vector,
1945                                         cpumask_t cpu_mask)
1946 {
1947         int irq = vector_to_irq(vector);
1948
1949         set_ioapic_affinity_irq(irq, cpu_mask);
1950 }
1951 #endif
1952
1953 /*
1954  * Level and edge triggered IO-APIC interrupts need different handling,
1955  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1956  * handled with the level-triggered descriptor, but that one has slightly
1957  * more overhead. Level-triggered interrupts cannot be handled with the
1958  * edge-triggered handler, without risking IRQ storms and other ugly
1959  * races.
1960  */
1961 static struct hw_interrupt_type ioapic_edge_type = {
1962         .typename       = "IO-APIC-edge",
1963         .startup        = startup_edge_ioapic,
1964         .shutdown       = shutdown_edge_ioapic,
1965         .enable         = enable_edge_ioapic,
1966         .disable        = disable_edge_ioapic,
1967         .ack            = ack_edge_ioapic,
1968         .end            = end_edge_ioapic,
1969         .set_affinity   = set_ioapic_affinity,
1970 };
1971
1972 static struct hw_interrupt_type ioapic_level_type = {
1973         .typename       = "IO-APIC-level",
1974         .startup        = startup_level_ioapic,
1975         .shutdown       = shutdown_level_ioapic,
1976         .enable         = enable_level_ioapic,
1977         .disable        = disable_level_ioapic,
1978         .ack            = mask_and_ack_level_ioapic,
1979         .end            = end_level_ioapic,
1980         .set_affinity   = set_ioapic_affinity,
1981 };
1982
1983 static inline void init_IO_APIC_traps(void)
1984 {
1985         int irq;
1986
1987         /*
1988          * NOTE! The local APIC isn't very good at handling
1989          * multiple interrupts at the same interrupt level.
1990          * As the interrupt level is determined by taking the
1991          * vector number and shifting that right by 4, we
1992          * want to spread these out a bit so that they don't
1993          * all fall in the same interrupt level.
1994          *
1995          * Also, we've got to be careful not to trash gate
1996          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1997          */
1998         for (irq = 0; irq < NR_IRQS ; irq++) {
1999                 int tmp = irq;
2000                 if (use_pci_vector()) {
2001                         if (!platform_legacy_irq(tmp))
2002                                 if ((tmp = vector_to_irq(tmp)) == -1)
2003                                         continue;
2004                 }
2005                 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
2006                         /*
2007                          * Hmm.. We don't have an entry for this,
2008                          * so default to an old-fashioned 8259
2009                          * interrupt if we can..
2010                          */
2011                         if (irq < 16)
2012                                 make_8259A_irq(irq);
2013                         else
2014                                 /* Strange. Oh, well.. */
2015                                 irq_desc[irq].handler = &no_irq_type;
2016                 }
2017         }
2018 }
2019
2020 static void enable_lapic_irq (unsigned int irq)
2021 {
2022         unsigned long v;
2023
2024         v = apic_read(APIC_LVT0);
2025         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2026 }
2027
2028 static void disable_lapic_irq (unsigned int irq)
2029 {
2030         unsigned long v;
2031
2032         v = apic_read(APIC_LVT0);
2033         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2034 }
2035
2036 static void ack_lapic_irq (unsigned int irq)
2037 {
2038         ack_APIC_irq();
2039 }
2040
2041 static void end_lapic_irq (unsigned int i) { /* nothing */ }
2042
2043 static struct hw_interrupt_type lapic_irq_type = {
2044         .typename       = "local-APIC-edge",
2045         .startup        = NULL, /* startup_irq() not used for IRQ0 */
2046         .shutdown       = NULL, /* shutdown_irq() not used for IRQ0 */
2047         .enable         = enable_lapic_irq,
2048         .disable        = disable_lapic_irq,
2049         .ack            = ack_lapic_irq,
2050         .end            = end_lapic_irq
2051 };
2052
2053 static void setup_nmi (void)
2054 {
2055         /*
2056          * Dirty trick to enable the NMI watchdog ...
2057          * We put the 8259A master into AEOI mode and
2058          * unmask on all local APICs LVT0 as NMI.
2059          *
2060          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2061          * is from Maciej W. Rozycki - so we do not have to EOI from
2062          * the NMI handler or the timer interrupt.
2063          */
2064         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2065
2066         on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
2067
2068         apic_printk(APIC_VERBOSE, " done.\n");
2069 }
2070
2071 /*
2072  * This looks a bit hackish but it's about the only one way of sending
2073  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2074  * not support the ExtINT mode, unfortunately.  We need to send these
2075  * cycles as some i82489DX-based boards have glue logic that keeps the
2076  * 8259A interrupt line asserted until INTA.  --macro
2077  */
2078 static inline void unlock_ExtINT_logic(void)
2079 {
2080         int pin, i;
2081         struct IO_APIC_route_entry entry0, entry1;
2082         unsigned char save_control, save_freq_select;
2083         unsigned long flags;
2084
2085         pin = find_isa_irq_pin(8, mp_INT);
2086         if (pin == -1)
2087                 return;
2088
2089         spin_lock_irqsave(&ioapic_lock, flags);
2090         *(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin);
2091         *(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin);
2092         spin_unlock_irqrestore(&ioapic_lock, flags);
2093         clear_IO_APIC_pin(0, pin);
2094
2095         memset(&entry1, 0, sizeof(entry1));
2096
2097         entry1.dest_mode = 0;                   /* physical delivery */
2098         entry1.mask = 0;                        /* unmask IRQ now */
2099         entry1.dest.physical.physical_dest = hard_smp_processor_id();
2100         entry1.delivery_mode = dest_ExtINT;
2101         entry1.polarity = entry0.polarity;
2102         entry1.trigger = 0;
2103         entry1.vector = 0;
2104
2105         spin_lock_irqsave(&ioapic_lock, flags);
2106         io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
2107         io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
2108         spin_unlock_irqrestore(&ioapic_lock, flags);
2109
2110         save_control = CMOS_READ(RTC_CONTROL);
2111         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2112         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2113                    RTC_FREQ_SELECT);
2114         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2115
2116         i = 100;
2117         while (i-- > 0) {
2118                 mdelay(10);
2119                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2120                         i -= 10;
2121         }
2122
2123         CMOS_WRITE(save_control, RTC_CONTROL);
2124         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2125         clear_IO_APIC_pin(0, pin);
2126
2127         spin_lock_irqsave(&ioapic_lock, flags);
2128         io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
2129         io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
2130         spin_unlock_irqrestore(&ioapic_lock, flags);
2131 }
2132
2133 /*
2134  * This code may look a bit paranoid, but it's supposed to cooperate with
2135  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2136  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2137  * fanatically on his truly buggy board.
2138  */
2139 static inline void check_timer(void)
2140 {
2141         int pin1, pin2;
2142         int vector;
2143
2144         /*
2145          * get/set the timer IRQ vector:
2146          */
2147         disable_8259A_irq(0);
2148         vector = assign_irq_vector(0);
2149         set_intr_gate(vector, interrupt[0]);
2150
2151         /*
2152          * Subtle, code in do_timer_interrupt() expects an AEOI
2153          * mode for the 8259A whenever interrupts are routed
2154          * through I/O APICs.  Also IRQ0 has to be enabled in
2155          * the 8259A which implies the virtual wire has to be
2156          * disabled in the local APIC.
2157          */
2158         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2159         init_8259A(1);
2160         timer_ack = 1;
2161         enable_8259A_irq(0);
2162
2163         pin1 = find_isa_irq_pin(0, mp_INT);
2164         pin2 = find_isa_irq_pin(0, mp_ExtINT);
2165
2166         printk(KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2);
2167
2168         if (pin1 != -1) {
2169                 /*
2170                  * Ok, does IRQ0 through the IOAPIC work?
2171                  */
2172                 unmask_IO_APIC_irq(0);
2173                 if (timer_irq_works()) {
2174                         if (nmi_watchdog == NMI_IO_APIC) {
2175                                 disable_8259A_irq(0);
2176                                 setup_nmi();
2177                                 enable_8259A_irq(0);
2178                                 check_nmi_watchdog();
2179                         }
2180                         return;
2181                 }
2182                 clear_IO_APIC_pin(0, pin1);
2183                 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
2184         }
2185
2186         printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2187         if (pin2 != -1) {
2188                 printk("\n..... (found pin %d) ...", pin2);
2189                 /*
2190                  * legacy devices should be connected to IO APIC #0
2191                  */
2192                 setup_ExtINT_IRQ0_pin(pin2, vector);
2193                 if (timer_irq_works()) {
2194                         printk("works.\n");
2195                         if (pin1 != -1)
2196                                 replace_pin_at_irq(0, 0, pin1, 0, pin2);
2197                         else
2198                                 add_pin_to_irq(0, 0, pin2);
2199                         if (nmi_watchdog == NMI_IO_APIC) {
2200                                 setup_nmi();
2201                                 check_nmi_watchdog();
2202                         }
2203                         return;
2204                 }
2205                 /*
2206                  * Cleanup, just in case ...
2207                  */
2208                 clear_IO_APIC_pin(0, pin2);
2209         }
2210         printk(" failed.\n");
2211
2212         if (nmi_watchdog == NMI_IO_APIC) {
2213                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2214                 nmi_watchdog = 0;
2215         }
2216
2217         printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2218
2219         disable_8259A_irq(0);
2220         irq_desc[0].handler = &lapic_irq_type;
2221         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
2222         enable_8259A_irq(0);
2223
2224         if (timer_irq_works()) {
2225                 printk(" works.\n");
2226                 return;
2227         }
2228         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2229         printk(" failed.\n");
2230
2231         printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2232
2233         timer_ack = 0;
2234         init_8259A(0);
2235         make_8259A_irq(0);
2236         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2237
2238         unlock_ExtINT_logic();
2239
2240         if (timer_irq_works()) {
2241                 printk(" works.\n");
2242                 return;
2243         }
2244         printk(" failed :(.\n");
2245         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2246                 "report.  Then try booting with the 'noapic' option");
2247 }
2248
2249 /*
2250  *
2251  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2252  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2253  *   Linux doesn't really care, as it's not actually used
2254  *   for any interrupt handling anyway.
2255  */
2256 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
2257
2258 void __init setup_IO_APIC(void)
2259 {
2260         enable_IO_APIC();
2261
2262         if (acpi_ioapic)
2263                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
2264         else
2265                 io_apic_irqs = ~PIC_IRQS;
2266
2267         printk("ENABLING IO-APIC IRQs\n");
2268
2269         /*
2270          * Set up IO-APIC IRQ routing.
2271          */
2272         if (!acpi_ioapic)
2273                 setup_ioapic_ids_from_mpc();
2274         sync_Arb_IDs();
2275         setup_IO_APIC_irqs();
2276         init_IO_APIC_traps();
2277         check_timer();
2278         if (!acpi_ioapic)
2279                 print_IO_APIC();
2280 }
2281
2282 /*
2283  *      Called after all the initialization is done. If we didnt find any
2284  *      APIC bugs then we can allow the modify fast path
2285  */
2286
2287 static int __init io_apic_bug_finalize(void)
2288 {
2289         if(sis_apic_bug == -1)
2290                 sis_apic_bug = 0;
2291         return 0;
2292 }
2293
2294 late_initcall(io_apic_bug_finalize);
2295
2296 struct sysfs_ioapic_data {
2297         struct sys_device dev;
2298         struct IO_APIC_route_entry entry[0];
2299 };
2300 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2301
2302 static int ioapic_suspend(struct sys_device *dev, u32 state)
2303 {
2304         struct IO_APIC_route_entry *entry;
2305         struct sysfs_ioapic_data *data;
2306         unsigned long flags;
2307         int i;
2308
2309         data = container_of(dev, struct sysfs_ioapic_data, dev);
2310         entry = data->entry;
2311         spin_lock_irqsave(&ioapic_lock, flags);
2312         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2313                 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
2314                 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
2315         }
2316         spin_unlock_irqrestore(&ioapic_lock, flags);
2317
2318         return 0;
2319 }
2320
2321 static int ioapic_resume(struct sys_device *dev)
2322 {
2323         struct IO_APIC_route_entry *entry;
2324         struct sysfs_ioapic_data *data;
2325         unsigned long flags;
2326         union IO_APIC_reg_00 reg_00;
2327         int i;
2328
2329         data = container_of(dev, struct sysfs_ioapic_data, dev);
2330         entry = data->entry;
2331
2332         spin_lock_irqsave(&ioapic_lock, flags);
2333         reg_00.raw = io_apic_read(dev->id, 0);
2334         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2335                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2336                 io_apic_write(dev->id, 0, reg_00.raw);
2337         }
2338         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2339                 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
2340                 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
2341         }
2342         spin_unlock_irqrestore(&ioapic_lock, flags);
2343
2344         return 0;
2345 }
2346
2347 static struct sysdev_class ioapic_sysdev_class = {
2348         set_kset_name("ioapic"),
2349         .suspend = ioapic_suspend,
2350         .resume = ioapic_resume,
2351 };
2352
2353 static int __init ioapic_init_sysfs(void)
2354 {
2355         struct sys_device * dev;
2356         int i, size, error = 0;
2357
2358         error = sysdev_class_register(&ioapic_sysdev_class);
2359         if (error)
2360                 return error;
2361
2362         for (i = 0; i < nr_ioapics; i++ ) {
2363                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2364                         * sizeof(struct IO_APIC_route_entry);
2365                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2366                 if (!mp_ioapic_data[i]) {
2367                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2368                         continue;
2369                 }
2370                 memset(mp_ioapic_data[i], 0, size);
2371                 dev = &mp_ioapic_data[i]->dev;
2372                 dev->id = i;
2373                 dev->cls = &ioapic_sysdev_class;
2374                 error = sysdev_register(dev);
2375                 if (error) {
2376                         kfree(mp_ioapic_data[i]);
2377                         mp_ioapic_data[i] = NULL;
2378                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2379                         continue;
2380                 }
2381         }
2382
2383         return 0;
2384 }
2385
2386 device_initcall(ioapic_init_sysfs);
2387
2388 /* --------------------------------------------------------------------------
2389                           ACPI-based IOAPIC Configuration
2390    -------------------------------------------------------------------------- */
2391
2392 #ifdef CONFIG_ACPI_BOOT
2393
2394 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2395 {
2396         union IO_APIC_reg_00 reg_00;
2397         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2398         physid_mask_t tmp;
2399         unsigned long flags;
2400         int i = 0;
2401
2402         /*
2403          * The P4 platform supports up to 256 APIC IDs on two separate APIC
2404          * buses (one for LAPICs, one for IOAPICs), where predecessors only
2405          * supports up to 16 on one shared APIC bus.
2406          *
2407          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2408          *      advantage of new APIC bus architecture.
2409          */
2410
2411         if (physids_empty(apic_id_map))
2412                 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2413
2414         spin_lock_irqsave(&ioapic_lock, flags);
2415         reg_00.raw = io_apic_read(ioapic, 0);
2416         spin_unlock_irqrestore(&ioapic_lock, flags);
2417
2418         if (apic_id >= get_physical_broadcast()) {
2419                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2420                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
2421                 apic_id = reg_00.bits.ID;
2422         }
2423
2424         /*
2425          * Every APIC in a system must have a unique ID or we get lots of nice
2426          * 'stuck on smp_invalidate_needed IPI wait' messages.
2427          */
2428         if (check_apicid_used(apic_id_map, apic_id)) {
2429
2430                 for (i = 0; i < get_physical_broadcast(); i++) {
2431                         if (!check_apicid_used(apic_id_map, i))
2432                                 break;
2433                 }
2434
2435                 if (i == get_physical_broadcast())
2436                         panic("Max apic_id exceeded!\n");
2437
2438                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2439                         "trying %d\n", ioapic, apic_id, i);
2440
2441                 apic_id = i;
2442         }
2443
2444         tmp = apicid_to_cpu_present(apic_id);
2445         physids_or(apic_id_map, apic_id_map, tmp);
2446
2447         if (reg_00.bits.ID != apic_id) {
2448                 reg_00.bits.ID = apic_id;
2449
2450                 spin_lock_irqsave(&ioapic_lock, flags);
2451                 io_apic_write(ioapic, 0, reg_00.raw);
2452                 reg_00.raw = io_apic_read(ioapic, 0);
2453                 spin_unlock_irqrestore(&ioapic_lock, flags);
2454
2455                 /* Sanity check */
2456                 if (reg_00.bits.ID != apic_id)
2457                         panic("IOAPIC[%d]: Unable change apic_id!\n", ioapic);
2458         }
2459
2460         apic_printk(APIC_VERBOSE, KERN_INFO
2461                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2462
2463         return apic_id;
2464 }
2465
2466
2467 int __init io_apic_get_version (int ioapic)
2468 {
2469         union IO_APIC_reg_01    reg_01;
2470         unsigned long flags;
2471
2472         spin_lock_irqsave(&ioapic_lock, flags);
2473         reg_01.raw = io_apic_read(ioapic, 1);
2474         spin_unlock_irqrestore(&ioapic_lock, flags);
2475
2476         return reg_01.bits.version;
2477 }
2478
2479
2480 int __init io_apic_get_redir_entries (int ioapic)
2481 {
2482         union IO_APIC_reg_01    reg_01;
2483         unsigned long flags;
2484
2485         spin_lock_irqsave(&ioapic_lock, flags);
2486         reg_01.raw = io_apic_read(ioapic, 1);
2487         spin_unlock_irqrestore(&ioapic_lock, flags);
2488
2489         return reg_01.bits.entries;
2490 }
2491
2492
2493 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2494 {
2495         struct IO_APIC_route_entry entry;
2496         unsigned long flags;
2497
2498         if (!IO_APIC_IRQ(irq)) {
2499                 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2500                         ioapic);
2501                 return -EINVAL;
2502         }
2503
2504         /*
2505          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2506          * Note that we mask (disable) IRQs now -- these get enabled when the
2507          * corresponding device driver registers for this IRQ.
2508          */
2509
2510         memset(&entry,0,sizeof(entry));
2511
2512         entry.delivery_mode = INT_DELIVERY_MODE;
2513         entry.dest_mode = INT_DEST_MODE;
2514         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2515         entry.trigger = edge_level;
2516         entry.polarity = active_high_low;
2517         entry.mask  = 1;
2518
2519         /*
2520          * IRQs < 16 are already in the irq_2_pin[] map
2521          */
2522         if (irq >= 16)
2523                 add_pin_to_irq(irq, ioapic, pin);
2524
2525         entry.vector = assign_irq_vector(irq);
2526
2527         apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2528                 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2529                 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2530                 edge_level, active_high_low);
2531
2532         ioapic_register_intr(irq, entry.vector, edge_level);
2533
2534         if (!ioapic && (irq < 16))
2535                 disable_8259A_irq(irq);
2536
2537         spin_lock_irqsave(&ioapic_lock, flags);
2538         io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2539         io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2540         spin_unlock_irqrestore(&ioapic_lock, flags);
2541
2542         return 0;
2543 }
2544
2545 #endif /*CONFIG_ACPI_BOOT*/