arch/i386/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/smp_lock.h>
  29 #include <linux/mc146818rtc.h>
  30 #include <linux/compiler.h>
  31 #include <linux/acpi.h>
  32 #include <linux/module.h>
  33 #include <linux/sysdev.h>
  34
  35 #include <asm/io.h>
  36 #include <asm/smp.h>
  37 #include <asm/desc.h>
  38 #include <asm/timer.h>
  39 #include <asm/i8259.h>
  40 #include <asm/nmi.h>
  41
  42 #include <mach_apic.h>
  43
  44 #include "io_ports.h"
  45
  46 int (*ioapic_renumber_irq)(int ioapic, int irq);
  47 atomic_t irq_mis_count;
  48
  49 /* Where if anywhere is the i8259 connect in external int mode */
  50 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
  51
  52 static DEFINE_SPINLOCK(ioapic_lock);
  53 static DEFINE_SPINLOCK(vector_lock);
  54
  55 int timer_over_8254 __initdata = 1;
  56
  57 /*
  58  *      Is the SiS APIC rmw bug present ?
  59  *      -1 = don't know, 0 = no, 1 = yes
  60  */
  61 int sis_apic_bug = -1;
  62
  63 /*
  64  * # of IRQ routing registers
  65  */
  66 int nr_ioapic_registers[MAX_IO_APICS];
  67
  68 int disable_timer_pin_1 __initdata;
  69
  70 /*
  71  * Rough estimation of how many shared IRQs there are, can
  72  * be changed anytime.
  73  */
  74 #define MAX_PLUS_SHARED_IRQS NR_IRQS
  75 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  76
  77 /*
  78  * This is performance-critical, we want to do it O(1)
  79  *
  80  * the indexing order of this array favors 1:1 mappings
  81  * between pins and IRQs.
  82  */
  83
  84 static struct irq_pin_list {
  85         int apic, pin, next;
  86 } irq_2_pin[PIN_MAP_SIZE];
  87
  88 int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
  89 #ifdef CONFIG_PCI_MSI
  90 #define vector_to_irq(vector)   \
  91         (platform_legacy_irq(vector) ? vector : vector_irq[vector])
  92 #else
  93 #define vector_to_irq(vector)   (vector)
  94 #endif
  95
  96 /*
  97  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
  98  * shared ISA-space IRQs, so we have to support them. We are super
  99  * fast in the common case, and fast for shared ISA-space IRQs.
 100  */
 101 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 102 {
 103         static int first_free_entry = NR_IRQS;
 104         struct irq_pin_list *entry = irq_2_pin + irq;
 105
 106         while (entry->next)
 107                 entry = irq_2_pin + entry->next;
 108
 109         if (entry->pin != -1) {
 110                 entry->next = first_free_entry;
 111                 entry = irq_2_pin + entry->next;
 112                 if (++first_free_entry >= PIN_MAP_SIZE)
 113                         panic("io_apic.c: whoops");
 114         }
 115         entry->apic = apic;
 116         entry->pin = pin;
 117 }
 118
 119 /*
 120  * Reroute an IRQ to a different pin.
 121  */
 122 static void __init replace_pin_at_irq(unsigned int irq,
 123                                       int oldapic, int oldpin,
 124                                       int newapic, int newpin)
 125 {
 126         struct irq_pin_list *entry = irq_2_pin + irq;
 127
 128         while (1) {
 129                 if (entry->apic == oldapic && entry->pin == oldpin) {
 130                         entry->apic = newapic;
 131                         entry->pin = newpin;
 132                 }
 133                 if (!entry->next)
 134                         break;
 135                 entry = irq_2_pin + entry->next;
 136         }
 137 }
 138
 139 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
 140 {
 141         struct irq_pin_list *entry = irq_2_pin + irq;
 142         unsigned int pin, reg;
 143
 144         for (;;) {
 145                 pin = entry->pin;
 146                 if (pin == -1)
 147                         break;
 148                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
 149                 reg &= ~disable;
 150                 reg |= enable;
 151                 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
 152                 if (!entry->next)
 153                         break;
 154                 entry = irq_2_pin + entry->next;
 155         }
 156 }
 157
 158 /* mask = 1 */
 159 static void __mask_IO_APIC_irq (unsigned int irq)
 160 {
 161         __modify_IO_APIC_irq(irq, 0x00010000, 0);
 162 }
 163
 164 /* mask = 0 */
 165 static void __unmask_IO_APIC_irq (unsigned int irq)
 166 {
 167         __modify_IO_APIC_irq(irq, 0, 0x00010000);
 168 }
 169
 170 /* mask = 1, trigger = 0 */
 171 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
 172 {
 173         __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
 174 }
 175
 176 /* mask = 0, trigger = 1 */
 177 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
 178 {
 179         __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
 180 }
 181
 182 static void mask_IO_APIC_irq (unsigned int irq)
 183 {
 184         unsigned long flags;
 185
 186         spin_lock_irqsave(&ioapic_lock, flags);
 187         __mask_IO_APIC_irq(irq);
 188         spin_unlock_irqrestore(&ioapic_lock, flags);
 189 }
 190
 191 static void unmask_IO_APIC_irq (unsigned int irq)
 192 {
 193         unsigned long flags;
 194
 195         spin_lock_irqsave(&ioapic_lock, flags);
 196         __unmask_IO_APIC_irq(irq);
 197         spin_unlock_irqrestore(&ioapic_lock, flags);
 198 }
 199
 200 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 201 {
 202         struct IO_APIC_route_entry entry;
 203         unsigned long flags;
 204
 205         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 206         spin_lock_irqsave(&ioapic_lock, flags);
 207         *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
 208         *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
 209         spin_unlock_irqrestore(&ioapic_lock, flags);
 210         if (entry.delivery_mode == dest_SMI)
 211                 return;
 212
 213         /*
 214          * Disable it in the IO-APIC irq-routing table:
 215          */
 216         memset(&entry, 0, sizeof(entry));
 217         entry.mask = 1;
 218         spin_lock_irqsave(&ioapic_lock, flags);
 219         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
 220         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
 221         spin_unlock_irqrestore(&ioapic_lock, flags);
 222 }
 223
 224 static void clear_IO_APIC (void)
 225 {
 226         int apic, pin;
 227
 228         for (apic = 0; apic < nr_ioapics; apic++)
 229                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 230                         clear_IO_APIC_pin(apic, pin);
 231 }
 232
 233 #ifdef CONFIG_SMP
 234 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
 235 {
 236         unsigned long flags;
 237         int pin;
 238         struct irq_pin_list *entry = irq_2_pin + irq;
 239         unsigned int apicid_value;
 240         cpumask_t tmp;
 241
 242         cpus_and(tmp, cpumask, cpu_online_map);
 243         if (cpus_empty(tmp))
 244                 tmp = TARGET_CPUS;
 245
 246         cpus_and(cpumask, tmp, CPU_MASK_ALL);
 247
 248         apicid_value = cpu_mask_to_apicid(cpumask);
 249         /* Prepare to do the io_apic_write */
 250         apicid_value = apicid_value << 24;
 251         spin_lock_irqsave(&ioapic_lock, flags);
 252         for (;;) {
 253                 pin = entry->pin;
 254                 if (pin == -1)
 255                         break;
 256                 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
 257                 if (!entry->next)
 258                         break;
 259                 entry = irq_2_pin + entry->next;
 260         }
 261         set_irq_info(irq, cpumask);
 262         spin_unlock_irqrestore(&ioapic_lock, flags);
 263 }
 264
 265 #if defined(CONFIG_IRQBALANCE)
 266 # include <asm/processor.h>     /* kernel_thread() */
 267 # include <linux/kernel_stat.h> /* kstat */
 268 # include <linux/slab.h>                /* kmalloc() */
 269 # include <linux/timer.h>       /* time_after() */
 270
 271 #ifdef CONFIG_BALANCED_IRQ_DEBUG
 272 #  define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
 273 #  define Dprintk(x...) do { TDprintk(x); } while (0)
 274 # else
 275 #  define TDprintk(x...)
 276 #  define Dprintk(x...)
 277 # endif
 278
 279 #define IRQBALANCE_CHECK_ARCH -999
 280 #define MAX_BALANCED_IRQ_INTERVAL       (5*HZ)
 281 #define MIN_BALANCED_IRQ_INTERVAL       (HZ/2)
 282 #define BALANCED_IRQ_MORE_DELTA         (HZ/10)
 283 #define BALANCED_IRQ_LESS_DELTA         (HZ)
 284
 285 static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
 286 static int physical_balance __read_mostly;
 287 static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
 288
 289 static struct irq_cpu_info {
 290         unsigned long * last_irq;
 291         unsigned long * irq_delta;
 292         unsigned long irq;
 293 } irq_cpu_data[NR_CPUS];
 294
 295 #define CPU_IRQ(cpu)            (irq_cpu_data[cpu].irq)
 296 #define LAST_CPU_IRQ(cpu,irq)   (irq_cpu_data[cpu].last_irq[irq])
 297 #define IRQ_DELTA(cpu,irq)      (irq_cpu_data[cpu].irq_delta[irq])
 298
 299 #define IDLE_ENOUGH(cpu,now) \
 300         (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
 301
 302 #define IRQ_ALLOWED(cpu, allowed_mask)  cpu_isset(cpu, allowed_mask)
 303
 304 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
 305
 306 static cpumask_t balance_irq_affinity[NR_IRQS] = {
 307         [0 ... NR_IRQS-1] = CPU_MASK_ALL
 308 };
 309
 310 void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
 311 {
 312         balance_irq_affinity[irq] = mask;
 313 }
 314
 315 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
 316                         unsigned long now, int direction)
 317 {
 318         int search_idle = 1;
 319         int cpu = curr_cpu;
 320
 321         goto inside;
 322
 323         do {
 324                 if (unlikely(cpu == curr_cpu))
 325                         search_idle = 0;
 326 inside:
 327                 if (direction == 1) {
 328                         cpu++;
 329                         if (cpu >= NR_CPUS)
 330                                 cpu = 0;
 331                 } else {
 332                         cpu--;
 333                         if (cpu == -1)
 334                                 cpu = NR_CPUS-1;
 335                 }
 336         } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
 337                         (search_idle && !IDLE_ENOUGH(cpu,now)));
 338
 339         return cpu;
 340 }
 341
 342 static inline void balance_irq(int cpu, int irq)
 343 {
 344         unsigned long now = jiffies;
 345         cpumask_t allowed_mask;
 346         unsigned int new_cpu;
 347
 348         if (irqbalance_disabled)
 349                 return;
 350
 351         cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
 352         new_cpu = move(cpu, allowed_mask, now, 1);
 353         if (cpu != new_cpu) {
 354                 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
 355         }
 356 }
 357
 358 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
 359 {
 360         int i, j;
 361         Dprintk("Rotating IRQs among CPUs.\n");
 362         for_each_online_cpu(i) {
 363                 for (j = 0; j < NR_IRQS; j++) {
 364                         if (!irq_desc[j].action)
 365                                 continue;
 366                         /* Is it a significant load ?  */
 367                         if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
 368                                                 useful_load_threshold)
 369                                 continue;
 370                         balance_irq(i, j);
 371                 }
 372         }
 373         balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 374                 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 375         return;
 376 }
 377
 378 static void do_irq_balance(void)
 379 {
 380         int i, j;
 381         unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
 382         unsigned long move_this_load = 0;
 383         int max_loaded = 0, min_loaded = 0;
 384         int load;
 385         unsigned long useful_load_threshold = balanced_irq_interval + 10;
 386         int selected_irq;
 387         int tmp_loaded, first_attempt = 1;
 388         unsigned long tmp_cpu_irq;
 389         unsigned long imbalance = 0;
 390         cpumask_t allowed_mask, target_cpu_mask, tmp;
 391
 392         for_each_possible_cpu(i) {
 393                 int package_index;
 394                 CPU_IRQ(i) = 0;
 395                 if (!cpu_online(i))
 396                         continue;
 397                 package_index = CPU_TO_PACKAGEINDEX(i);
 398                 for (j = 0; j < NR_IRQS; j++) {
 399                         unsigned long value_now, delta;
 400                         /* Is this an active IRQ? */
 401                         if (!irq_desc[j].action)
 402                                 continue;
 403                         if ( package_index == i )
 404                                 IRQ_DELTA(package_index,j) = 0;
 405                         /* Determine the total count per processor per IRQ */
 406                         value_now = (unsigned long) kstat_cpu(i).irqs[j];
 407
 408                         /* Determine the activity per processor per IRQ */
 409                         delta = value_now - LAST_CPU_IRQ(i,j);
 410
 411                         /* Update last_cpu_irq[][] for the next time */
 412                         LAST_CPU_IRQ(i,j) = value_now;
 413
 414                         /* Ignore IRQs whose rate is less than the clock */
 415                         if (delta < useful_load_threshold)
 416                                 continue;
 417                         /* update the load for the processor or package total */
 418                         IRQ_DELTA(package_index,j) += delta;
 419
 420                         /* Keep track of the higher numbered sibling as well */
 421                         if (i != package_index)
 422                                 CPU_IRQ(i) += delta;
 423                         /*
 424                          * We have sibling A and sibling B in the package
 425                          *
 426                          * cpu_irq[A] = load for cpu A + load for cpu B
 427                          * cpu_irq[B] = load for cpu B
 428                          */
 429                         CPU_IRQ(package_index) += delta;
 430                 }
 431         }
 432         /* Find the least loaded processor package */
 433         for_each_online_cpu(i) {
 434                 if (i != CPU_TO_PACKAGEINDEX(i))
 435                         continue;
 436                 if (min_cpu_irq > CPU_IRQ(i)) {
 437                         min_cpu_irq = CPU_IRQ(i);
 438                         min_loaded = i;
 439                 }
 440         }
 441         max_cpu_irq = ULONG_MAX;
 442
 443 tryanothercpu:
 444         /* Look for heaviest loaded processor.
 445          * We may come back to get the next heaviest loaded processor.
 446          * Skip processors with trivial loads.
 447          */
 448         tmp_cpu_irq = 0;
 449         tmp_loaded = -1;
 450         for_each_online_cpu(i) {
 451                 if (i != CPU_TO_PACKAGEINDEX(i))
 452                         continue;
 453                 if (max_cpu_irq <= CPU_IRQ(i))
 454                         continue;
 455                 if (tmp_cpu_irq < CPU_IRQ(i)) {
 456                         tmp_cpu_irq = CPU_IRQ(i);
 457                         tmp_loaded = i;
 458                 }
 459         }
 460
 461         if (tmp_loaded == -1) {
 462          /* In the case of small number of heavy interrupt sources,
 463           * loading some of the cpus too much. We use Ingo's original
 464           * approach to rotate them around.
 465           */
 466                 if (!first_attempt && imbalance >= useful_load_threshold) {
 467                         rotate_irqs_among_cpus(useful_load_threshold);
 468                         return;
 469                 }
 470                 goto not_worth_the_effort;
 471         }
 472
 473         first_attempt = 0;              /* heaviest search */
 474         max_cpu_irq = tmp_cpu_irq;      /* load */
 475         max_loaded = tmp_loaded;        /* processor */
 476         imbalance = (max_cpu_irq - min_cpu_irq) / 2;
 477
 478         Dprintk("max_loaded cpu = %d\n", max_loaded);
 479         Dprintk("min_loaded cpu = %d\n", min_loaded);
 480         Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
 481         Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
 482         Dprintk("load imbalance = %lu\n", imbalance);
 483
 484         /* if imbalance is less than approx 10% of max load, then
 485          * observe diminishing returns action. - quit
 486          */
 487         if (imbalance < (max_cpu_irq >> 3)) {
 488                 Dprintk("Imbalance too trivial\n");
 489                 goto not_worth_the_effort;
 490         }
 491
 492 tryanotherirq:
 493         /* if we select an IRQ to move that can't go where we want, then
 494          * see if there is another one to try.
 495          */
 496         move_this_load = 0;
 497         selected_irq = -1;
 498         for (j = 0; j < NR_IRQS; j++) {
 499                 /* Is this an active IRQ? */
 500                 if (!irq_desc[j].action)
 501                         continue;
 502                 if (imbalance <= IRQ_DELTA(max_loaded,j))
 503                         continue;
 504                 /* Try to find the IRQ that is closest to the imbalance
 505                  * without going over.
 506                  */
 507                 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
 508                         move_this_load = IRQ_DELTA(max_loaded,j);
 509                         selected_irq = j;
 510                 }
 511         }
 512         if (selected_irq == -1) {
 513                 goto tryanothercpu;
 514         }
 515
 516         imbalance = move_this_load;
 517
 518         /* For physical_balance case, we accumlated both load
 519          * values in the one of the siblings cpu_irq[],
 520          * to use the same code for physical and logical processors
 521          * as much as possible.
 522          *
 523          * NOTE: the cpu_irq[] array holds the sum of the load for
 524          * sibling A and sibling B in the slot for the lowest numbered
 525          * sibling (A), _AND_ the load for sibling B in the slot for
 526          * the higher numbered sibling.
 527          *
 528          * We seek the least loaded sibling by making the comparison
 529          * (A+B)/2 vs B
 530          */
 531         load = CPU_IRQ(min_loaded) >> 1;
 532         for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
 533                 if (load > CPU_IRQ(j)) {
 534                         /* This won't change cpu_sibling_map[min_loaded] */
 535                         load = CPU_IRQ(j);
 536                         min_loaded = j;
 537                 }
 538         }
 539
 540         cpus_and(allowed_mask,
 541                 cpu_online_map,
 542                 balance_irq_affinity[selected_irq]);
 543         target_cpu_mask = cpumask_of_cpu(min_loaded);
 544         cpus_and(tmp, target_cpu_mask, allowed_mask);
 545
 546         if (!cpus_empty(tmp)) {
 547
 548                 Dprintk("irq = %d moved to cpu = %d\n",
 549                                 selected_irq, min_loaded);
 550                 /* mark for change destination */
 551                 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
 552
 553                 /* Since we made a change, come back sooner to
 554                  * check for more variation.
 555                  */
 556                 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 557                         balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 558                 return;
 559         }
 560         goto tryanotherirq;
 561
 562 not_worth_the_effort:
 563         /*
 564          * if we did not find an IRQ to move, then adjust the time interval
 565          * upward
 566          */
 567         balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
 568                 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
 569         Dprintk("IRQ worth rotating not found\n");
 570         return;
 571 }
 572
 573 static int balanced_irq(void *unused)
 574 {
 575         int i;
 576         unsigned long prev_balance_time = jiffies;
 577         long time_remaining = balanced_irq_interval;
 578
 579         daemonize("kirqd");
 580
 581         /* push everything to CPU 0 to give us a starting point.  */
 582         for (i = 0 ; i < NR_IRQS ; i++) {
 583                 irq_desc[i].pending_mask = cpumask_of_cpu(0);
 584                 set_pending_irq(i, cpumask_of_cpu(0));
 585         }
 586
 587         for ( ; ; ) {
 588                 time_remaining = schedule_timeout_interruptible(time_remaining);
 589                 try_to_freeze();
 590                 if (time_after(jiffies,
 591                                 prev_balance_time+balanced_irq_interval)) {
 592                         preempt_disable();
 593                         do_irq_balance();
 594                         prev_balance_time = jiffies;
 595                         time_remaining = balanced_irq_interval;
 596                         preempt_enable();
 597                 }
 598         }
 599         return 0;
 600 }
 601
 602 static int __init balanced_irq_init(void)
 603 {
 604         int i;
 605         struct cpuinfo_x86 *c;
 606         cpumask_t tmp;
 607
 608         cpus_shift_right(tmp, cpu_online_map, 2);
 609         c = &boot_cpu_data;
 610         /* When not overwritten by the command line ask subarchitecture. */
 611         if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
 612                 irqbalance_disabled = NO_BALANCE_IRQ;
 613         if (irqbalance_disabled)
 614                 return 0;
 615
 616          /* disable irqbalance completely if there is only one processor online */
 617         if (num_online_cpus() < 2) {
 618                 irqbalance_disabled = 1;
 619                 return 0;
 620         }
 621         /*
 622          * Enable physical balance only if more than 1 physical processor
 623          * is present
 624          */
 625         if (smp_num_siblings > 1 && !cpus_empty(tmp))
 626                 physical_balance = 1;
 627
 628         for_each_online_cpu(i) {
 629                 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 630                 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 631                 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
 632                         printk(KERN_ERR "balanced_irq_init: out of memory");
 633                         goto failed;
 634                 }
 635                 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
 636                 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
 637         }
 638
 639         printk(KERN_INFO "Starting balanced_irq\n");
 640         if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0)
 641                 return 0;
 642         else
 643                 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
 644 failed:
 645         for_each_possible_cpu(i) {
 646                 kfree(irq_cpu_data[i].irq_delta);
 647                 irq_cpu_data[i].irq_delta = NULL;
 648                 kfree(irq_cpu_data[i].last_irq);
 649                 irq_cpu_data[i].last_irq = NULL;
 650         }
 651         return 0;
 652 }
 653
 654 int __init irqbalance_disable(char *str)
 655 {
 656         irqbalance_disabled = 1;
 657         return 1;
 658 }
 659
 660 __setup("noirqbalance", irqbalance_disable);
 661
 662 late_initcall(balanced_irq_init);
 663 #endif /* CONFIG_IRQBALANCE */
 664 #endif /* CONFIG_SMP */
 665
 666 #ifndef CONFIG_SMP
 667 void fastcall send_IPI_self(int vector)
 668 {
 669         unsigned int cfg;
 670
 671         /*
 672          * Wait for idle.
 673          */
 674         apic_wait_icr_idle();
 675         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
 676         /*
 677          * Send the IPI. The write to APIC_ICR fires this off.
 678          */
 679         apic_write_around(APIC_ICR, cfg);
 680 }
 681 #endif /* !CONFIG_SMP */
 682
 683
 684 /*
 685  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 686  * specific CPU-side IRQs.
 687  */
 688
 689 #define MAX_PIRQS 8
 690 static int pirq_entries [MAX_PIRQS];
 691 static int pirqs_enabled;
 692 int skip_ioapic_setup;
 693
 694 static int __init ioapic_setup(char *str)
 695 {
 696         skip_ioapic_setup = 1;
 697         return 1;
 698 }
 699
 700 __setup("noapic", ioapic_setup);
 701
 702 static int __init ioapic_pirq_setup(char *str)
 703 {
 704         int i, max;
 705         int ints[MAX_PIRQS+1];
 706
 707         get_options(str, ARRAY_SIZE(ints), ints);
 708
 709         for (i = 0; i < MAX_PIRQS; i++)
 710                 pirq_entries[i] = -1;
 711
 712         pirqs_enabled = 1;
 713         apic_printk(APIC_VERBOSE, KERN_INFO
 714                         "PIRQ redirection, working around broken MP-BIOS.\n");
 715         max = MAX_PIRQS;
 716         if (ints[0] < MAX_PIRQS)
 717                 max = ints[0];
 718
 719         for (i = 0; i < max; i++) {
 720                 apic_printk(APIC_VERBOSE, KERN_DEBUG
 721                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 722                 /*
 723                  * PIRQs are mapped upside down, usually.
 724                  */
 725                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 726         }
 727         return 1;
 728 }
 729
 730 __setup("pirq=", ioapic_pirq_setup);
 731
 732 /*
 733  * Find the IRQ entry number of a certain pin.
 734  */
 735 static int find_irq_entry(int apic, int pin, int type)
 736 {
 737         int i;
 738
 739         for (i = 0; i < mp_irq_entries; i++)
 740                 if (mp_irqs[i].mpc_irqtype == type &&
 741                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 742                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 743                     mp_irqs[i].mpc_dstirq == pin)
 744                         return i;
 745
 746         return -1;
 747 }
 748
 749 /*
 750  * Find the pin to which IRQ[irq] (ISA) is connected
 751  */
 752 static int __init find_isa_irq_pin(int irq, int type)
 753 {
 754         int i;
 755
 756         for (i = 0; i < mp_irq_entries; i++) {
 757                 int lbus = mp_irqs[i].mpc_srcbus;
 758
 759                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 760                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 761                      mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
 762                      mp_bus_id_to_type[lbus] == MP_BUS_NEC98
 763                     ) &&
 764                     (mp_irqs[i].mpc_irqtype == type) &&
 765                     (mp_irqs[i].mpc_srcbusirq == irq))
 766
 767                         return mp_irqs[i].mpc_dstirq;
 768         }
 769         return -1;
 770 }
 771
 772 static int __init find_isa_irq_apic(int irq, int type)
 773 {
 774         int i;
 775
 776         for (i = 0; i < mp_irq_entries; i++) {
 777                 int lbus = mp_irqs[i].mpc_srcbus;
 778
 779                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 780                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 781                      mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
 782                      mp_bus_id_to_type[lbus] == MP_BUS_NEC98
 783                     ) &&
 784                     (mp_irqs[i].mpc_irqtype == type) &&
 785                     (mp_irqs[i].mpc_srcbusirq == irq))
 786                         break;
 787         }
 788         if (i < mp_irq_entries) {
 789                 int apic;
 790                 for(apic = 0; apic < nr_ioapics; apic++) {
 791                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
 792                                 return apic;
 793                 }
 794         }
 795
 796         return -1;
 797 }
 798
 799 /*
 800  * Find a specific PCI IRQ entry.
 801  * Not an __init, possibly needed by modules
 802  */
 803 static int pin_2_irq(int idx, int apic, int pin);
 804
 805 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 806 {
 807         int apic, i, best_guess = -1;
 808
 809         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
 810                 "slot:%d, pin:%d.\n", bus, slot, pin);
 811         if (mp_bus_id_to_pci_bus[bus] == -1) {
 812                 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 813                 return -1;
 814         }
 815         for (i = 0; i < mp_irq_entries; i++) {
 816                 int lbus = mp_irqs[i].mpc_srcbus;
 817
 818                 for (apic = 0; apic < nr_ioapics; apic++)
 819                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 820                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 821                                 break;
 822
 823                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
 824                     !mp_irqs[i].mpc_irqtype &&
 825                     (bus == lbus) &&
 826                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 827                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 828
 829                         if (!(apic || IO_APIC_IRQ(irq)))
 830                                 continue;
 831
 832                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 833                                 return irq;
 834                         /*
 835                          * Use the first all-but-pin matching entry as a
 836                          * best-guess fuzzy result for broken mptables.
 837                          */
 838                         if (best_guess < 0)
 839                                 best_guess = irq;
 840                 }
 841         }
 842         return best_guess;
 843 }
 844 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
 845
 846 /*
 847  * This function currently is only a helper for the i386 smp boot process where
 848  * we need to reprogram the ioredtbls to cater for the cpus which have come online
 849  * so mask in all cases should simply be TARGET_CPUS
 850  */
 851 #ifdef CONFIG_SMP
 852 void __init setup_ioapic_dest(void)
 853 {
 854         int pin, ioapic, irq, irq_entry;
 855
 856         if (skip_ioapic_setup == 1)
 857                 return;
 858
 859         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
 860                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
 861                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
 862                         if (irq_entry == -1)
 863                                 continue;
 864                         irq = pin_2_irq(irq_entry, ioapic, pin);
 865                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
 866                 }
 867
 868         }
 869 }
 870 #endif
 871
 872 /*
 873  * EISA Edge/Level control register, ELCR
 874  */
 875 static int EISA_ELCR(unsigned int irq)
 876 {
 877         if (irq < 16) {
 878                 unsigned int port = 0x4d0 + (irq >> 3);
 879                 return (inb(port) >> (irq & 7)) & 1;
 880         }
 881         apic_printk(APIC_VERBOSE, KERN_INFO
 882                         "Broken MPtable reports ISA irq %d\n", irq);
 883         return 0;
 884 }
 885
 886 /* EISA interrupts are always polarity zero and can be edge or level
 887  * trigger depending on the ELCR value.  If an interrupt is listed as
 888  * EISA conforming in the MP table, that means its trigger type must
 889  * be read in from the ELCR */
 890
 891 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
 892 #define default_EISA_polarity(idx)      (0)
 893
 894 /* ISA interrupts are always polarity zero edge triggered,
 895  * when listed as conforming in the MP table. */
 896
 897 #define default_ISA_trigger(idx)        (0)
 898 #define default_ISA_polarity(idx)       (0)
 899
 900 /* PCI interrupts are always polarity one level triggered,
 901  * when listed as conforming in the MP table. */
 902
 903 #define default_PCI_trigger(idx)        (1)
 904 #define default_PCI_polarity(idx)       (1)
 905
 906 /* MCA interrupts are always polarity zero level triggered,
 907  * when listed as conforming in the MP table. */
 908
 909 #define default_MCA_trigger(idx)        (1)
 910 #define default_MCA_polarity(idx)       (0)
 911
 912 /* NEC98 interrupts are always polarity zero edge triggered,
 913  * when listed as conforming in the MP table. */
 914
 915 #define default_NEC98_trigger(idx)     (0)
 916 #define default_NEC98_polarity(idx)    (0)
 917
 918 static int __init MPBIOS_polarity(int idx)
 919 {
 920         int bus = mp_irqs[idx].mpc_srcbus;
 921         int polarity;
 922
 923         /*
 924          * Determine IRQ line polarity (high active or low active):
 925          */
 926         switch (mp_irqs[idx].mpc_irqflag & 3)
 927         {
 928                 case 0: /* conforms, ie. bus-type dependent polarity */
 929                 {
 930                         switch (mp_bus_id_to_type[bus])
 931                         {
 932                                 case MP_BUS_ISA: /* ISA pin */
 933                                 {
 934                                         polarity = default_ISA_polarity(idx);
 935                                         break;
 936                                 }
 937                                 case MP_BUS_EISA: /* EISA pin */
 938                                 {
 939                                         polarity = default_EISA_polarity(idx);
 940                                         break;
 941                                 }
 942                                 case MP_BUS_PCI: /* PCI pin */
 943                                 {
 944                                         polarity = default_PCI_polarity(idx);
 945                                         break;
 946                                 }
 947                                 case MP_BUS_MCA: /* MCA pin */
 948                                 {
 949                                         polarity = default_MCA_polarity(idx);
 950                                         break;
 951                                 }
 952                                 case MP_BUS_NEC98: /* NEC 98 pin */
 953                                 {
 954                                         polarity = default_NEC98_polarity(idx);
 955                                         break;
 956                                 }
 957                                 default:
 958                                 {
 959                                         printk(KERN_WARNING "broken BIOS!!\n");
 960                                         polarity = 1;
 961                                         break;
 962                                 }
 963                         }
 964                         break;
 965                 }
 966                 case 1: /* high active */
 967                 {
 968                         polarity = 0;
 969                         break;
 970                 }
 971                 case 2: /* reserved */
 972                 {
 973                         printk(KERN_WARNING "broken BIOS!!\n");
 974                         polarity = 1;
 975                         break;
 976                 }
 977                 case 3: /* low active */
 978                 {
 979                         polarity = 1;
 980                         break;
 981                 }
 982                 default: /* invalid */
 983                 {
 984                         printk(KERN_WARNING "broken BIOS!!\n");
 985                         polarity = 1;
 986                         break;
 987                 }
 988         }
 989         return polarity;
 990 }
 991
 992 static int MPBIOS_trigger(int idx)
 993 {
 994         int bus = mp_irqs[idx].mpc_srcbus;
 995         int trigger;
 996
 997         /*
 998          * Determine IRQ trigger mode (edge or level sensitive):
 999          */
1000         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
1001         {
1002                 case 0: /* conforms, ie. bus-type dependent */
1003                 {
1004                         switch (mp_bus_id_to_type[bus])
1005                         {
1006                                 case MP_BUS_ISA: /* ISA pin */
1007                                 {
1008                                         trigger = default_ISA_trigger(idx);
1009                                         break;
1010                                 }
1011                                 case MP_BUS_EISA: /* EISA pin */
1012                                 {
1013                                         trigger = default_EISA_trigger(idx);
1014                                         break;
1015                                 }
1016                                 case MP_BUS_PCI: /* PCI pin */
1017                                 {
1018                                         trigger = default_PCI_trigger(idx);
1019                                         break;
1020                                 }
1021                                 case MP_BUS_MCA: /* MCA pin */
1022                                 {
1023                                         trigger = default_MCA_trigger(idx);
1024                                         break;
1025                                 }
1026                                 case MP_BUS_NEC98: /* NEC 98 pin */
1027                                 {
1028                                         trigger = default_NEC98_trigger(idx);
1029                                         break;
1030                                 }
1031                                 default:
1032                                 {
1033                                         printk(KERN_WARNING "broken BIOS!!\n");
1034                                         trigger = 1;
1035                                         break;
1036                                 }
1037                         }
1038                         break;
1039                 }
1040                 case 1: /* edge */
1041                 {
1042                         trigger = 0;
1043                         break;
1044                 }
1045                 case 2: /* reserved */
1046                 {
1047                         printk(KERN_WARNING "broken BIOS!!\n");
1048                         trigger = 1;
1049                         break;
1050                 }
1051                 case 3: /* level */
1052                 {
1053                         trigger = 1;
1054                         break;
1055                 }
1056                 default: /* invalid */
1057                 {
1058                         printk(KERN_WARNING "broken BIOS!!\n");
1059                         trigger = 0;
1060                         break;
1061                 }
1062         }
1063         return trigger;
1064 }
1065
1066 static inline int irq_polarity(int idx)
1067 {
1068         return MPBIOS_polarity(idx);
1069 }
1070
1071 static inline int irq_trigger(int idx)
1072 {
1073         return MPBIOS_trigger(idx);
1074 }
1075
1076 static int pin_2_irq(int idx, int apic, int pin)
1077 {
1078         int irq, i;
1079         int bus = mp_irqs[idx].mpc_srcbus;
1080
1081         /*
1082          * Debugging check, we are in big trouble if this message pops up!
1083          */
1084         if (mp_irqs[idx].mpc_dstirq != pin)
1085                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1086
1087         switch (mp_bus_id_to_type[bus])
1088         {
1089                 case MP_BUS_ISA: /* ISA pin */
1090                 case MP_BUS_EISA:
1091                 case MP_BUS_MCA:
1092                 case MP_BUS_NEC98:
1093                 {
1094                         irq = mp_irqs[idx].mpc_srcbusirq;
1095                         break;
1096                 }
1097                 case MP_BUS_PCI: /* PCI pin */
1098                 {
1099                         /*
1100                          * PCI IRQs are mapped in order
1101                          */
1102                         i = irq = 0;
1103                         while (i < apic)
1104                                 irq += nr_ioapic_registers[i++];
1105                         irq += pin;
1106
1107                         /*
1108                          * For MPS mode, so far only needed by ES7000 platform
1109                          */
1110                         if (ioapic_renumber_irq)
1111                                 irq = ioapic_renumber_irq(apic, irq);
1112
1113                         break;
1114                 }
1115                 default:
1116                 {
1117                         printk(KERN_ERR "unknown bus type %d.\n",bus);
1118                         irq = 0;
1119                         break;
1120                 }
1121         }
1122
1123         /*
1124          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1125          */
1126         if ((pin >= 16) && (pin <= 23)) {
1127                 if (pirq_entries[pin-16] != -1) {
1128                         if (!pirq_entries[pin-16]) {
1129                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1130                                                 "disabling PIRQ%d\n", pin-16);
1131                         } else {
1132                                 irq = pirq_entries[pin-16];
1133                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1134                                                 "using PIRQ%d -> IRQ %d\n",
1135                                                 pin-16, irq);
1136                         }
1137                 }
1138         }
1139         return irq;
1140 }
1141
1142 static inline int IO_APIC_irq_trigger(int irq)
1143 {
1144         int apic, idx, pin;
1145
1146         for (apic = 0; apic < nr_ioapics; apic++) {
1147                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1148                         idx = find_irq_entry(apic,pin,mp_INT);
1149                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1150                                 return irq_trigger(idx);
1151                 }
1152         }
1153         /*
1154          * nonexistent IRQs are edge default
1155          */
1156         return 0;
1157 }
1158
1159 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1160 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1161
1162 int assign_irq_vector(int irq)
1163 {
1164         static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
1165         unsigned long flags;
1166         int vector;
1167
1168         BUG_ON(irq != AUTO_ASSIGN && (unsigned)irq >= NR_IRQ_VECTORS);
1169
1170         spin_lock_irqsave(&vector_lock, flags);
1171
1172         if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0) {
1173                 spin_unlock_irqrestore(&vector_lock, flags);
1174                 return IO_APIC_VECTOR(irq);
1175         }
1176 next:
1177         current_vector += 8;
1178         if (current_vector == SYSCALL_VECTOR)
1179                 goto next;
1180
1181         if (current_vector >= FIRST_SYSTEM_VECTOR) {
1182                 offset++;
1183                 if (!(offset%8)) {
1184                         spin_unlock_irqrestore(&vector_lock, flags);
1185                         return -ENOSPC;
1186                 }
1187                 current_vector = FIRST_DEVICE_VECTOR + offset;
1188         }
1189
1190         vector = current_vector;
1191         vector_irq[vector] = irq;
1192         if (irq != AUTO_ASSIGN)
1193                 IO_APIC_VECTOR(irq) = vector;
1194
1195         spin_unlock_irqrestore(&vector_lock, flags);
1196
1197         return vector;
1198 }
1199
1200 static struct hw_interrupt_type ioapic_level_type;
1201 static struct hw_interrupt_type ioapic_edge_type;
1202
1203 #define IOAPIC_AUTO     -1
1204 #define IOAPIC_EDGE     0
1205 #define IOAPIC_LEVEL    1
1206
1207 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1208 {
1209         unsigned idx;
1210
1211         idx = use_pci_vector() && !platform_legacy_irq(irq) ? vector : irq;
1212
1213         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1214                         trigger == IOAPIC_LEVEL)
1215                 irq_desc[idx].chip = &ioapic_level_type;
1216         else
1217                 irq_desc[idx].chip = &ioapic_edge_type;
1218         set_intr_gate(vector, interrupt[idx]);
1219 }
1220
1221 static void __init setup_IO_APIC_irqs(void)
1222 {
1223         struct IO_APIC_route_entry entry;
1224         int apic, pin, idx, irq, first_notcon = 1, vector;
1225         unsigned long flags;
1226
1227         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1228
1229         for (apic = 0; apic < nr_ioapics; apic++) {
1230         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1231
1232                 /*
1233                  * add it to the IO-APIC irq-routing table:
1234                  */
1235                 memset(&entry,0,sizeof(entry));
1236
1237                 entry.delivery_mode = INT_DELIVERY_MODE;
1238                 entry.dest_mode = INT_DEST_MODE;
1239                 entry.mask = 0;                         /* enable IRQ */
1240                 entry.dest.logical.logical_dest =
1241                                         cpu_mask_to_apicid(TARGET_CPUS);
1242
1243                 idx = find_irq_entry(apic,pin,mp_INT);
1244                 if (idx == -1) {
1245                         if (first_notcon) {
1246                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1247                                                 " IO-APIC (apicid-pin) %d-%d",
1248                                                 mp_ioapics[apic].mpc_apicid,
1249                                                 pin);
1250                                 first_notcon = 0;
1251                         } else
1252                                 apic_printk(APIC_VERBOSE, ", %d-%d",
1253                                         mp_ioapics[apic].mpc_apicid, pin);
1254                         continue;
1255                 }
1256
1257                 entry.trigger = irq_trigger(idx);
1258                 entry.polarity = irq_polarity(idx);
1259
1260                 if (irq_trigger(idx)) {
1261                         entry.trigger = 1;
1262                         entry.mask = 1;
1263                 }
1264
1265                 irq = pin_2_irq(idx, apic, pin);
1266                 /*
1267                  * skip adding the timer int on secondary nodes, which causes
1268                  * a small but painful rift in the time-space continuum
1269                  */
1270                 if (multi_timer_check(apic, irq))
1271                         continue;
1272                 else
1273                         add_pin_to_irq(irq, apic, pin);
1274
1275                 if (!apic && !IO_APIC_IRQ(irq))
1276                         continue;
1277
1278                 if (IO_APIC_IRQ(irq)) {
1279                         vector = assign_irq_vector(irq);
1280                         entry.vector = vector;
1281                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1282
1283                         if (!apic && (irq < 16))
1284                                 disable_8259A_irq(irq);
1285                 }
1286                 spin_lock_irqsave(&ioapic_lock, flags);
1287                 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1288                 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1289                 set_native_irq_info(irq, TARGET_CPUS);
1290                 spin_unlock_irqrestore(&ioapic_lock, flags);
1291         }
1292         }
1293
1294         if (!first_notcon)
1295                 apic_printk(APIC_VERBOSE, " not connected.\n");
1296 }
1297
1298 /*
1299  * Set up the 8259A-master output pin:
1300  */
1301 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1302 {
1303         struct IO_APIC_route_entry entry;
1304         unsigned long flags;
1305
1306         memset(&entry,0,sizeof(entry));
1307
1308         disable_8259A_irq(0);
1309
1310         /* mask LVT0 */
1311         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1312
1313         /*
1314          * We use logical delivery to get the timer IRQ
1315          * to the first CPU.
1316          */
1317         entry.dest_mode = INT_DEST_MODE;
1318         entry.mask = 0;                                 /* unmask IRQ now */
1319         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1320         entry.delivery_mode = INT_DELIVERY_MODE;
1321         entry.polarity = 0;
1322         entry.trigger = 0;
1323         entry.vector = vector;
1324
1325         /*
1326          * The timer IRQ doesn't have to know that behind the
1327          * scene we have a 8259A-master in AEOI mode ...
1328          */
1329         irq_desc[0].chip = &ioapic_edge_type;
1330
1331         /*
1332          * Add it to the IO-APIC irq-routing table:
1333          */
1334         spin_lock_irqsave(&ioapic_lock, flags);
1335         io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1336         io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1337         spin_unlock_irqrestore(&ioapic_lock, flags);
1338
1339         enable_8259A_irq(0);
1340 }
1341
1342 static inline void UNEXPECTED_IO_APIC(void)
1343 {
1344 }
1345
1346 void __init print_IO_APIC(void)
1347 {
1348         int apic, i;
1349         union IO_APIC_reg_00 reg_00;
1350         union IO_APIC_reg_01 reg_01;
1351         union IO_APIC_reg_02 reg_02;
1352         union IO_APIC_reg_03 reg_03;
1353         unsigned long flags;
1354
1355         if (apic_verbosity == APIC_QUIET)
1356                 return;
1357
1358         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1359         for (i = 0; i < nr_ioapics; i++)
1360                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1361                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1362
1363         /*
1364          * We are a bit conservative about what we expect.  We have to
1365          * know about every hardware change ASAP.
1366          */
1367         printk(KERN_INFO "testing the IO APIC.......................\n");
1368
1369         for (apic = 0; apic < nr_ioapics; apic++) {
1370
1371         spin_lock_irqsave(&ioapic_lock, flags);
1372         reg_00.raw = io_apic_read(apic, 0);
1373         reg_01.raw = io_apic_read(apic, 1);
1374         if (reg_01.bits.version >= 0x10)
1375                 reg_02.raw = io_apic_read(apic, 2);
1376         if (reg_01.bits.version >= 0x20)
1377                 reg_03.raw = io_apic_read(apic, 3);
1378         spin_unlock_irqrestore(&ioapic_lock, flags);
1379
1380         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1381         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1382         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1383         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1384         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1385         if (reg_00.bits.ID >= get_physical_broadcast())
1386                 UNEXPECTED_IO_APIC();
1387         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1388                 UNEXPECTED_IO_APIC();
1389
1390         printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1391         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1392         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1393                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1394                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1395                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1396                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1397                 (reg_01.bits.entries != 0x2E) &&
1398                 (reg_01.bits.entries != 0x3F)
1399         )
1400                 UNEXPECTED_IO_APIC();
1401
1402         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1403         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1404         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1405                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1406                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1407                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1408                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
1409         )
1410                 UNEXPECTED_IO_APIC();
1411         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1412                 UNEXPECTED_IO_APIC();
1413
1414         /*
1415          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1416          * but the value of reg_02 is read as the previous read register
1417          * value, so ignore it if reg_02 == reg_01.
1418          */
1419         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1420                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1421                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1422                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1423                         UNEXPECTED_IO_APIC();
1424         }
1425
1426         /*
1427          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1428          * or reg_03, but the value of reg_0[23] is read as the previous read
1429          * register value, so ignore it if reg_03 == reg_0[12].
1430          */
1431         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1432             reg_03.raw != reg_01.raw) {
1433                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1434                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1435                 if (reg_03.bits.__reserved_1)
1436                         UNEXPECTED_IO_APIC();
1437         }
1438
1439         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1440
1441         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1442                           " Stat Dest Deli Vect:   \n");
1443
1444         for (i = 0; i <= reg_01.bits.entries; i++) {
1445                 struct IO_APIC_route_entry entry;
1446
1447                 spin_lock_irqsave(&ioapic_lock, flags);
1448                 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
1449                 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
1450                 spin_unlock_irqrestore(&ioapic_lock, flags);
1451
1452                 printk(KERN_DEBUG " %02x %03X %02X  ",
1453                         i,
1454                         entry.dest.logical.logical_dest,
1455                         entry.dest.physical.physical_dest
1456                 );
1457
1458                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1459                         entry.mask,
1460                         entry.trigger,
1461                         entry.irr,
1462                         entry.polarity,
1463                         entry.delivery_status,
1464                         entry.dest_mode,
1465                         entry.delivery_mode,
1466                         entry.vector
1467                 );
1468         }
1469         }
1470         if (use_pci_vector())
1471                 printk(KERN_INFO "Using vector-based indexing\n");
1472         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1473         for (i = 0; i < NR_IRQS; i++) {
1474                 struct irq_pin_list *entry = irq_2_pin + i;
1475                 if (entry->pin < 0)
1476                         continue;
1477                 if (use_pci_vector() && !platform_legacy_irq(i))
1478                         printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1479                 else
1480                         printk(KERN_DEBUG "IRQ%d ", i);
1481                 for (;;) {
1482                         printk("-> %d:%d", entry->apic, entry->pin);
1483                         if (!entry->next)
1484                                 break;
1485                         entry = irq_2_pin + entry->next;
1486                 }
1487                 printk("\n");
1488         }
1489
1490         printk(KERN_INFO ".................................... done.\n");
1491
1492         return;
1493 }
1494
1495 #if 0
1496
1497 static void print_APIC_bitfield (int base)
1498 {
1499         unsigned int v;
1500         int i, j;
1501
1502         if (apic_verbosity == APIC_QUIET)
1503                 return;
1504
1505         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1506         for (i = 0; i < 8; i++) {
1507                 v = apic_read(base + i*0x10);
1508                 for (j = 0; j < 32; j++) {
1509                         if (v & (1<<j))
1510                                 printk("1");
1511                         else
1512                                 printk("0");
1513                 }
1514                 printk("\n");
1515         }
1516 }
1517
1518 void /*__init*/ print_local_APIC(void * dummy)
1519 {
1520         unsigned int v, ver, maxlvt;
1521
1522         if (apic_verbosity == APIC_QUIET)
1523                 return;
1524
1525         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1526                 smp_processor_id(), hard_smp_processor_id());
1527         v = apic_read(APIC_ID);
1528         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1529         v = apic_read(APIC_LVR);
1530         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1531         ver = GET_APIC_VERSION(v);
1532         maxlvt = get_maxlvt();
1533
1534         v = apic_read(APIC_TASKPRI);
1535         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1536
1537         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1538                 v = apic_read(APIC_ARBPRI);
1539                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1540                         v & APIC_ARBPRI_MASK);
1541                 v = apic_read(APIC_PROCPRI);
1542                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1543         }
1544
1545         v = apic_read(APIC_EOI);
1546         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1547         v = apic_read(APIC_RRR);
1548         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1549         v = apic_read(APIC_LDR);
1550         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1551         v = apic_read(APIC_DFR);
1552         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1553         v = apic_read(APIC_SPIV);
1554         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1555
1556         printk(KERN_DEBUG "... APIC ISR field:\n");
1557         print_APIC_bitfield(APIC_ISR);
1558         printk(KERN_DEBUG "... APIC TMR field:\n");
1559         print_APIC_bitfield(APIC_TMR);
1560         printk(KERN_DEBUG "... APIC IRR field:\n");
1561         print_APIC_bitfield(APIC_IRR);
1562
1563         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1564                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1565                         apic_write(APIC_ESR, 0);
1566                 v = apic_read(APIC_ESR);
1567                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1568         }
1569
1570         v = apic_read(APIC_ICR);
1571         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1572         v = apic_read(APIC_ICR2);
1573         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1574
1575         v = apic_read(APIC_LVTT);
1576         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1577
1578         if (maxlvt > 3) {                       /* PC is LVT#4. */
1579                 v = apic_read(APIC_LVTPC);
1580                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1581         }
1582         v = apic_read(APIC_LVT0);
1583         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1584         v = apic_read(APIC_LVT1);
1585         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1586
1587         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1588                 v = apic_read(APIC_LVTERR);
1589                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1590         }
1591
1592         v = apic_read(APIC_TMICT);
1593         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1594         v = apic_read(APIC_TMCCT);
1595         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1596         v = apic_read(APIC_TDCR);
1597         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1598         printk("\n");
1599 }
1600
1601 void print_all_local_APICs (void)
1602 {
1603         on_each_cpu(print_local_APIC, NULL, 1, 1);
1604 }
1605
1606 void /*__init*/ print_PIC(void)
1607 {
1608         unsigned int v;
1609         unsigned long flags;
1610
1611         if (apic_verbosity == APIC_QUIET)
1612                 return;
1613
1614         printk(KERN_DEBUG "\nprinting PIC contents\n");
1615
1616         spin_lock_irqsave(&i8259A_lock, flags);
1617
1618         v = inb(0xa1) << 8 | inb(0x21);
1619         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1620
1621         v = inb(0xa0) << 8 | inb(0x20);
1622         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1623
1624         outb(0x0b,0xa0);
1625         outb(0x0b,0x20);
1626         v = inb(0xa0) << 8 | inb(0x20);
1627         outb(0x0a,0xa0);
1628         outb(0x0a,0x20);
1629
1630         spin_unlock_irqrestore(&i8259A_lock, flags);
1631
1632         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1633
1634         v = inb(0x4d1) << 8 | inb(0x4d0);
1635         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1636 }
1637
1638 #endif  /*  0  */
1639
1640 static void __init enable_IO_APIC(void)
1641 {
1642         union IO_APIC_reg_01 reg_01;
1643         int i8259_apic, i8259_pin;
1644         int i, apic;
1645         unsigned long flags;
1646
1647         for (i = 0; i < PIN_MAP_SIZE; i++) {
1648                 irq_2_pin[i].pin = -1;
1649                 irq_2_pin[i].next = 0;
1650         }
1651         if (!pirqs_enabled)
1652                 for (i = 0; i < MAX_PIRQS; i++)
1653                         pirq_entries[i] = -1;
1654
1655         /*
1656          * The number of IO-APIC IRQ registers (== #pins):
1657          */
1658         for (apic = 0; apic < nr_ioapics; apic++) {
1659                 spin_lock_irqsave(&ioapic_lock, flags);
1660                 reg_01.raw = io_apic_read(apic, 1);
1661                 spin_unlock_irqrestore(&ioapic_lock, flags);
1662                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1663         }
1664         for(apic = 0; apic < nr_ioapics; apic++) {
1665                 int pin;
1666                 /* See if any of the pins is in ExtINT mode */
1667                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1668                         struct IO_APIC_route_entry entry;
1669                         spin_lock_irqsave(&ioapic_lock, flags);
1670                         *(((int *)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1671                         *(((int *)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1672                         spin_unlock_irqrestore(&ioapic_lock, flags);
1673
1674
1675                         /* If the interrupt line is enabled and in ExtInt mode
1676                          * I have found the pin where the i8259 is connected.
1677                          */
1678                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1679                                 ioapic_i8259.apic = apic;
1680                                 ioapic_i8259.pin  = pin;
1681                                 goto found_i8259;
1682                         }
1683                 }
1684         }
1685  found_i8259:
1686         /* Look to see what if the MP table has reported the ExtINT */
1687         /* If we could not find the appropriate pin by looking at the ioapic
1688          * the i8259 probably is not connected the ioapic but give the
1689          * mptable a chance anyway.
1690          */
1691         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1692         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1693         /* Trust the MP table if nothing is setup in the hardware */
1694         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1695                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1696                 ioapic_i8259.pin  = i8259_pin;
1697                 ioapic_i8259.apic = i8259_apic;
1698         }
1699         /* Complain if the MP table and the hardware disagree */
1700         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1701                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1702         {
1703                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1704         }
1705
1706         /*
1707          * Do not trust the IO-APIC being empty at bootup
1708          */
1709         clear_IO_APIC();
1710 }
1711
1712 /*
1713  * Not an __init, needed by the reboot code
1714  */
1715 void disable_IO_APIC(void)
1716 {
1717         /*
1718          * Clear the IO-APIC before rebooting:
1719          */
1720         clear_IO_APIC();
1721
1722         /*
1723          * If the i8259 is routed through an IOAPIC
1724          * Put that IOAPIC in virtual wire mode
1725          * so legacy interrupts can be delivered.
1726          */
1727         if (ioapic_i8259.pin != -1) {
1728                 struct IO_APIC_route_entry entry;
1729                 unsigned long flags;
1730
1731                 memset(&entry, 0, sizeof(entry));
1732                 entry.mask            = 0; /* Enabled */
1733                 entry.trigger         = 0; /* Edge */
1734                 entry.irr             = 0;
1735                 entry.polarity        = 0; /* High */
1736                 entry.delivery_status = 0;
1737                 entry.dest_mode       = 0; /* Physical */
1738                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1739                 entry.vector          = 0;
1740                 entry.dest.physical.physical_dest =
1741                                         GET_APIC_ID(apic_read(APIC_ID));
1742
1743                 /*
1744                  * Add it to the IO-APIC irq-routing table:
1745                  */
1746                 spin_lock_irqsave(&ioapic_lock, flags);
1747                 io_apic_write(ioapic_i8259.apic, 0x11+2*ioapic_i8259.pin,
1748                         *(((int *)&entry)+1));
1749                 io_apic_write(ioapic_i8259.apic, 0x10+2*ioapic_i8259.pin,
1750                         *(((int *)&entry)+0));
1751                 spin_unlock_irqrestore(&ioapic_lock, flags);
1752         }
1753         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1754 }
1755
1756 /*
1757  * function to set the IO-APIC physical IDs based on the
1758  * values stored in the MPC table.
1759  *
1760  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1761  */
1762
1763 #ifndef CONFIG_X86_NUMAQ
1764 static void __init setup_ioapic_ids_from_mpc(void)
1765 {
1766         union IO_APIC_reg_00 reg_00;
1767         physid_mask_t phys_id_present_map;
1768         int apic;
1769         int i;
1770         unsigned char old_id;
1771         unsigned long flags;
1772
1773         /*
1774          * Don't check I/O APIC IDs for xAPIC systems.  They have
1775          * no meaning without the serial APIC bus.
1776          */
1777         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1778                 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1779                 return;
1780         /*
1781          * This is broken; anything with a real cpu count has to
1782          * circumvent this idiocy regardless.
1783          */
1784         phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1785
1786         /*
1787          * Set the IOAPIC ID to the value stored in the MPC table.
1788          */
1789         for (apic = 0; apic < nr_ioapics; apic++) {
1790
1791                 /* Read the register 0 value */
1792                 spin_lock_irqsave(&ioapic_lock, flags);
1793                 reg_00.raw = io_apic_read(apic, 0);
1794                 spin_unlock_irqrestore(&ioapic_lock, flags);
1795
1796                 old_id = mp_ioapics[apic].mpc_apicid;
1797
1798                 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1799                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1800                                 apic, mp_ioapics[apic].mpc_apicid);
1801                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1802                                 reg_00.bits.ID);
1803                         mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1804                 }
1805
1806                 /*
1807                  * Sanity check, is the ID really free? Every APIC in a
1808                  * system must have a unique ID or we get lots of nice
1809                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1810                  */
1811                 if (check_apicid_used(phys_id_present_map,
1812                                         mp_ioapics[apic].mpc_apicid)) {
1813                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1814                                 apic, mp_ioapics[apic].mpc_apicid);
1815                         for (i = 0; i < get_physical_broadcast(); i++)
1816                                 if (!physid_isset(i, phys_id_present_map))
1817                                         break;
1818                         if (i >= get_physical_broadcast())
1819                                 panic("Max APIC ID exceeded!\n");
1820                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1821                                 i);
1822                         physid_set(i, phys_id_present_map);
1823                         mp_ioapics[apic].mpc_apicid = i;
1824                 } else {
1825                         physid_mask_t tmp;
1826                         tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1827                         apic_printk(APIC_VERBOSE, "Setting %d in the "
1828                                         "phys_id_present_map\n",
1829                                         mp_ioapics[apic].mpc_apicid);
1830                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
1831                 }
1832
1833
1834                 /*
1835                  * We need to adjust the IRQ routing table
1836                  * if the ID changed.
1837                  */
1838                 if (old_id != mp_ioapics[apic].mpc_apicid)
1839                         for (i = 0; i < mp_irq_entries; i++)
1840                                 if (mp_irqs[i].mpc_dstapic == old_id)
1841                                         mp_irqs[i].mpc_dstapic
1842                                                 = mp_ioapics[apic].mpc_apicid;
1843
1844                 /*
1845                  * Read the right value from the MPC table and
1846                  * write it into the ID register.
1847                  */
1848                 apic_printk(APIC_VERBOSE, KERN_INFO
1849                         "...changing IO-APIC physical APIC ID to %d ...",
1850                         mp_ioapics[apic].mpc_apicid);
1851
1852                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1853                 spin_lock_irqsave(&ioapic_lock, flags);
1854                 io_apic_write(apic, 0, reg_00.raw);
1855                 spin_unlock_irqrestore(&ioapic_lock, flags);
1856
1857                 /*
1858                  * Sanity check
1859                  */
1860                 spin_lock_irqsave(&ioapic_lock, flags);
1861                 reg_00.raw = io_apic_read(apic, 0);
1862                 spin_unlock_irqrestore(&ioapic_lock, flags);
1863                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1864                         printk("could not set ID!\n");
1865                 else
1866                         apic_printk(APIC_VERBOSE, " ok.\n");
1867         }
1868 }
1869 #else
1870 static void __init setup_ioapic_ids_from_mpc(void) { }
1871 #endif
1872
1873 /*
1874  * There is a nasty bug in some older SMP boards, their mptable lies
1875  * about the timer IRQ. We do the following to work around the situation:
1876  *
1877  *      - timer IRQ defaults to IO-APIC IRQ
1878  *      - if this function detects that timer IRQs are defunct, then we fall
1879  *        back to ISA timer IRQs
1880  */
1881 static int __init timer_irq_works(void)
1882 {
1883         unsigned long t1 = jiffies;
1884
1885         local_irq_enable();
1886         /* Let ten ticks pass... */
1887         mdelay((10 * 1000) / HZ);
1888
1889         /*
1890          * Expect a few ticks at least, to be sure some possible
1891          * glue logic does not lock up after one or two first
1892          * ticks in a non-ExtINT mode.  Also the local APIC
1893          * might have cached one ExtINT interrupt.  Finally, at
1894          * least one tick may be lost due to delays.
1895          */
1896         if (jiffies - t1 > 4)
1897                 return 1;
1898
1899         return 0;
1900 }
1901
1902 /*
1903  * In the SMP+IOAPIC case it might happen that there are an unspecified
1904  * number of pending IRQ events unhandled. These cases are very rare,
1905  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1906  * better to do it this way as thus we do not have to be aware of
1907  * 'pending' interrupts in the IRQ path, except at this point.
1908  */
1909 /*
1910  * Edge triggered needs to resend any interrupt
1911  * that was delayed but this is now handled in the device
1912  * independent code.
1913  */
1914
1915 /*
1916  * Starting up a edge-triggered IO-APIC interrupt is
1917  * nasty - we need to make sure that we get the edge.
1918  * If it is already asserted for some reason, we need
1919  * return 1 to indicate that is was pending.
1920  *
1921  * This is not complete - we should be able to fake
1922  * an edge even if it isn't on the 8259A...
1923  */
1924 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1925 {
1926         int was_pending = 0;
1927         unsigned long flags;
1928
1929         spin_lock_irqsave(&ioapic_lock, flags);
1930         if (irq < 16) {
1931                 disable_8259A_irq(irq);
1932                 if (i8259A_irq_pending(irq))
1933                         was_pending = 1;
1934         }
1935         __unmask_IO_APIC_irq(irq);
1936         spin_unlock_irqrestore(&ioapic_lock, flags);
1937
1938         return was_pending;
1939 }
1940
1941 /*
1942  * Once we have recorded IRQ_PENDING already, we can mask the
1943  * interrupt for real. This prevents IRQ storms from unhandled
1944  * devices.
1945  */
1946 static void ack_edge_ioapic_irq(unsigned int irq)
1947 {
1948         move_irq(irq);
1949         if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1950                                         == (IRQ_PENDING | IRQ_DISABLED))
1951                 mask_IO_APIC_irq(irq);
1952         ack_APIC_irq();
1953 }
1954
1955 /*
1956  * Level triggered interrupts can just be masked,
1957  * and shutting down and starting up the interrupt
1958  * is the same as enabling and disabling them -- except
1959  * with a startup need to return a "was pending" value.
1960  *
1961  * Level triggered interrupts are special because we
1962  * do not touch any IO-APIC register while handling
1963  * them. We ack the APIC in the end-IRQ handler, not
1964  * in the start-IRQ-handler. Protection against reentrance
1965  * from the same interrupt is still provided, both by the
1966  * generic IRQ layer and by the fact that an unacked local
1967  * APIC does not accept IRQs.
1968  */
1969 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1970 {
1971         unmask_IO_APIC_irq(irq);
1972
1973         return 0; /* don't check for pending */
1974 }
1975
1976 static void end_level_ioapic_irq (unsigned int irq)
1977 {
1978         unsigned long v;
1979         int i;
1980
1981         move_irq(irq);
1982 /*
1983  * It appears there is an erratum which affects at least version 0x11
1984  * of I/O APIC (that's the 82093AA and cores integrated into various
1985  * chipsets).  Under certain conditions a level-triggered interrupt is
1986  * erroneously delivered as edge-triggered one but the respective IRR
1987  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1988  * message but it will never arrive and further interrupts are blocked
1989  * from the source.  The exact reason is so far unknown, but the
1990  * phenomenon was observed when two consecutive interrupt requests
1991  * from a given source get delivered to the same CPU and the source is
1992  * temporarily disabled in between.
1993  *
1994  * A workaround is to simulate an EOI message manually.  We achieve it
1995  * by setting the trigger mode to edge and then to level when the edge
1996  * trigger mode gets detected in the TMR of a local APIC for a
1997  * level-triggered interrupt.  We mask the source for the time of the
1998  * operation to prevent an edge-triggered interrupt escaping meanwhile.
1999  * The idea is from Manfred Spraul.  --macro
2000  */
2001         i = IO_APIC_VECTOR(irq);
2002
2003         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2004
2005         ack_APIC_irq();
2006
2007         if (!(v & (1 << (i & 0x1f)))) {
2008                 atomic_inc(&irq_mis_count);
2009                 spin_lock(&ioapic_lock);
2010                 __mask_and_edge_IO_APIC_irq(irq);
2011                 __unmask_and_level_IO_APIC_irq(irq);
2012                 spin_unlock(&ioapic_lock);
2013         }
2014 }
2015
2016 #ifdef CONFIG_PCI_MSI
2017 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
2018 {
2019         int irq = vector_to_irq(vector);
2020
2021         return startup_edge_ioapic_irq(irq);
2022 }
2023
2024 static void ack_edge_ioapic_vector(unsigned int vector)
2025 {
2026         int irq = vector_to_irq(vector);
2027
2028         move_native_irq(vector);
2029         ack_edge_ioapic_irq(irq);
2030 }
2031
2032 static unsigned int startup_level_ioapic_vector (unsigned int vector)
2033 {
2034         int irq = vector_to_irq(vector);
2035
2036         return startup_level_ioapic_irq (irq);
2037 }
2038
2039 static void end_level_ioapic_vector (unsigned int vector)
2040 {
2041         int irq = vector_to_irq(vector);
2042
2043         move_native_irq(vector);
2044         end_level_ioapic_irq(irq);
2045 }
2046
2047 static void mask_IO_APIC_vector (unsigned int vector)
2048 {
2049         int irq = vector_to_irq(vector);
2050
2051         mask_IO_APIC_irq(irq);
2052 }
2053
2054 static void unmask_IO_APIC_vector (unsigned int vector)
2055 {
2056         int irq = vector_to_irq(vector);
2057
2058         unmask_IO_APIC_irq(irq);
2059 }
2060
2061 #ifdef CONFIG_SMP
2062 static void set_ioapic_affinity_vector (unsigned int vector,
2063                                         cpumask_t cpu_mask)
2064 {
2065         int irq = vector_to_irq(vector);
2066
2067         set_native_irq_info(vector, cpu_mask);
2068         set_ioapic_affinity_irq(irq, cpu_mask);
2069 }
2070 #endif
2071 #endif
2072
2073 static int ioapic_retrigger(unsigned int irq)
2074 {
2075         send_IPI_self(IO_APIC_VECTOR(irq));
2076
2077         return 1;
2078 }
2079
2080 /*
2081  * Level and edge triggered IO-APIC interrupts need different handling,
2082  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2083  * handled with the level-triggered descriptor, but that one has slightly
2084  * more overhead. Level-triggered interrupts cannot be handled with the
2085  * edge-triggered handler, without risking IRQ storms and other ugly
2086  * races.
2087  */
2088 static struct hw_interrupt_type ioapic_edge_type __read_mostly = {
2089         .typename       = "IO-APIC-edge",
2090         .startup        = startup_edge_ioapic,
2091         .shutdown       = shutdown_edge_ioapic,
2092         .enable         = enable_edge_ioapic,
2093         .disable        = disable_edge_ioapic,
2094         .ack            = ack_edge_ioapic,
2095         .end            = end_edge_ioapic,
2096 #ifdef CONFIG_SMP
2097         .set_affinity   = set_ioapic_affinity,
2098 #endif
2099         .retrigger      = ioapic_retrigger,
2100 };
2101
2102 static struct hw_interrupt_type ioapic_level_type __read_mostly = {
2103         .typename       = "IO-APIC-level",
2104         .startup        = startup_level_ioapic,
2105         .shutdown       = shutdown_level_ioapic,
2106         .enable         = enable_level_ioapic,
2107         .disable        = disable_level_ioapic,
2108         .ack            = mask_and_ack_level_ioapic,
2109         .end            = end_level_ioapic,
2110 #ifdef CONFIG_SMP
2111         .set_affinity   = set_ioapic_affinity,
2112 #endif
2113         .retrigger      = ioapic_retrigger,
2114 };
2115
2116 static inline void init_IO_APIC_traps(void)
2117 {
2118         int irq;
2119
2120         /*
2121          * NOTE! The local APIC isn't very good at handling
2122          * multiple interrupts at the same interrupt level.
2123          * As the interrupt level is determined by taking the
2124          * vector number and shifting that right by 4, we
2125          * want to spread these out a bit so that they don't
2126          * all fall in the same interrupt level.
2127          *
2128          * Also, we've got to be careful not to trash gate
2129          * 0x80, because int 0x80 is hm, kind of importantish. ;)
2130          */
2131         for (irq = 0; irq < NR_IRQS ; irq++) {
2132                 int tmp = irq;
2133                 if (use_pci_vector()) {
2134                         if (!platform_legacy_irq(tmp))
2135                                 if ((tmp = vector_to_irq(tmp)) == -1)
2136                                         continue;
2137                 }
2138                 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
2139                         /*
2140                          * Hmm.. We don't have an entry for this,
2141                          * so default to an old-fashioned 8259
2142                          * interrupt if we can..
2143                          */
2144                         if (irq < 16)
2145                                 make_8259A_irq(irq);
2146                         else
2147                                 /* Strange. Oh, well.. */
2148                                 irq_desc[irq].chip = &no_irq_type;
2149                 }
2150         }
2151 }
2152
2153 static void enable_lapic_irq (unsigned int irq)
2154 {
2155         unsigned long v;
2156
2157         v = apic_read(APIC_LVT0);
2158         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2159 }
2160
2161 static void disable_lapic_irq (unsigned int irq)
2162 {
2163         unsigned long v;
2164
2165         v = apic_read(APIC_LVT0);
2166         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2167 }
2168
2169 static void ack_lapic_irq (unsigned int irq)
2170 {
2171         ack_APIC_irq();
2172 }
2173
2174 static void end_lapic_irq (unsigned int i) { /* nothing */ }
2175
2176 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
2177         .typename       = "local-APIC-edge",
2178         .startup        = NULL, /* startup_irq() not used for IRQ0 */
2179         .shutdown       = NULL, /* shutdown_irq() not used for IRQ0 */
2180         .enable         = enable_lapic_irq,
2181         .disable        = disable_lapic_irq,
2182         .ack            = ack_lapic_irq,
2183         .end            = end_lapic_irq
2184 };
2185
2186 static void setup_nmi (void)
2187 {
2188         /*
2189          * Dirty trick to enable the NMI watchdog ...
2190          * We put the 8259A master into AEOI mode and
2191          * unmask on all local APICs LVT0 as NMI.
2192          *
2193          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2194          * is from Maciej W. Rozycki - so we do not have to EOI from
2195          * the NMI handler or the timer interrupt.
2196          */
2197         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2198
2199         on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
2200
2201         apic_printk(APIC_VERBOSE, " done.\n");
2202 }
2203
2204 /*
2205  * This looks a bit hackish but it's about the only one way of sending
2206  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2207  * not support the ExtINT mode, unfortunately.  We need to send these
2208  * cycles as some i82489DX-based boards have glue logic that keeps the
2209  * 8259A interrupt line asserted until INTA.  --macro
2210  */
2211 static inline void unlock_ExtINT_logic(void)
2212 {
2213         int apic, pin, i;
2214         struct IO_APIC_route_entry entry0, entry1;
2215         unsigned char save_control, save_freq_select;
2216         unsigned long flags;
2217
2218         pin  = find_isa_irq_pin(8, mp_INT);
2219         apic = find_isa_irq_apic(8, mp_INT);
2220         if (pin == -1)
2221                 return;
2222
2223         spin_lock_irqsave(&ioapic_lock, flags);
2224         *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
2225         *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
2226         spin_unlock_irqrestore(&ioapic_lock, flags);
2227         clear_IO_APIC_pin(apic, pin);
2228
2229         memset(&entry1, 0, sizeof(entry1));
2230
2231         entry1.dest_mode = 0;                   /* physical delivery */
2232         entry1.mask = 0;                        /* unmask IRQ now */
2233         entry1.dest.physical.physical_dest = hard_smp_processor_id();
2234         entry1.delivery_mode = dest_ExtINT;
2235         entry1.polarity = entry0.polarity;
2236         entry1.trigger = 0;
2237         entry1.vector = 0;
2238
2239         spin_lock_irqsave(&ioapic_lock, flags);
2240         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
2241         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
2242         spin_unlock_irqrestore(&ioapic_lock, flags);
2243
2244         save_control = CMOS_READ(RTC_CONTROL);
2245         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2246         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2247                    RTC_FREQ_SELECT);
2248         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2249
2250         i = 100;
2251         while (i-- > 0) {
2252                 mdelay(10);
2253                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2254                         i -= 10;
2255         }
2256
2257         CMOS_WRITE(save_control, RTC_CONTROL);
2258         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2259         clear_IO_APIC_pin(apic, pin);
2260
2261         spin_lock_irqsave(&ioapic_lock, flags);
2262         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
2263         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
2264         spin_unlock_irqrestore(&ioapic_lock, flags);
2265 }
2266
2267 int timer_uses_ioapic_pin_0;
2268
2269 /*
2270  * This code may look a bit paranoid, but it's supposed to cooperate with
2271  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2272  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2273  * fanatically on his truly buggy board.
2274  */
2275 static inline void check_timer(void)
2276 {
2277         int apic1, pin1, apic2, pin2;
2278         int vector;
2279
2280         /*
2281          * get/set the timer IRQ vector:
2282          */
2283         disable_8259A_irq(0);
2284         vector = assign_irq_vector(0);
2285         set_intr_gate(vector, interrupt[0]);
2286
2287         /*
2288          * Subtle, code in do_timer_interrupt() expects an AEOI
2289          * mode for the 8259A whenever interrupts are routed
2290          * through I/O APICs.  Also IRQ0 has to be enabled in
2291          * the 8259A which implies the virtual wire has to be
2292          * disabled in the local APIC.
2293          */
2294         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2295         init_8259A(1);
2296         timer_ack = 1;
2297         if (timer_over_8254 > 0)
2298                 enable_8259A_irq(0);
2299
2300         pin1  = find_isa_irq_pin(0, mp_INT);
2301         apic1 = find_isa_irq_apic(0, mp_INT);
2302         pin2  = ioapic_i8259.pin;
2303         apic2 = ioapic_i8259.apic;
2304
2305         if (pin1 == 0)
2306                 timer_uses_ioapic_pin_0 = 1;
2307
2308         printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2309                 vector, apic1, pin1, apic2, pin2);
2310
2311         if (pin1 != -1) {
2312                 /*
2313                  * Ok, does IRQ0 through the IOAPIC work?
2314                  */
2315                 unmask_IO_APIC_irq(0);
2316                 if (timer_irq_works()) {
2317                         if (nmi_watchdog == NMI_IO_APIC) {
2318                                 disable_8259A_irq(0);
2319                                 setup_nmi();
2320                                 enable_8259A_irq(0);
2321                         }
2322                         if (disable_timer_pin_1 > 0)
2323                                 clear_IO_APIC_pin(0, pin1);
2324                         return;
2325                 }
2326                 clear_IO_APIC_pin(apic1, pin1);
2327                 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2328                                 "IO-APIC\n");
2329         }
2330
2331         printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2332         if (pin2 != -1) {
2333                 printk("\n..... (found pin %d) ...", pin2);
2334                 /*
2335                  * legacy devices should be connected to IO APIC #0
2336                  */
2337                 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
2338                 if (timer_irq_works()) {
2339                         printk("works.\n");
2340                         if (pin1 != -1)
2341                                 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2342                         else
2343                                 add_pin_to_irq(0, apic2, pin2);
2344                         if (nmi_watchdog == NMI_IO_APIC) {
2345                                 setup_nmi();
2346                         }
2347                         return;
2348                 }
2349                 /*
2350                  * Cleanup, just in case ...
2351                  */
2352                 clear_IO_APIC_pin(apic2, pin2);
2353         }
2354         printk(" failed.\n");
2355
2356         if (nmi_watchdog == NMI_IO_APIC) {
2357                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2358                 nmi_watchdog = 0;
2359         }
2360
2361         printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2362
2363         disable_8259A_irq(0);
2364         irq_desc[0].chip = &lapic_irq_type;
2365         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
2366         enable_8259A_irq(0);
2367
2368         if (timer_irq_works()) {
2369                 printk(" works.\n");
2370                 return;
2371         }
2372         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2373         printk(" failed.\n");
2374
2375         printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2376
2377         timer_ack = 0;
2378         init_8259A(0);
2379         make_8259A_irq(0);
2380         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2381
2382         unlock_ExtINT_logic();
2383
2384         if (timer_irq_works()) {
2385                 printk(" works.\n");
2386                 return;
2387         }
2388         printk(" failed :(.\n");
2389         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2390                 "report.  Then try booting with the 'noapic' option");
2391 }
2392
2393 /*
2394  *
2395  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2396  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2397  *   Linux doesn't really care, as it's not actually used
2398  *   for any interrupt handling anyway.
2399  */
2400 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
2401
2402 void __init setup_IO_APIC(void)
2403 {
2404         enable_IO_APIC();
2405
2406         if (acpi_ioapic)
2407                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
2408         else
2409                 io_apic_irqs = ~PIC_IRQS;
2410
2411         printk("ENABLING IO-APIC IRQs\n");
2412
2413         /*
2414          * Set up IO-APIC IRQ routing.
2415          */
2416         if (!acpi_ioapic)
2417                 setup_ioapic_ids_from_mpc();
2418         sync_Arb_IDs();
2419         setup_IO_APIC_irqs();
2420         init_IO_APIC_traps();
2421         check_timer();
2422         if (!acpi_ioapic)
2423                 print_IO_APIC();
2424 }
2425
2426 static int __init setup_disable_8254_timer(char *s)
2427 {
2428         timer_over_8254 = -1;
2429         return 1;
2430 }
2431 static int __init setup_enable_8254_timer(char *s)
2432 {
2433         timer_over_8254 = 2;
2434         return 1;
2435 }
2436
2437 __setup("disable_8254_timer", setup_disable_8254_timer);
2438 __setup("enable_8254_timer", setup_enable_8254_timer);
2439
2440 /*
2441  *      Called after all the initialization is done. If we didnt find any
2442  *      APIC bugs then we can allow the modify fast path
2443  */
2444
2445 static int __init io_apic_bug_finalize(void)
2446 {
2447         if(sis_apic_bug == -1)
2448                 sis_apic_bug = 0;
2449         return 0;
2450 }
2451
2452 late_initcall(io_apic_bug_finalize);
2453
2454 struct sysfs_ioapic_data {
2455         struct sys_device dev;
2456         struct IO_APIC_route_entry entry[0];
2457 };
2458 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2459
2460 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2461 {
2462         struct IO_APIC_route_entry *entry;
2463         struct sysfs_ioapic_data *data;
2464         unsigned long flags;
2465         int i;
2466
2467         data = container_of(dev, struct sysfs_ioapic_data, dev);
2468         entry = data->entry;
2469         spin_lock_irqsave(&ioapic_lock, flags);
2470         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2471                 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
2472                 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
2473         }
2474         spin_unlock_irqrestore(&ioapic_lock, flags);
2475
2476         return 0;
2477 }
2478
2479 static int ioapic_resume(struct sys_device *dev)
2480 {
2481         struct IO_APIC_route_entry *entry;
2482         struct sysfs_ioapic_data *data;
2483         unsigned long flags;
2484         union IO_APIC_reg_00 reg_00;
2485         int i;
2486
2487         data = container_of(dev, struct sysfs_ioapic_data, dev);
2488         entry = data->entry;
2489
2490         spin_lock_irqsave(&ioapic_lock, flags);
2491         reg_00.raw = io_apic_read(dev->id, 0);
2492         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2493                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2494                 io_apic_write(dev->id, 0, reg_00.raw);
2495         }
2496         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2497                 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
2498                 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
2499         }
2500         spin_unlock_irqrestore(&ioapic_lock, flags);
2501
2502         return 0;
2503 }
2504
2505 static struct sysdev_class ioapic_sysdev_class = {
2506         set_kset_name("ioapic"),
2507         .suspend = ioapic_suspend,
2508         .resume = ioapic_resume,
2509 };
2510
2511 static int __init ioapic_init_sysfs(void)
2512 {
2513         struct sys_device * dev;
2514         int i, size, error = 0;
2515
2516         error = sysdev_class_register(&ioapic_sysdev_class);
2517         if (error)
2518                 return error;
2519
2520         for (i = 0; i < nr_ioapics; i++ ) {
2521                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2522                         * sizeof(struct IO_APIC_route_entry);
2523                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2524                 if (!mp_ioapic_data[i]) {
2525                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2526                         continue;
2527                 }
2528                 memset(mp_ioapic_data[i], 0, size);
2529                 dev = &mp_ioapic_data[i]->dev;
2530                 dev->id = i;
2531                 dev->cls = &ioapic_sysdev_class;
2532                 error = sysdev_register(dev);
2533                 if (error) {
2534                         kfree(mp_ioapic_data[i]);
2535                         mp_ioapic_data[i] = NULL;
2536                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2537                         continue;
2538                 }
2539         }
2540
2541         return 0;
2542 }
2543
2544 device_initcall(ioapic_init_sysfs);
2545
2546 /* --------------------------------------------------------------------------
2547                           ACPI-based IOAPIC Configuration
2548    -------------------------------------------------------------------------- */
2549
2550 #ifdef CONFIG_ACPI
2551
2552 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2553 {
2554         union IO_APIC_reg_00 reg_00;
2555         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2556         physid_mask_t tmp;
2557         unsigned long flags;
2558         int i = 0;
2559
2560         /*
2561          * The P4 platform supports up to 256 APIC IDs on two separate APIC
2562          * buses (one for LAPICs, one for IOAPICs), where predecessors only
2563          * supports up to 16 on one shared APIC bus.
2564          *
2565          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2566          *      advantage of new APIC bus architecture.
2567          */
2568
2569         if (physids_empty(apic_id_map))
2570                 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2571
2572         spin_lock_irqsave(&ioapic_lock, flags);
2573         reg_00.raw = io_apic_read(ioapic, 0);
2574         spin_unlock_irqrestore(&ioapic_lock, flags);
2575
2576         if (apic_id >= get_physical_broadcast()) {
2577                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2578                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
2579                 apic_id = reg_00.bits.ID;
2580         }
2581
2582         /*
2583          * Every APIC in a system must have a unique ID or we get lots of nice
2584          * 'stuck on smp_invalidate_needed IPI wait' messages.
2585          */
2586         if (check_apicid_used(apic_id_map, apic_id)) {
2587
2588                 for (i = 0; i < get_physical_broadcast(); i++) {
2589                         if (!check_apicid_used(apic_id_map, i))
2590                                 break;
2591                 }
2592
2593                 if (i == get_physical_broadcast())
2594                         panic("Max apic_id exceeded!\n");
2595
2596                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2597                         "trying %d\n", ioapic, apic_id, i);
2598
2599                 apic_id = i;
2600         }
2601
2602         tmp = apicid_to_cpu_present(apic_id);
2603         physids_or(apic_id_map, apic_id_map, tmp);
2604
2605         if (reg_00.bits.ID != apic_id) {
2606                 reg_00.bits.ID = apic_id;
2607
2608                 spin_lock_irqsave(&ioapic_lock, flags);
2609                 io_apic_write(ioapic, 0, reg_00.raw);
2610                 reg_00.raw = io_apic_read(ioapic, 0);
2611                 spin_unlock_irqrestore(&ioapic_lock, flags);
2612
2613                 /* Sanity check */
2614                 if (reg_00.bits.ID != apic_id) {
2615                         printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2616                         return -1;
2617                 }
2618         }
2619
2620         apic_printk(APIC_VERBOSE, KERN_INFO
2621                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2622
2623         return apic_id;
2624 }
2625
2626
2627 int __init io_apic_get_version (int ioapic)
2628 {
2629         union IO_APIC_reg_01    reg_01;
2630         unsigned long flags;
2631
2632         spin_lock_irqsave(&ioapic_lock, flags);
2633         reg_01.raw = io_apic_read(ioapic, 1);
2634         spin_unlock_irqrestore(&ioapic_lock, flags);
2635
2636         return reg_01.bits.version;
2637 }
2638
2639
2640 int __init io_apic_get_redir_entries (int ioapic)
2641 {
2642         union IO_APIC_reg_01    reg_01;
2643         unsigned long flags;
2644
2645         spin_lock_irqsave(&ioapic_lock, flags);
2646         reg_01.raw = io_apic_read(ioapic, 1);
2647         spin_unlock_irqrestore(&ioapic_lock, flags);
2648
2649         return reg_01.bits.entries;
2650 }
2651
2652
2653 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2654 {
2655         struct IO_APIC_route_entry entry;
2656         unsigned long flags;
2657
2658         if (!IO_APIC_IRQ(irq)) {
2659                 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2660                         ioapic);
2661                 return -EINVAL;
2662         }
2663
2664         /*
2665          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2666          * Note that we mask (disable) IRQs now -- these get enabled when the
2667          * corresponding device driver registers for this IRQ.
2668          */
2669
2670         memset(&entry,0,sizeof(entry));
2671
2672         entry.delivery_mode = INT_DELIVERY_MODE;
2673         entry.dest_mode = INT_DEST_MODE;
2674         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2675         entry.trigger = edge_level;
2676         entry.polarity = active_high_low;
2677         entry.mask  = 1;
2678
2679         /*
2680          * IRQs < 16 are already in the irq_2_pin[] map
2681          */
2682         if (irq >= 16)
2683                 add_pin_to_irq(irq, ioapic, pin);
2684
2685         entry.vector = assign_irq_vector(irq);
2686
2687         apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2688                 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2689                 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2690                 edge_level, active_high_low);
2691
2692         ioapic_register_intr(irq, entry.vector, edge_level);
2693
2694         if (!ioapic && (irq < 16))
2695                 disable_8259A_irq(irq);
2696
2697         spin_lock_irqsave(&ioapic_lock, flags);
2698         io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2699         io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2700         set_native_irq_info(use_pci_vector() ? entry.vector : irq, TARGET_CPUS);
2701         spin_unlock_irqrestore(&ioapic_lock, flags);
2702
2703         return 0;
2704 }
2705
2706 #endif /* CONFIG_ACPI */