arch/i386/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/irq.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/init.h>
  27 #include <linux/delay.h>
  28 #include <linux/sched.h>
  29 #include <linux/config.h>
  30 #include <linux/smp_lock.h>
  31 #include <linux/mc146818rtc.h>
  32 #include <linux/compiler.h>
  33 #include <linux/acpi.h>
  34 #include <linux/module.h>
  35 #include <linux/sysdev.h>
  36
  37 #include <asm/io.h>
  38 #include <asm/smp.h>
  39 #include <asm/desc.h>
  40 #include <asm/timer.h>
  41 #include <asm/i8259.h>
  42
  43 #include <mach_apic.h>
  44
  45 #include "io_ports.h"
  46
  47 int (*ioapic_renumber_irq)(int ioapic, int irq);
  48 atomic_t irq_mis_count;
  49
  50 static DEFINE_SPINLOCK(ioapic_lock);
  51
  52 /*
  53  *      Is the SiS APIC rmw bug present ?
  54  *      -1 = don't know, 0 = no, 1 = yes
  55  */
  56 int sis_apic_bug = -1;
  57
  58 /*
  59  * # of IRQ routing registers
  60  */
  61 int nr_ioapic_registers[MAX_IO_APICS];
  62
  63 /*
  64  * Rough estimation of how many shared IRQs there are, can
  65  * be changed anytime.
  66  */
  67 #define MAX_PLUS_SHARED_IRQS NR_IRQS
  68 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  69
  70 /*
  71  * This is performance-critical, we want to do it O(1)
  72  *
  73  * the indexing order of this array favors 1:1 mappings
  74  * between pins and IRQs.
  75  */
  76
  77 static struct irq_pin_list {
  78         int apic, pin, next;
  79 } irq_2_pin[PIN_MAP_SIZE];
  80
  81 int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
  82 #ifdef CONFIG_PCI_MSI
  83 #define vector_to_irq(vector)   \
  84         (platform_legacy_irq(vector) ? vector : vector_irq[vector])
  85 #else
  86 #define vector_to_irq(vector)   (vector)
  87 #endif
  88
  89 /*
  90  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
  91  * shared ISA-space IRQs, so we have to support them. We are super
  92  * fast in the common case, and fast for shared ISA-space IRQs.
  93  */
  94 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
  95 {
  96         static int first_free_entry = NR_IRQS;
  97         struct irq_pin_list *entry = irq_2_pin + irq;
  98
  99         while (entry->next)
 100                 entry = irq_2_pin + entry->next;
 101
 102         if (entry->pin != -1) {
 103                 entry->next = first_free_entry;
 104                 entry = irq_2_pin + entry->next;
 105                 if (++first_free_entry >= PIN_MAP_SIZE)
 106                         panic("io_apic.c: whoops");
 107         }
 108         entry->apic = apic;
 109         entry->pin = pin;
 110 }
 111
 112 /*
 113  * Reroute an IRQ to a different pin.
 114  */
 115 static void __init replace_pin_at_irq(unsigned int irq,
 116                                       int oldapic, int oldpin,
 117                                       int newapic, int newpin)
 118 {
 119         struct irq_pin_list *entry = irq_2_pin + irq;
 120
 121         while (1) {
 122                 if (entry->apic == oldapic && entry->pin == oldpin) {
 123                         entry->apic = newapic;
 124                         entry->pin = newpin;
 125                 }
 126                 if (!entry->next)
 127                         break;
 128                 entry = irq_2_pin + entry->next;
 129         }
 130 }
 131
 132 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
 133 {
 134         struct irq_pin_list *entry = irq_2_pin + irq;
 135         unsigned int pin, reg;
 136
 137         for (;;) {
 138                 pin = entry->pin;
 139                 if (pin == -1)
 140                         break;
 141                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
 142                 reg &= ~disable;
 143                 reg |= enable;
 144                 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
 145                 if (!entry->next)
 146                         break;
 147                 entry = irq_2_pin + entry->next;
 148         }
 149 }
 150
 151 /* mask = 1 */
 152 static void __mask_IO_APIC_irq (unsigned int irq)
 153 {
 154         __modify_IO_APIC_irq(irq, 0x00010000, 0);
 155 }
 156
 157 /* mask = 0 */
 158 static void __unmask_IO_APIC_irq (unsigned int irq)
 159 {
 160         __modify_IO_APIC_irq(irq, 0, 0x00010000);
 161 }
 162
 163 /* mask = 1, trigger = 0 */
 164 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
 165 {
 166         __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
 167 }
 168
 169 /* mask = 0, trigger = 1 */
 170 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
 171 {
 172         __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
 173 }
 174
 175 static void mask_IO_APIC_irq (unsigned int irq)
 176 {
 177         unsigned long flags;
 178
 179         spin_lock_irqsave(&ioapic_lock, flags);
 180         __mask_IO_APIC_irq(irq);
 181         spin_unlock_irqrestore(&ioapic_lock, flags);
 182 }
 183
 184 static void unmask_IO_APIC_irq (unsigned int irq)
 185 {
 186         unsigned long flags;
 187
 188         spin_lock_irqsave(&ioapic_lock, flags);
 189         __unmask_IO_APIC_irq(irq);
 190         spin_unlock_irqrestore(&ioapic_lock, flags);
 191 }
 192
 193 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 194 {
 195         struct IO_APIC_route_entry entry;
 196         unsigned long flags;
 197
 198         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 199         spin_lock_irqsave(&ioapic_lock, flags);
 200         *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
 201         *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
 202         spin_unlock_irqrestore(&ioapic_lock, flags);
 203         if (entry.delivery_mode == dest_SMI)
 204                 return;
 205
 206         /*
 207          * Disable it in the IO-APIC irq-routing table:
 208          */
 209         memset(&entry, 0, sizeof(entry));
 210         entry.mask = 1;
 211         spin_lock_irqsave(&ioapic_lock, flags);
 212         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
 213         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
 214         spin_unlock_irqrestore(&ioapic_lock, flags);
 215 }
 216
 217 static void clear_IO_APIC (void)
 218 {
 219         int apic, pin;
 220
 221         for (apic = 0; apic < nr_ioapics; apic++)
 222                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 223                         clear_IO_APIC_pin(apic, pin);
 224 }
 225
 226 #ifdef CONFIG_SMP
 227 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
 228 {
 229         unsigned long flags;
 230         int pin;
 231         struct irq_pin_list *entry = irq_2_pin + irq;
 232         unsigned int apicid_value;
 233         cpumask_t tmp;
 234
 235         cpus_and(tmp, cpumask, cpu_online_map);
 236         if (cpus_empty(tmp))
 237                 tmp = TARGET_CPUS;
 238
 239         cpus_and(cpumask, tmp, CPU_MASK_ALL);
 240
 241         apicid_value = cpu_mask_to_apicid(cpumask);
 242         /* Prepare to do the io_apic_write */
 243         apicid_value = apicid_value << 24;
 244         spin_lock_irqsave(&ioapic_lock, flags);
 245         for (;;) {
 246                 pin = entry->pin;
 247                 if (pin == -1)
 248                         break;
 249                 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
 250                 if (!entry->next)
 251                         break;
 252                 entry = irq_2_pin + entry->next;
 253         }
 254         set_irq_info(irq, cpumask);
 255         spin_unlock_irqrestore(&ioapic_lock, flags);
 256 }
 257
 258 #if defined(CONFIG_IRQBALANCE)
 259 # include <asm/processor.h>     /* kernel_thread() */
 260 # include <linux/kernel_stat.h> /* kstat */
 261 # include <linux/slab.h>                /* kmalloc() */
 262 # include <linux/timer.h>       /* time_after() */
 263
 264 # ifdef CONFIG_BALANCED_IRQ_DEBUG
 265 #  define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
 266 #  define Dprintk(x...) do { TDprintk(x); } while (0)
 267 # else
 268 #  define TDprintk(x...)
 269 #  define Dprintk(x...)
 270 # endif
 271
 272
 273 #define IRQBALANCE_CHECK_ARCH -999
 274 static int irqbalance_disabled = IRQBALANCE_CHECK_ARCH;
 275 static int physical_balance = 0;
 276
 277 static struct irq_cpu_info {
 278         unsigned long * last_irq;
 279         unsigned long * irq_delta;
 280         unsigned long irq;
 281 } irq_cpu_data[NR_CPUS];
 282
 283 #define CPU_IRQ(cpu)            (irq_cpu_data[cpu].irq)
 284 #define LAST_CPU_IRQ(cpu,irq)   (irq_cpu_data[cpu].last_irq[irq])
 285 #define IRQ_DELTA(cpu,irq)      (irq_cpu_data[cpu].irq_delta[irq])
 286
 287 #define IDLE_ENOUGH(cpu,now) \
 288         (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
 289
 290 #define IRQ_ALLOWED(cpu, allowed_mask)  cpu_isset(cpu, allowed_mask)
 291
 292 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
 293
 294 #define MAX_BALANCED_IRQ_INTERVAL       (5*HZ)
 295 #define MIN_BALANCED_IRQ_INTERVAL       (HZ/2)
 296 #define BALANCED_IRQ_MORE_DELTA         (HZ/10)
 297 #define BALANCED_IRQ_LESS_DELTA         (HZ)
 298
 299 static long balanced_irq_interval = MAX_BALANCED_IRQ_INTERVAL;
 300
 301 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
 302                         unsigned long now, int direction)
 303 {
 304         int search_idle = 1;
 305         int cpu = curr_cpu;
 306
 307         goto inside;
 308
 309         do {
 310                 if (unlikely(cpu == curr_cpu))
 311                         search_idle = 0;
 312 inside:
 313                 if (direction == 1) {
 314                         cpu++;
 315                         if (cpu >= NR_CPUS)
 316                                 cpu = 0;
 317                 } else {
 318                         cpu--;
 319                         if (cpu == -1)
 320                                 cpu = NR_CPUS-1;
 321                 }
 322         } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
 323                         (search_idle && !IDLE_ENOUGH(cpu,now)));
 324
 325         return cpu;
 326 }
 327
 328 static inline void balance_irq(int cpu, int irq)
 329 {
 330         unsigned long now = jiffies;
 331         cpumask_t allowed_mask;
 332         unsigned int new_cpu;
 333
 334         if (irqbalance_disabled)
 335                 return;
 336
 337         cpus_and(allowed_mask, cpu_online_map, irq_affinity[irq]);
 338         new_cpu = move(cpu, allowed_mask, now, 1);
 339         if (cpu != new_cpu) {
 340                 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
 341         }
 342 }
 343
 344 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
 345 {
 346         int i, j;
 347         Dprintk("Rotating IRQs among CPUs.\n");
 348         for (i = 0; i < NR_CPUS; i++) {
 349                 for (j = 0; cpu_online(i) && (j < NR_IRQS); j++) {
 350                         if (!irq_desc[j].action)
 351                                 continue;
 352                         /* Is it a significant load ?  */
 353                         if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
 354                                                 useful_load_threshold)
 355                                 continue;
 356                         balance_irq(i, j);
 357                 }
 358         }
 359         balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 360                 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 361         return;
 362 }
 363
 364 static void do_irq_balance(void)
 365 {
 366         int i, j;
 367         unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
 368         unsigned long move_this_load = 0;
 369         int max_loaded = 0, min_loaded = 0;
 370         int load;
 371         unsigned long useful_load_threshold = balanced_irq_interval + 10;
 372         int selected_irq;
 373         int tmp_loaded, first_attempt = 1;
 374         unsigned long tmp_cpu_irq;
 375         unsigned long imbalance = 0;
 376         cpumask_t allowed_mask, target_cpu_mask, tmp;
 377
 378         for (i = 0; i < NR_CPUS; i++) {
 379                 int package_index;
 380                 CPU_IRQ(i) = 0;
 381                 if (!cpu_online(i))
 382                         continue;
 383                 package_index = CPU_TO_PACKAGEINDEX(i);
 384                 for (j = 0; j < NR_IRQS; j++) {
 385                         unsigned long value_now, delta;
 386                         /* Is this an active IRQ? */
 387                         if (!irq_desc[j].action)
 388                                 continue;
 389                         if ( package_index == i )
 390                                 IRQ_DELTA(package_index,j) = 0;
 391                         /* Determine the total count per processor per IRQ */
 392                         value_now = (unsigned long) kstat_cpu(i).irqs[j];
 393
 394                         /* Determine the activity per processor per IRQ */
 395                         delta = value_now - LAST_CPU_IRQ(i,j);
 396
 397                         /* Update last_cpu_irq[][] for the next time */
 398                         LAST_CPU_IRQ(i,j) = value_now;
 399
 400                         /* Ignore IRQs whose rate is less than the clock */
 401                         if (delta < useful_load_threshold)
 402                                 continue;
 403                         /* update the load for the processor or package total */
 404                         IRQ_DELTA(package_index,j) += delta;
 405
 406                         /* Keep track of the higher numbered sibling as well */
 407                         if (i != package_index)
 408                                 CPU_IRQ(i) += delta;
 409                         /*
 410                          * We have sibling A and sibling B in the package
 411                          *
 412                          * cpu_irq[A] = load for cpu A + load for cpu B
 413                          * cpu_irq[B] = load for cpu B
 414                          */
 415                         CPU_IRQ(package_index) += delta;
 416                 }
 417         }
 418         /* Find the least loaded processor package */
 419         for (i = 0; i < NR_CPUS; i++) {
 420                 if (!cpu_online(i))
 421                         continue;
 422                 if (i != CPU_TO_PACKAGEINDEX(i))
 423                         continue;
 424                 if (min_cpu_irq > CPU_IRQ(i)) {
 425                         min_cpu_irq = CPU_IRQ(i);
 426                         min_loaded = i;
 427                 }
 428         }
 429         max_cpu_irq = ULONG_MAX;
 430
 431 tryanothercpu:
 432         /* Look for heaviest loaded processor.
 433          * We may come back to get the next heaviest loaded processor.
 434          * Skip processors with trivial loads.
 435          */
 436         tmp_cpu_irq = 0;
 437         tmp_loaded = -1;
 438         for (i = 0; i < NR_CPUS; i++) {
 439                 if (!cpu_online(i))
 440                         continue;
 441                 if (i != CPU_TO_PACKAGEINDEX(i))
 442                         continue;
 443                 if (max_cpu_irq <= CPU_IRQ(i))
 444                         continue;
 445                 if (tmp_cpu_irq < CPU_IRQ(i)) {
 446                         tmp_cpu_irq = CPU_IRQ(i);
 447                         tmp_loaded = i;
 448                 }
 449         }
 450
 451         if (tmp_loaded == -1) {
 452          /* In the case of small number of heavy interrupt sources,
 453           * loading some of the cpus too much. We use Ingo's original
 454           * approach to rotate them around.
 455           */
 456                 if (!first_attempt && imbalance >= useful_load_threshold) {
 457                         rotate_irqs_among_cpus(useful_load_threshold);
 458                         return;
 459                 }
 460                 goto not_worth_the_effort;
 461         }
 462
 463         first_attempt = 0;              /* heaviest search */
 464         max_cpu_irq = tmp_cpu_irq;      /* load */
 465         max_loaded = tmp_loaded;        /* processor */
 466         imbalance = (max_cpu_irq - min_cpu_irq) / 2;
 467
 468         Dprintk("max_loaded cpu = %d\n", max_loaded);
 469         Dprintk("min_loaded cpu = %d\n", min_loaded);
 470         Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
 471         Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
 472         Dprintk("load imbalance = %lu\n", imbalance);
 473
 474         /* if imbalance is less than approx 10% of max load, then
 475          * observe diminishing returns action. - quit
 476          */
 477         if (imbalance < (max_cpu_irq >> 3)) {
 478                 Dprintk("Imbalance too trivial\n");
 479                 goto not_worth_the_effort;
 480         }
 481
 482 tryanotherirq:
 483         /* if we select an IRQ to move that can't go where we want, then
 484          * see if there is another one to try.
 485          */
 486         move_this_load = 0;
 487         selected_irq = -1;
 488         for (j = 0; j < NR_IRQS; j++) {
 489                 /* Is this an active IRQ? */
 490                 if (!irq_desc[j].action)
 491                         continue;
 492                 if (imbalance <= IRQ_DELTA(max_loaded,j))
 493                         continue;
 494                 /* Try to find the IRQ that is closest to the imbalance
 495                  * without going over.
 496                  */
 497                 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
 498                         move_this_load = IRQ_DELTA(max_loaded,j);
 499                         selected_irq = j;
 500                 }
 501         }
 502         if (selected_irq == -1) {
 503                 goto tryanothercpu;
 504         }
 505
 506         imbalance = move_this_load;
 507
 508         /* For physical_balance case, we accumlated both load
 509          * values in the one of the siblings cpu_irq[],
 510          * to use the same code for physical and logical processors
 511          * as much as possible.
 512          *
 513          * NOTE: the cpu_irq[] array holds the sum of the load for
 514          * sibling A and sibling B in the slot for the lowest numbered
 515          * sibling (A), _AND_ the load for sibling B in the slot for
 516          * the higher numbered sibling.
 517          *
 518          * We seek the least loaded sibling by making the comparison
 519          * (A+B)/2 vs B
 520          */
 521         load = CPU_IRQ(min_loaded) >> 1;
 522         for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
 523                 if (load > CPU_IRQ(j)) {
 524                         /* This won't change cpu_sibling_map[min_loaded] */
 525                         load = CPU_IRQ(j);
 526                         min_loaded = j;
 527                 }
 528         }
 529
 530         cpus_and(allowed_mask, cpu_online_map, irq_affinity[selected_irq]);
 531         target_cpu_mask = cpumask_of_cpu(min_loaded);
 532         cpus_and(tmp, target_cpu_mask, allowed_mask);
 533
 534         if (!cpus_empty(tmp)) {
 535
 536                 Dprintk("irq = %d moved to cpu = %d\n",
 537                                 selected_irq, min_loaded);
 538                 /* mark for change destination */
 539                 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
 540
 541                 /* Since we made a change, come back sooner to
 542                  * check for more variation.
 543                  */
 544                 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 545                         balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 546                 return;
 547         }
 548         goto tryanotherirq;
 549
 550 not_worth_the_effort:
 551         /*
 552          * if we did not find an IRQ to move, then adjust the time interval
 553          * upward
 554          */
 555         balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
 556                 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
 557         Dprintk("IRQ worth rotating not found\n");
 558         return;
 559 }
 560
 561 static int balanced_irq(void *unused)
 562 {
 563         int i;
 564         unsigned long prev_balance_time = jiffies;
 565         long time_remaining = balanced_irq_interval;
 566
 567         daemonize("kirqd");
 568
 569         /* push everything to CPU 0 to give us a starting point.  */
 570         for (i = 0 ; i < NR_IRQS ; i++) {
 571                 pending_irq_cpumask[i] = cpumask_of_cpu(0);
 572                 set_pending_irq(i, cpumask_of_cpu(0));
 573         }
 574
 575         for ( ; ; ) {
 576                 set_current_state(TASK_INTERRUPTIBLE);
 577                 time_remaining = schedule_timeout(time_remaining);
 578                 try_to_freeze();
 579                 if (time_after(jiffies,
 580                                 prev_balance_time+balanced_irq_interval)) {
 581                         preempt_disable();
 582                         do_irq_balance();
 583                         prev_balance_time = jiffies;
 584                         time_remaining = balanced_irq_interval;
 585                         preempt_enable();
 586                 }
 587         }
 588         return 0;
 589 }
 590
 591 static int __init balanced_irq_init(void)
 592 {
 593         int i;
 594         struct cpuinfo_x86 *c;
 595         cpumask_t tmp;
 596
 597         cpus_shift_right(tmp, cpu_online_map, 2);
 598         c = &boot_cpu_data;
 599         /* When not overwritten by the command line ask subarchitecture. */
 600         if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
 601                 irqbalance_disabled = NO_BALANCE_IRQ;
 602         if (irqbalance_disabled)
 603                 return 0;
 604
 605          /* disable irqbalance completely if there is only one processor online */
 606         if (num_online_cpus() < 2) {
 607                 irqbalance_disabled = 1;
 608                 return 0;
 609         }
 610         /*
 611          * Enable physical balance only if more than 1 physical processor
 612          * is present
 613          */
 614         if (smp_num_siblings > 1 && !cpus_empty(tmp))
 615                 physical_balance = 1;
 616
 617         for (i = 0; i < NR_CPUS; i++) {
 618                 if (!cpu_online(i))
 619                         continue;
 620                 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 621                 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 622                 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
 623                         printk(KERN_ERR "balanced_irq_init: out of memory");
 624                         goto failed;
 625                 }
 626                 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
 627                 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
 628         }
 629
 630         printk(KERN_INFO "Starting balanced_irq\n");
 631         if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0)
 632                 return 0;
 633         else
 634                 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
 635 failed:
 636         for (i = 0; i < NR_CPUS; i++) {
 637                 kfree(irq_cpu_data[i].irq_delta);
 638                 kfree(irq_cpu_data[i].last_irq);
 639         }
 640         return 0;
 641 }
 642
 643 int __init irqbalance_disable(char *str)
 644 {
 645         irqbalance_disabled = 1;
 646         return 0;
 647 }
 648
 649 __setup("noirqbalance", irqbalance_disable);
 650
 651 late_initcall(balanced_irq_init);
 652 #endif /* CONFIG_IRQBALANCE */
 653 #endif /* CONFIG_SMP */
 654
 655 #ifndef CONFIG_SMP
 656 void fastcall send_IPI_self(int vector)
 657 {
 658         unsigned int cfg;
 659
 660         /*
 661          * Wait for idle.
 662          */
 663         apic_wait_icr_idle();
 664         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
 665         /*
 666          * Send the IPI. The write to APIC_ICR fires this off.
 667          */
 668         apic_write_around(APIC_ICR, cfg);
 669 }
 670 #endif /* !CONFIG_SMP */
 671
 672
 673 /*
 674  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 675  * specific CPU-side IRQs.
 676  */
 677
 678 #define MAX_PIRQS 8
 679 static int pirq_entries [MAX_PIRQS];
 680 static int pirqs_enabled;
 681 int skip_ioapic_setup;
 682
 683 static int __init ioapic_setup(char *str)
 684 {
 685         skip_ioapic_setup = 1;
 686         return 1;
 687 }
 688
 689 __setup("noapic", ioapic_setup);
 690
 691 static int __init ioapic_pirq_setup(char *str)
 692 {
 693         int i, max;
 694         int ints[MAX_PIRQS+1];
 695
 696         get_options(str, ARRAY_SIZE(ints), ints);
 697
 698         for (i = 0; i < MAX_PIRQS; i++)
 699                 pirq_entries[i] = -1;
 700
 701         pirqs_enabled = 1;
 702         apic_printk(APIC_VERBOSE, KERN_INFO
 703                         "PIRQ redirection, working around broken MP-BIOS.\n");
 704         max = MAX_PIRQS;
 705         if (ints[0] < MAX_PIRQS)
 706                 max = ints[0];
 707
 708         for (i = 0; i < max; i++) {
 709                 apic_printk(APIC_VERBOSE, KERN_DEBUG
 710                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 711                 /*
 712                  * PIRQs are mapped upside down, usually.
 713                  */
 714                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 715         }
 716         return 1;
 717 }
 718
 719 __setup("pirq=", ioapic_pirq_setup);
 720
 721 /*
 722  * Find the IRQ entry number of a certain pin.
 723  */
 724 static int find_irq_entry(int apic, int pin, int type)
 725 {
 726         int i;
 727
 728         for (i = 0; i < mp_irq_entries; i++)
 729                 if (mp_irqs[i].mpc_irqtype == type &&
 730                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 731                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 732                     mp_irqs[i].mpc_dstirq == pin)
 733                         return i;
 734
 735         return -1;
 736 }
 737
 738 /*
 739  * Find the pin to which IRQ[irq] (ISA) is connected
 740  */
 741 static int find_isa_irq_pin(int irq, int type)
 742 {
 743         int i;
 744
 745         for (i = 0; i < mp_irq_entries; i++) {
 746                 int lbus = mp_irqs[i].mpc_srcbus;
 747
 748                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 749                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 750                      mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
 751                      mp_bus_id_to_type[lbus] == MP_BUS_NEC98
 752                     ) &&
 753                     (mp_irqs[i].mpc_irqtype == type) &&
 754                     (mp_irqs[i].mpc_srcbusirq == irq))
 755
 756                         return mp_irqs[i].mpc_dstirq;
 757         }
 758         return -1;
 759 }
 760
 761 /*
 762  * Find a specific PCI IRQ entry.
 763  * Not an __init, possibly needed by modules
 764  */
 765 static int pin_2_irq(int idx, int apic, int pin);
 766
 767 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 768 {
 769         int apic, i, best_guess = -1;
 770
 771         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
 772                 "slot:%d, pin:%d.\n", bus, slot, pin);
 773         if (mp_bus_id_to_pci_bus[bus] == -1) {
 774                 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 775                 return -1;
 776         }
 777         for (i = 0; i < mp_irq_entries; i++) {
 778                 int lbus = mp_irqs[i].mpc_srcbus;
 779
 780                 for (apic = 0; apic < nr_ioapics; apic++)
 781                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 782                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 783                                 break;
 784
 785                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
 786                     !mp_irqs[i].mpc_irqtype &&
 787                     (bus == lbus) &&
 788                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 789                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 790
 791                         if (!(apic || IO_APIC_IRQ(irq)))
 792                                 continue;
 793
 794                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 795                                 return irq;
 796                         /*
 797                          * Use the first all-but-pin matching entry as a
 798                          * best-guess fuzzy result for broken mptables.
 799                          */
 800                         if (best_guess < 0)
 801                                 best_guess = irq;
 802                 }
 803         }
 804         return best_guess;
 805 }
 806 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
 807
 808 /*
 809  * This function currently is only a helper for the i386 smp boot process where
 810  * we need to reprogram the ioredtbls to cater for the cpus which have come online
 811  * so mask in all cases should simply be TARGET_CPUS
 812  */
 813 #ifdef CONFIG_SMP
 814 void __init setup_ioapic_dest(void)
 815 {
 816         int pin, ioapic, irq, irq_entry;
 817
 818         if (skip_ioapic_setup == 1)
 819                 return;
 820
 821         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
 822                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
 823                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
 824                         if (irq_entry == -1)
 825                                 continue;
 826                         irq = pin_2_irq(irq_entry, ioapic, pin);
 827                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
 828                 }
 829
 830         }
 831 }
 832 #endif
 833
 834 /*
 835  * EISA Edge/Level control register, ELCR
 836  */
 837 static int EISA_ELCR(unsigned int irq)
 838 {
 839         if (irq < 16) {
 840                 unsigned int port = 0x4d0 + (irq >> 3);
 841                 return (inb(port) >> (irq & 7)) & 1;
 842         }
 843         apic_printk(APIC_VERBOSE, KERN_INFO
 844                         "Broken MPtable reports ISA irq %d\n", irq);
 845         return 0;
 846 }
 847
 848 /* EISA interrupts are always polarity zero and can be edge or level
 849  * trigger depending on the ELCR value.  If an interrupt is listed as
 850  * EISA conforming in the MP table, that means its trigger type must
 851  * be read in from the ELCR */
 852
 853 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
 854 #define default_EISA_polarity(idx)      (0)
 855
 856 /* ISA interrupts are always polarity zero edge triggered,
 857  * when listed as conforming in the MP table. */
 858
 859 #define default_ISA_trigger(idx)        (0)
 860 #define default_ISA_polarity(idx)       (0)
 861
 862 /* PCI interrupts are always polarity one level triggered,
 863  * when listed as conforming in the MP table. */
 864
 865 #define default_PCI_trigger(idx)        (1)
 866 #define default_PCI_polarity(idx)       (1)
 867
 868 /* MCA interrupts are always polarity zero level triggered,
 869  * when listed as conforming in the MP table. */
 870
 871 #define default_MCA_trigger(idx)        (1)
 872 #define default_MCA_polarity(idx)       (0)
 873
 874 /* NEC98 interrupts are always polarity zero edge triggered,
 875  * when listed as conforming in the MP table. */
 876
 877 #define default_NEC98_trigger(idx)     (0)
 878 #define default_NEC98_polarity(idx)    (0)
 879
 880 static int __init MPBIOS_polarity(int idx)
 881 {
 882         int bus = mp_irqs[idx].mpc_srcbus;
 883         int polarity;
 884
 885         /*
 886          * Determine IRQ line polarity (high active or low active):
 887          */
 888         switch (mp_irqs[idx].mpc_irqflag & 3)
 889         {
 890                 case 0: /* conforms, ie. bus-type dependent polarity */
 891                 {
 892                         switch (mp_bus_id_to_type[bus])
 893                         {
 894                                 case MP_BUS_ISA: /* ISA pin */
 895                                 {
 896                                         polarity = default_ISA_polarity(idx);
 897                                         break;
 898                                 }
 899                                 case MP_BUS_EISA: /* EISA pin */
 900                                 {
 901                                         polarity = default_EISA_polarity(idx);
 902                                         break;
 903                                 }
 904                                 case MP_BUS_PCI: /* PCI pin */
 905                                 {
 906                                         polarity = default_PCI_polarity(idx);
 907                                         break;
 908                                 }
 909                                 case MP_BUS_MCA: /* MCA pin */
 910                                 {
 911                                         polarity = default_MCA_polarity(idx);
 912                                         break;
 913                                 }
 914                                 case MP_BUS_NEC98: /* NEC 98 pin */
 915                                 {
 916                                         polarity = default_NEC98_polarity(idx);
 917                                         break;
 918                                 }
 919                                 default:
 920                                 {
 921                                         printk(KERN_WARNING "broken BIOS!!\n");
 922                                         polarity = 1;
 923                                         break;
 924                                 }
 925                         }
 926                         break;
 927                 }
 928                 case 1: /* high active */
 929                 {
 930                         polarity = 0;
 931                         break;
 932                 }
 933                 case 2: /* reserved */
 934                 {
 935                         printk(KERN_WARNING "broken BIOS!!\n");
 936                         polarity = 1;
 937                         break;
 938                 }
 939                 case 3: /* low active */
 940                 {
 941                         polarity = 1;
 942                         break;
 943                 }
 944                 default: /* invalid */
 945                 {
 946                         printk(KERN_WARNING "broken BIOS!!\n");
 947                         polarity = 1;
 948                         break;
 949                 }
 950         }
 951         return polarity;
 952 }
 953
 954 static int MPBIOS_trigger(int idx)
 955 {
 956         int bus = mp_irqs[idx].mpc_srcbus;
 957         int trigger;
 958
 959         /*
 960          * Determine IRQ trigger mode (edge or level sensitive):
 961          */
 962         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
 963         {
 964                 case 0: /* conforms, ie. bus-type dependent */
 965                 {
 966                         switch (mp_bus_id_to_type[bus])
 967                         {
 968                                 case MP_BUS_ISA: /* ISA pin */
 969                                 {
 970                                         trigger = default_ISA_trigger(idx);
 971                                         break;
 972                                 }
 973                                 case MP_BUS_EISA: /* EISA pin */
 974                                 {
 975                                         trigger = default_EISA_trigger(idx);
 976                                         break;
 977                                 }
 978                                 case MP_BUS_PCI: /* PCI pin */
 979                                 {
 980                                         trigger = default_PCI_trigger(idx);
 981                                         break;
 982                                 }
 983                                 case MP_BUS_MCA: /* MCA pin */
 984                                 {
 985                                         trigger = default_MCA_trigger(idx);
 986                                         break;
 987                                 }
 988                                 case MP_BUS_NEC98: /* NEC 98 pin */
 989                                 {
 990                                         trigger = default_NEC98_trigger(idx);
 991                                         break;
 992                                 }
 993                                 default:
 994                                 {
 995                                         printk(KERN_WARNING "broken BIOS!!\n");
 996                                         trigger = 1;
 997                                         break;
 998                                 }
 999                         }
1000                         break;
1001                 }
1002                 case 1: /* edge */
1003                 {
1004                         trigger = 0;
1005                         break;
1006                 }
1007                 case 2: /* reserved */
1008                 {
1009                         printk(KERN_WARNING "broken BIOS!!\n");
1010                         trigger = 1;
1011                         break;
1012                 }
1013                 case 3: /* level */
1014                 {
1015                         trigger = 1;
1016                         break;
1017                 }
1018                 default: /* invalid */
1019                 {
1020                         printk(KERN_WARNING "broken BIOS!!\n");
1021                         trigger = 0;
1022                         break;
1023                 }
1024         }
1025         return trigger;
1026 }
1027
1028 static inline int irq_polarity(int idx)
1029 {
1030         return MPBIOS_polarity(idx);
1031 }
1032
1033 static inline int irq_trigger(int idx)
1034 {
1035         return MPBIOS_trigger(idx);
1036 }
1037
1038 static int pin_2_irq(int idx, int apic, int pin)
1039 {
1040         int irq, i;
1041         int bus = mp_irqs[idx].mpc_srcbus;
1042
1043         /*
1044          * Debugging check, we are in big trouble if this message pops up!
1045          */
1046         if (mp_irqs[idx].mpc_dstirq != pin)
1047                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1048
1049         switch (mp_bus_id_to_type[bus])
1050         {
1051                 case MP_BUS_ISA: /* ISA pin */
1052                 case MP_BUS_EISA:
1053                 case MP_BUS_MCA:
1054                 case MP_BUS_NEC98:
1055                 {
1056                         irq = mp_irqs[idx].mpc_srcbusirq;
1057                         break;
1058                 }
1059                 case MP_BUS_PCI: /* PCI pin */
1060                 {
1061                         /*
1062                          * PCI IRQs are mapped in order
1063                          */
1064                         i = irq = 0;
1065                         while (i < apic)
1066                                 irq += nr_ioapic_registers[i++];
1067                         irq += pin;
1068
1069                         /*
1070                          * For MPS mode, so far only needed by ES7000 platform
1071                          */
1072                         if (ioapic_renumber_irq)
1073                                 irq = ioapic_renumber_irq(apic, irq);
1074
1075                         break;
1076                 }
1077                 default:
1078                 {
1079                         printk(KERN_ERR "unknown bus type %d.\n",bus);
1080                         irq = 0;
1081                         break;
1082                 }
1083         }
1084
1085         /*
1086          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1087          */
1088         if ((pin >= 16) && (pin <= 23)) {
1089                 if (pirq_entries[pin-16] != -1) {
1090                         if (!pirq_entries[pin-16]) {
1091                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1092                                                 "disabling PIRQ%d\n", pin-16);
1093                         } else {
1094                                 irq = pirq_entries[pin-16];
1095                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1096                                                 "using PIRQ%d -> IRQ %d\n",
1097                                                 pin-16, irq);
1098                         }
1099                 }
1100         }
1101         return irq;
1102 }
1103
1104 static inline int IO_APIC_irq_trigger(int irq)
1105 {
1106         int apic, idx, pin;
1107
1108         for (apic = 0; apic < nr_ioapics; apic++) {
1109                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1110                         idx = find_irq_entry(apic,pin,mp_INT);
1111                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1112                                 return irq_trigger(idx);
1113                 }
1114         }
1115         /*
1116          * nonexistent IRQs are edge default
1117          */
1118         return 0;
1119 }
1120
1121 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1122 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1123
1124 int assign_irq_vector(int irq)
1125 {
1126         static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
1127
1128         BUG_ON(irq >= NR_IRQ_VECTORS);
1129         if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0)
1130                 return IO_APIC_VECTOR(irq);
1131 next:
1132         current_vector += 8;
1133         if (current_vector == SYSCALL_VECTOR)
1134                 goto next;
1135
1136         if (current_vector >= FIRST_SYSTEM_VECTOR) {
1137                 offset++;
1138                 if (!(offset%8))
1139                         return -ENOSPC;
1140                 current_vector = FIRST_DEVICE_VECTOR + offset;
1141         }
1142
1143         vector_irq[current_vector] = irq;
1144         if (irq != AUTO_ASSIGN)
1145                 IO_APIC_VECTOR(irq) = current_vector;
1146
1147         return current_vector;
1148 }
1149
1150 static struct hw_interrupt_type ioapic_level_type;
1151 static struct hw_interrupt_type ioapic_edge_type;
1152
1153 #define IOAPIC_AUTO     -1
1154 #define IOAPIC_EDGE     0
1155 #define IOAPIC_LEVEL    1
1156
1157 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1158 {
1159         if (use_pci_vector() && !platform_legacy_irq(irq)) {
1160                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1161                                 trigger == IOAPIC_LEVEL)
1162                         irq_desc[vector].handler = &ioapic_level_type;
1163                 else
1164                         irq_desc[vector].handler = &ioapic_edge_type;
1165                 set_intr_gate(vector, interrupt[vector]);
1166         } else  {
1167                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1168                                 trigger == IOAPIC_LEVEL)
1169                         irq_desc[irq].handler = &ioapic_level_type;
1170                 else
1171                         irq_desc[irq].handler = &ioapic_edge_type;
1172                 set_intr_gate(vector, interrupt[irq]);
1173         }
1174 }
1175
1176 static void __init setup_IO_APIC_irqs(void)
1177 {
1178         struct IO_APIC_route_entry entry;
1179         int apic, pin, idx, irq, first_notcon = 1, vector;
1180         unsigned long flags;
1181
1182         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1183
1184         for (apic = 0; apic < nr_ioapics; apic++) {
1185         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1186
1187                 /*
1188                  * add it to the IO-APIC irq-routing table:
1189                  */
1190                 memset(&entry,0,sizeof(entry));
1191
1192                 entry.delivery_mode = INT_DELIVERY_MODE;
1193                 entry.dest_mode = INT_DEST_MODE;
1194                 entry.mask = 0;                         /* enable IRQ */
1195                 entry.dest.logical.logical_dest =
1196                                         cpu_mask_to_apicid(TARGET_CPUS);
1197
1198                 idx = find_irq_entry(apic,pin,mp_INT);
1199                 if (idx == -1) {
1200                         if (first_notcon) {
1201                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1202                                                 " IO-APIC (apicid-pin) %d-%d",
1203                                                 mp_ioapics[apic].mpc_apicid,
1204                                                 pin);
1205                                 first_notcon = 0;
1206                         } else
1207                                 apic_printk(APIC_VERBOSE, ", %d-%d",
1208                                         mp_ioapics[apic].mpc_apicid, pin);
1209                         continue;
1210                 }
1211
1212                 entry.trigger = irq_trigger(idx);
1213                 entry.polarity = irq_polarity(idx);
1214
1215                 if (irq_trigger(idx)) {
1216                         entry.trigger = 1;
1217                         entry.mask = 1;
1218                 }
1219
1220                 irq = pin_2_irq(idx, apic, pin);
1221                 /*
1222                  * skip adding the timer int on secondary nodes, which causes
1223                  * a small but painful rift in the time-space continuum
1224                  */
1225                 if (multi_timer_check(apic, irq))
1226                         continue;
1227                 else
1228                         add_pin_to_irq(irq, apic, pin);
1229
1230                 if (!apic && !IO_APIC_IRQ(irq))
1231                         continue;
1232
1233                 if (IO_APIC_IRQ(irq)) {
1234                         vector = assign_irq_vector(irq);
1235                         entry.vector = vector;
1236                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1237
1238                         if (!apic && (irq < 16))
1239                                 disable_8259A_irq(irq);
1240                 }
1241                 spin_lock_irqsave(&ioapic_lock, flags);
1242                 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1243                 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1244                 set_native_irq_info(irq, TARGET_CPUS);
1245                 spin_unlock_irqrestore(&ioapic_lock, flags);
1246         }
1247         }
1248
1249         if (!first_notcon)
1250                 apic_printk(APIC_VERBOSE, " not connected.\n");
1251 }
1252
1253 /*
1254  * Set up the 8259A-master output pin:
1255  */
1256 static void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
1257 {
1258         struct IO_APIC_route_entry entry;
1259         unsigned long flags;
1260
1261         memset(&entry,0,sizeof(entry));
1262
1263         disable_8259A_irq(0);
1264
1265         /* mask LVT0 */
1266         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1267
1268         /*
1269          * We use logical delivery to get the timer IRQ
1270          * to the first CPU.
1271          */
1272         entry.dest_mode = INT_DEST_MODE;
1273         entry.mask = 0;                                 /* unmask IRQ now */
1274         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1275         entry.delivery_mode = INT_DELIVERY_MODE;
1276         entry.polarity = 0;
1277         entry.trigger = 0;
1278         entry.vector = vector;
1279
1280         /*
1281          * The timer IRQ doesn't have to know that behind the
1282          * scene we have a 8259A-master in AEOI mode ...
1283          */
1284         irq_desc[0].handler = &ioapic_edge_type;
1285
1286         /*
1287          * Add it to the IO-APIC irq-routing table:
1288          */
1289         spin_lock_irqsave(&ioapic_lock, flags);
1290         io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
1291         io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
1292         spin_unlock_irqrestore(&ioapic_lock, flags);
1293
1294         enable_8259A_irq(0);
1295 }
1296
1297 static inline void UNEXPECTED_IO_APIC(void)
1298 {
1299 }
1300
1301 void __init print_IO_APIC(void)
1302 {
1303         int apic, i;
1304         union IO_APIC_reg_00 reg_00;
1305         union IO_APIC_reg_01 reg_01;
1306         union IO_APIC_reg_02 reg_02;
1307         union IO_APIC_reg_03 reg_03;
1308         unsigned long flags;
1309
1310         if (apic_verbosity == APIC_QUIET)
1311                 return;
1312
1313         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1314         for (i = 0; i < nr_ioapics; i++)
1315                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1316                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1317
1318         /*
1319          * We are a bit conservative about what we expect.  We have to
1320          * know about every hardware change ASAP.
1321          */
1322         printk(KERN_INFO "testing the IO APIC.......................\n");
1323
1324         for (apic = 0; apic < nr_ioapics; apic++) {
1325
1326         spin_lock_irqsave(&ioapic_lock, flags);
1327         reg_00.raw = io_apic_read(apic, 0);
1328         reg_01.raw = io_apic_read(apic, 1);
1329         if (reg_01.bits.version >= 0x10)
1330                 reg_02.raw = io_apic_read(apic, 2);
1331         if (reg_01.bits.version >= 0x20)
1332                 reg_03.raw = io_apic_read(apic, 3);
1333         spin_unlock_irqrestore(&ioapic_lock, flags);
1334
1335         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1336         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1337         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1338         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1339         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1340         if (reg_00.bits.ID >= get_physical_broadcast())
1341                 UNEXPECTED_IO_APIC();
1342         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1343                 UNEXPECTED_IO_APIC();
1344
1345         printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1346         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1347         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1348                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1349                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1350                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1351                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1352                 (reg_01.bits.entries != 0x2E) &&
1353                 (reg_01.bits.entries != 0x3F)
1354         )
1355                 UNEXPECTED_IO_APIC();
1356
1357         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1358         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1359         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1360                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1361                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1362                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1363                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
1364         )
1365                 UNEXPECTED_IO_APIC();
1366         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1367                 UNEXPECTED_IO_APIC();
1368
1369         /*
1370          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1371          * but the value of reg_02 is read as the previous read register
1372          * value, so ignore it if reg_02 == reg_01.
1373          */
1374         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1375                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1376                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1377                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1378                         UNEXPECTED_IO_APIC();
1379         }
1380
1381         /*
1382          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1383          * or reg_03, but the value of reg_0[23] is read as the previous read
1384          * register value, so ignore it if reg_03 == reg_0[12].
1385          */
1386         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1387             reg_03.raw != reg_01.raw) {
1388                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1389                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1390                 if (reg_03.bits.__reserved_1)
1391                         UNEXPECTED_IO_APIC();
1392         }
1393
1394         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1395
1396         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1397                           " Stat Dest Deli Vect:   \n");
1398
1399         for (i = 0; i <= reg_01.bits.entries; i++) {
1400                 struct IO_APIC_route_entry entry;
1401
1402                 spin_lock_irqsave(&ioapic_lock, flags);
1403                 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
1404                 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
1405                 spin_unlock_irqrestore(&ioapic_lock, flags);
1406
1407                 printk(KERN_DEBUG " %02x %03X %02X  ",
1408                         i,
1409                         entry.dest.logical.logical_dest,
1410                         entry.dest.physical.physical_dest
1411                 );
1412
1413                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1414                         entry.mask,
1415                         entry.trigger,
1416                         entry.irr,
1417                         entry.polarity,
1418                         entry.delivery_status,
1419                         entry.dest_mode,
1420                         entry.delivery_mode,
1421                         entry.vector
1422                 );
1423         }
1424         }
1425         if (use_pci_vector())
1426                 printk(KERN_INFO "Using vector-based indexing\n");
1427         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1428         for (i = 0; i < NR_IRQS; i++) {
1429                 struct irq_pin_list *entry = irq_2_pin + i;
1430                 if (entry->pin < 0)
1431                         continue;
1432                 if (use_pci_vector() && !platform_legacy_irq(i))
1433                         printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1434                 else
1435                         printk(KERN_DEBUG "IRQ%d ", i);
1436                 for (;;) {
1437                         printk("-> %d:%d", entry->apic, entry->pin);
1438                         if (!entry->next)
1439                                 break;
1440                         entry = irq_2_pin + entry->next;
1441                 }
1442                 printk("\n");
1443         }
1444
1445         printk(KERN_INFO ".................................... done.\n");
1446
1447         return;
1448 }
1449
1450 #if 0
1451
1452 static void print_APIC_bitfield (int base)
1453 {
1454         unsigned int v;
1455         int i, j;
1456
1457         if (apic_verbosity == APIC_QUIET)
1458                 return;
1459
1460         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1461         for (i = 0; i < 8; i++) {
1462                 v = apic_read(base + i*0x10);
1463                 for (j = 0; j < 32; j++) {
1464                         if (v & (1<<j))
1465                                 printk("1");
1466                         else
1467                                 printk("0");
1468                 }
1469                 printk("\n");
1470         }
1471 }
1472
1473 void /*__init*/ print_local_APIC(void * dummy)
1474 {
1475         unsigned int v, ver, maxlvt;
1476
1477         if (apic_verbosity == APIC_QUIET)
1478                 return;
1479
1480         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1481                 smp_processor_id(), hard_smp_processor_id());
1482         v = apic_read(APIC_ID);
1483         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1484         v = apic_read(APIC_LVR);
1485         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1486         ver = GET_APIC_VERSION(v);
1487         maxlvt = get_maxlvt();
1488
1489         v = apic_read(APIC_TASKPRI);
1490         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1491
1492         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1493                 v = apic_read(APIC_ARBPRI);
1494                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1495                         v & APIC_ARBPRI_MASK);
1496                 v = apic_read(APIC_PROCPRI);
1497                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1498         }
1499
1500         v = apic_read(APIC_EOI);
1501         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1502         v = apic_read(APIC_RRR);
1503         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1504         v = apic_read(APIC_LDR);
1505         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1506         v = apic_read(APIC_DFR);
1507         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1508         v = apic_read(APIC_SPIV);
1509         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1510
1511         printk(KERN_DEBUG "... APIC ISR field:\n");
1512         print_APIC_bitfield(APIC_ISR);
1513         printk(KERN_DEBUG "... APIC TMR field:\n");
1514         print_APIC_bitfield(APIC_TMR);
1515         printk(KERN_DEBUG "... APIC IRR field:\n");
1516         print_APIC_bitfield(APIC_IRR);
1517
1518         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1519                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1520                         apic_write(APIC_ESR, 0);
1521                 v = apic_read(APIC_ESR);
1522                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1523         }
1524
1525         v = apic_read(APIC_ICR);
1526         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1527         v = apic_read(APIC_ICR2);
1528         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1529
1530         v = apic_read(APIC_LVTT);
1531         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1532
1533         if (maxlvt > 3) {                       /* PC is LVT#4. */
1534                 v = apic_read(APIC_LVTPC);
1535                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1536         }
1537         v = apic_read(APIC_LVT0);
1538         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1539         v = apic_read(APIC_LVT1);
1540         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1541
1542         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1543                 v = apic_read(APIC_LVTERR);
1544                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1545         }
1546
1547         v = apic_read(APIC_TMICT);
1548         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1549         v = apic_read(APIC_TMCCT);
1550         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1551         v = apic_read(APIC_TDCR);
1552         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1553         printk("\n");
1554 }
1555
1556 void print_all_local_APICs (void)
1557 {
1558         on_each_cpu(print_local_APIC, NULL, 1, 1);
1559 }
1560
1561 void /*__init*/ print_PIC(void)
1562 {
1563         unsigned int v;
1564         unsigned long flags;
1565
1566         if (apic_verbosity == APIC_QUIET)
1567                 return;
1568
1569         printk(KERN_DEBUG "\nprinting PIC contents\n");
1570
1571         spin_lock_irqsave(&i8259A_lock, flags);
1572
1573         v = inb(0xa1) << 8 | inb(0x21);
1574         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1575
1576         v = inb(0xa0) << 8 | inb(0x20);
1577         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1578
1579         outb(0x0b,0xa0);
1580         outb(0x0b,0x20);
1581         v = inb(0xa0) << 8 | inb(0x20);
1582         outb(0x0a,0xa0);
1583         outb(0x0a,0x20);
1584
1585         spin_unlock_irqrestore(&i8259A_lock, flags);
1586
1587         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1588
1589         v = inb(0x4d1) << 8 | inb(0x4d0);
1590         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1591 }
1592
1593 #endif  /*  0  */
1594
1595 static void __init enable_IO_APIC(void)
1596 {
1597         union IO_APIC_reg_01 reg_01;
1598         int i;
1599         unsigned long flags;
1600
1601         for (i = 0; i < PIN_MAP_SIZE; i++) {
1602                 irq_2_pin[i].pin = -1;
1603                 irq_2_pin[i].next = 0;
1604         }
1605         if (!pirqs_enabled)
1606                 for (i = 0; i < MAX_PIRQS; i++)
1607                         pirq_entries[i] = -1;
1608
1609         /*
1610          * The number of IO-APIC IRQ registers (== #pins):
1611          */
1612         for (i = 0; i < nr_ioapics; i++) {
1613                 spin_lock_irqsave(&ioapic_lock, flags);
1614                 reg_01.raw = io_apic_read(i, 1);
1615                 spin_unlock_irqrestore(&ioapic_lock, flags);
1616                 nr_ioapic_registers[i] = reg_01.bits.entries+1;
1617         }
1618
1619         /*
1620          * Do not trust the IO-APIC being empty at bootup
1621          */
1622         clear_IO_APIC();
1623 }
1624
1625 /*
1626  * Not an __init, needed by the reboot code
1627  */
1628 void disable_IO_APIC(void)
1629 {
1630         int pin;
1631         /*
1632          * Clear the IO-APIC before rebooting:
1633          */
1634         clear_IO_APIC();
1635
1636         /*
1637          * If the i8259 is routed through an IOAPIC
1638          * Put that IOAPIC in virtual wire mode
1639          * so legacy interrupts can be delivered.
1640          */
1641         pin = find_isa_irq_pin(0, mp_ExtINT);
1642         if (pin != -1) {
1643                 struct IO_APIC_route_entry entry;
1644                 unsigned long flags;
1645
1646                 memset(&entry, 0, sizeof(entry));
1647                 entry.mask            = 0; /* Enabled */
1648                 entry.trigger         = 0; /* Edge */
1649                 entry.irr             = 0;
1650                 entry.polarity        = 0; /* High */
1651                 entry.delivery_status = 0;
1652                 entry.dest_mode       = 0; /* Physical */
1653                 entry.delivery_mode   = 7; /* ExtInt */
1654                 entry.vector          = 0;
1655                 entry.dest.physical.physical_dest = 0;
1656
1657
1658                 /*
1659                  * Add it to the IO-APIC irq-routing table:
1660                  */
1661                 spin_lock_irqsave(&ioapic_lock, flags);
1662                 io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
1663                 io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
1664                 spin_unlock_irqrestore(&ioapic_lock, flags);
1665         }
1666         disconnect_bsp_APIC(pin != -1);
1667 }
1668
1669 /*
1670  * function to set the IO-APIC physical IDs based on the
1671  * values stored in the MPC table.
1672  *
1673  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1674  */
1675
1676 #ifndef CONFIG_X86_NUMAQ
1677 static void __init setup_ioapic_ids_from_mpc(void)
1678 {
1679         union IO_APIC_reg_00 reg_00;
1680         physid_mask_t phys_id_present_map;
1681         int apic;
1682         int i;
1683         unsigned char old_id;
1684         unsigned long flags;
1685
1686         /*
1687          * Don't check I/O APIC IDs for xAPIC systems.  They have
1688          * no meaning without the serial APIC bus.
1689          */
1690         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && boot_cpu_data.x86 < 15))
1691                 return;
1692         /*
1693          * This is broken; anything with a real cpu count has to
1694          * circumvent this idiocy regardless.
1695          */
1696         phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1697
1698         /*
1699          * Set the IOAPIC ID to the value stored in the MPC table.
1700          */
1701         for (apic = 0; apic < nr_ioapics; apic++) {
1702
1703                 /* Read the register 0 value */
1704                 spin_lock_irqsave(&ioapic_lock, flags);
1705                 reg_00.raw = io_apic_read(apic, 0);
1706                 spin_unlock_irqrestore(&ioapic_lock, flags);
1707
1708                 old_id = mp_ioapics[apic].mpc_apicid;
1709
1710                 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1711                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1712                                 apic, mp_ioapics[apic].mpc_apicid);
1713                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1714                                 reg_00.bits.ID);
1715                         mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1716                 }
1717
1718                 /*
1719                  * Sanity check, is the ID really free? Every APIC in a
1720                  * system must have a unique ID or we get lots of nice
1721                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1722                  */
1723                 if (check_apicid_used(phys_id_present_map,
1724                                         mp_ioapics[apic].mpc_apicid)) {
1725                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1726                                 apic, mp_ioapics[apic].mpc_apicid);
1727                         for (i = 0; i < get_physical_broadcast(); i++)
1728                                 if (!physid_isset(i, phys_id_present_map))
1729                                         break;
1730                         if (i >= get_physical_broadcast())
1731                                 panic("Max APIC ID exceeded!\n");
1732                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1733                                 i);
1734                         physid_set(i, phys_id_present_map);
1735                         mp_ioapics[apic].mpc_apicid = i;
1736                 } else {
1737                         physid_mask_t tmp;
1738                         tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1739                         apic_printk(APIC_VERBOSE, "Setting %d in the "
1740                                         "phys_id_present_map\n",
1741                                         mp_ioapics[apic].mpc_apicid);
1742                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
1743                 }
1744
1745
1746                 /*
1747                  * We need to adjust the IRQ routing table
1748                  * if the ID changed.
1749                  */
1750                 if (old_id != mp_ioapics[apic].mpc_apicid)
1751                         for (i = 0; i < mp_irq_entries; i++)
1752                                 if (mp_irqs[i].mpc_dstapic == old_id)
1753                                         mp_irqs[i].mpc_dstapic
1754                                                 = mp_ioapics[apic].mpc_apicid;
1755
1756                 /*
1757                  * Read the right value from the MPC table and
1758                  * write it into the ID register.
1759                  */
1760                 apic_printk(APIC_VERBOSE, KERN_INFO
1761                         "...changing IO-APIC physical APIC ID to %d ...",
1762                         mp_ioapics[apic].mpc_apicid);
1763
1764                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1765                 spin_lock_irqsave(&ioapic_lock, flags);
1766                 io_apic_write(apic, 0, reg_00.raw);
1767                 spin_unlock_irqrestore(&ioapic_lock, flags);
1768
1769                 /*
1770                  * Sanity check
1771                  */
1772                 spin_lock_irqsave(&ioapic_lock, flags);
1773                 reg_00.raw = io_apic_read(apic, 0);
1774                 spin_unlock_irqrestore(&ioapic_lock, flags);
1775                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1776                         printk("could not set ID!\n");
1777                 else
1778                         apic_printk(APIC_VERBOSE, " ok.\n");
1779         }
1780 }
1781 #else
1782 static void __init setup_ioapic_ids_from_mpc(void) { }
1783 #endif
1784
1785 /*
1786  * There is a nasty bug in some older SMP boards, their mptable lies
1787  * about the timer IRQ. We do the following to work around the situation:
1788  *
1789  *      - timer IRQ defaults to IO-APIC IRQ
1790  *      - if this function detects that timer IRQs are defunct, then we fall
1791  *        back to ISA timer IRQs
1792  */
1793 static int __init timer_irq_works(void)
1794 {
1795         unsigned long t1 = jiffies;
1796
1797         local_irq_enable();
1798         /* Let ten ticks pass... */
1799         mdelay((10 * 1000) / HZ);
1800
1801         /*
1802          * Expect a few ticks at least, to be sure some possible
1803          * glue logic does not lock up after one or two first
1804          * ticks in a non-ExtINT mode.  Also the local APIC
1805          * might have cached one ExtINT interrupt.  Finally, at
1806          * least one tick may be lost due to delays.
1807          */
1808         if (jiffies - t1 > 4)
1809                 return 1;
1810
1811         return 0;
1812 }
1813
1814 /*
1815  * In the SMP+IOAPIC case it might happen that there are an unspecified
1816  * number of pending IRQ events unhandled. These cases are very rare,
1817  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1818  * better to do it this way as thus we do not have to be aware of
1819  * 'pending' interrupts in the IRQ path, except at this point.
1820  */
1821 /*
1822  * Edge triggered needs to resend any interrupt
1823  * that was delayed but this is now handled in the device
1824  * independent code.
1825  */
1826
1827 /*
1828  * Starting up a edge-triggered IO-APIC interrupt is
1829  * nasty - we need to make sure that we get the edge.
1830  * If it is already asserted for some reason, we need
1831  * return 1 to indicate that is was pending.
1832  *
1833  * This is not complete - we should be able to fake
1834  * an edge even if it isn't on the 8259A...
1835  */
1836 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1837 {
1838         int was_pending = 0;
1839         unsigned long flags;
1840
1841         spin_lock_irqsave(&ioapic_lock, flags);
1842         if (irq < 16) {
1843                 disable_8259A_irq(irq);
1844                 if (i8259A_irq_pending(irq))
1845                         was_pending = 1;
1846         }
1847         __unmask_IO_APIC_irq(irq);
1848         spin_unlock_irqrestore(&ioapic_lock, flags);
1849
1850         return was_pending;
1851 }
1852
1853 /*
1854  * Once we have recorded IRQ_PENDING already, we can mask the
1855  * interrupt for real. This prevents IRQ storms from unhandled
1856  * devices.
1857  */
1858 static void ack_edge_ioapic_irq(unsigned int irq)
1859 {
1860         move_irq(irq);
1861         if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1862                                         == (IRQ_PENDING | IRQ_DISABLED))
1863                 mask_IO_APIC_irq(irq);
1864         ack_APIC_irq();
1865 }
1866
1867 /*
1868  * Level triggered interrupts can just be masked,
1869  * and shutting down and starting up the interrupt
1870  * is the same as enabling and disabling them -- except
1871  * with a startup need to return a "was pending" value.
1872  *
1873  * Level triggered interrupts are special because we
1874  * do not touch any IO-APIC register while handling
1875  * them. We ack the APIC in the end-IRQ handler, not
1876  * in the start-IRQ-handler. Protection against reentrance
1877  * from the same interrupt is still provided, both by the
1878  * generic IRQ layer and by the fact that an unacked local
1879  * APIC does not accept IRQs.
1880  */
1881 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1882 {
1883         unmask_IO_APIC_irq(irq);
1884
1885         return 0; /* don't check for pending */
1886 }
1887
1888 static void end_level_ioapic_irq (unsigned int irq)
1889 {
1890         unsigned long v;
1891         int i;
1892
1893         move_irq(irq);
1894 /*
1895  * It appears there is an erratum which affects at least version 0x11
1896  * of I/O APIC (that's the 82093AA and cores integrated into various
1897  * chipsets).  Under certain conditions a level-triggered interrupt is
1898  * erroneously delivered as edge-triggered one but the respective IRR
1899  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1900  * message but it will never arrive and further interrupts are blocked
1901  * from the source.  The exact reason is so far unknown, but the
1902  * phenomenon was observed when two consecutive interrupt requests
1903  * from a given source get delivered to the same CPU and the source is
1904  * temporarily disabled in between.
1905  *
1906  * A workaround is to simulate an EOI message manually.  We achieve it
1907  * by setting the trigger mode to edge and then to level when the edge
1908  * trigger mode gets detected in the TMR of a local APIC for a
1909  * level-triggered interrupt.  We mask the source for the time of the
1910  * operation to prevent an edge-triggered interrupt escaping meanwhile.
1911  * The idea is from Manfred Spraul.  --macro
1912  */
1913         i = IO_APIC_VECTOR(irq);
1914
1915         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1916
1917         ack_APIC_irq();
1918
1919         if (!(v & (1 << (i & 0x1f)))) {
1920                 atomic_inc(&irq_mis_count);
1921                 spin_lock(&ioapic_lock);
1922                 __mask_and_edge_IO_APIC_irq(irq);
1923                 __unmask_and_level_IO_APIC_irq(irq);
1924                 spin_unlock(&ioapic_lock);
1925         }
1926 }
1927
1928 #ifdef CONFIG_PCI_MSI
1929 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1930 {
1931         int irq = vector_to_irq(vector);
1932
1933         return startup_edge_ioapic_irq(irq);
1934 }
1935
1936 static void ack_edge_ioapic_vector(unsigned int vector)
1937 {
1938         int irq = vector_to_irq(vector);
1939
1940         move_irq(vector);
1941         ack_edge_ioapic_irq(irq);
1942 }
1943
1944 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1945 {
1946         int irq = vector_to_irq(vector);
1947
1948         return startup_level_ioapic_irq (irq);
1949 }
1950
1951 static void end_level_ioapic_vector (unsigned int vector)
1952 {
1953         int irq = vector_to_irq(vector);
1954
1955         move_irq(vector);
1956         end_level_ioapic_irq(irq);
1957 }
1958
1959 static void mask_IO_APIC_vector (unsigned int vector)
1960 {
1961         int irq = vector_to_irq(vector);
1962
1963         mask_IO_APIC_irq(irq);
1964 }
1965
1966 static void unmask_IO_APIC_vector (unsigned int vector)
1967 {
1968         int irq = vector_to_irq(vector);
1969
1970         unmask_IO_APIC_irq(irq);
1971 }
1972
1973 #ifdef CONFIG_SMP
1974 static void set_ioapic_affinity_vector (unsigned int vector,
1975                                         cpumask_t cpu_mask)
1976 {
1977         int irq = vector_to_irq(vector);
1978
1979         set_native_irq_info(vector, cpu_mask);
1980         set_ioapic_affinity_irq(irq, cpu_mask);
1981 }
1982 #endif
1983 #endif
1984
1985 /*
1986  * Level and edge triggered IO-APIC interrupts need different handling,
1987  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1988  * handled with the level-triggered descriptor, but that one has slightly
1989  * more overhead. Level-triggered interrupts cannot be handled with the
1990  * edge-triggered handler, without risking IRQ storms and other ugly
1991  * races.
1992  */
1993 static struct hw_interrupt_type ioapic_edge_type __read_mostly = {
1994         .typename       = "IO-APIC-edge",
1995         .startup        = startup_edge_ioapic,
1996         .shutdown       = shutdown_edge_ioapic,
1997         .enable         = enable_edge_ioapic,
1998         .disable        = disable_edge_ioapic,
1999         .ack            = ack_edge_ioapic,
2000         .end            = end_edge_ioapic,
2001 #ifdef CONFIG_SMP
2002         .set_affinity   = set_ioapic_affinity,
2003 #endif
2004 };
2005
2006 static struct hw_interrupt_type ioapic_level_type __read_mostly = {
2007         .typename       = "IO-APIC-level",
2008         .startup        = startup_level_ioapic,
2009         .shutdown       = shutdown_level_ioapic,
2010         .enable         = enable_level_ioapic,
2011         .disable        = disable_level_ioapic,
2012         .ack            = mask_and_ack_level_ioapic,
2013         .end            = end_level_ioapic,
2014 #ifdef CONFIG_SMP
2015         .set_affinity   = set_ioapic_affinity,
2016 #endif
2017 };
2018
2019 static inline void init_IO_APIC_traps(void)
2020 {
2021         int irq;
2022
2023         /*
2024          * NOTE! The local APIC isn't very good at handling
2025          * multiple interrupts at the same interrupt level.
2026          * As the interrupt level is determined by taking the
2027          * vector number and shifting that right by 4, we
2028          * want to spread these out a bit so that they don't
2029          * all fall in the same interrupt level.
2030          *
2031          * Also, we've got to be careful not to trash gate
2032          * 0x80, because int 0x80 is hm, kind of importantish. ;)
2033          */
2034         for (irq = 0; irq < NR_IRQS ; irq++) {
2035                 int tmp = irq;
2036                 if (use_pci_vector()) {
2037                         if (!platform_legacy_irq(tmp))
2038                                 if ((tmp = vector_to_irq(tmp)) == -1)
2039                                         continue;
2040                 }
2041                 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
2042                         /*
2043                          * Hmm.. We don't have an entry for this,
2044                          * so default to an old-fashioned 8259
2045                          * interrupt if we can..
2046                          */
2047                         if (irq < 16)
2048                                 make_8259A_irq(irq);
2049                         else
2050                                 /* Strange. Oh, well.. */
2051                                 irq_desc[irq].handler = &no_irq_type;
2052                 }
2053         }
2054 }
2055
2056 static void enable_lapic_irq (unsigned int irq)
2057 {
2058         unsigned long v;
2059
2060         v = apic_read(APIC_LVT0);
2061         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2062 }
2063
2064 static void disable_lapic_irq (unsigned int irq)
2065 {
2066         unsigned long v;
2067
2068         v = apic_read(APIC_LVT0);
2069         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2070 }
2071
2072 static void ack_lapic_irq (unsigned int irq)
2073 {
2074         ack_APIC_irq();
2075 }
2076
2077 static void end_lapic_irq (unsigned int i) { /* nothing */ }
2078
2079 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
2080         .typename       = "local-APIC-edge",
2081         .startup        = NULL, /* startup_irq() not used for IRQ0 */
2082         .shutdown       = NULL, /* shutdown_irq() not used for IRQ0 */
2083         .enable         = enable_lapic_irq,
2084         .disable        = disable_lapic_irq,
2085         .ack            = ack_lapic_irq,
2086         .end            = end_lapic_irq
2087 };
2088
2089 static void setup_nmi (void)
2090 {
2091         /*
2092          * Dirty trick to enable the NMI watchdog ...
2093          * We put the 8259A master into AEOI mode and
2094          * unmask on all local APICs LVT0 as NMI.
2095          *
2096          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2097          * is from Maciej W. Rozycki - so we do not have to EOI from
2098          * the NMI handler or the timer interrupt.
2099          */
2100         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2101
2102         on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
2103
2104         apic_printk(APIC_VERBOSE, " done.\n");
2105 }
2106
2107 /*
2108  * This looks a bit hackish but it's about the only one way of sending
2109  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2110  * not support the ExtINT mode, unfortunately.  We need to send these
2111  * cycles as some i82489DX-based boards have glue logic that keeps the
2112  * 8259A interrupt line asserted until INTA.  --macro
2113  */
2114 static inline void unlock_ExtINT_logic(void)
2115 {
2116         int pin, i;
2117         struct IO_APIC_route_entry entry0, entry1;
2118         unsigned char save_control, save_freq_select;
2119         unsigned long flags;
2120
2121         pin = find_isa_irq_pin(8, mp_INT);
2122         if (pin == -1)
2123                 return;
2124
2125         spin_lock_irqsave(&ioapic_lock, flags);
2126         *(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin);
2127         *(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin);
2128         spin_unlock_irqrestore(&ioapic_lock, flags);
2129         clear_IO_APIC_pin(0, pin);
2130
2131         memset(&entry1, 0, sizeof(entry1));
2132
2133         entry1.dest_mode = 0;                   /* physical delivery */
2134         entry1.mask = 0;                        /* unmask IRQ now */
2135         entry1.dest.physical.physical_dest = hard_smp_processor_id();
2136         entry1.delivery_mode = dest_ExtINT;
2137         entry1.polarity = entry0.polarity;
2138         entry1.trigger = 0;
2139         entry1.vector = 0;
2140
2141         spin_lock_irqsave(&ioapic_lock, flags);
2142         io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
2143         io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
2144         spin_unlock_irqrestore(&ioapic_lock, flags);
2145
2146         save_control = CMOS_READ(RTC_CONTROL);
2147         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2148         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2149                    RTC_FREQ_SELECT);
2150         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2151
2152         i = 100;
2153         while (i-- > 0) {
2154                 mdelay(10);
2155                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2156                         i -= 10;
2157         }
2158
2159         CMOS_WRITE(save_control, RTC_CONTROL);
2160         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2161         clear_IO_APIC_pin(0, pin);
2162
2163         spin_lock_irqsave(&ioapic_lock, flags);
2164         io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
2165         io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
2166         spin_unlock_irqrestore(&ioapic_lock, flags);
2167 }
2168
2169 /*
2170  * This code may look a bit paranoid, but it's supposed to cooperate with
2171  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2172  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2173  * fanatically on his truly buggy board.
2174  */
2175 static inline void check_timer(void)
2176 {
2177         int pin1, pin2;
2178         int vector;
2179
2180         /*
2181          * get/set the timer IRQ vector:
2182          */
2183         disable_8259A_irq(0);
2184         vector = assign_irq_vector(0);
2185         set_intr_gate(vector, interrupt[0]);
2186
2187         /*
2188          * Subtle, code in do_timer_interrupt() expects an AEOI
2189          * mode for the 8259A whenever interrupts are routed
2190          * through I/O APICs.  Also IRQ0 has to be enabled in
2191          * the 8259A which implies the virtual wire has to be
2192          * disabled in the local APIC.
2193          */
2194         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2195         init_8259A(1);
2196         timer_ack = 1;
2197         enable_8259A_irq(0);
2198
2199         pin1 = find_isa_irq_pin(0, mp_INT);
2200         pin2 = find_isa_irq_pin(0, mp_ExtINT);
2201
2202         printk(KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2);
2203
2204         if (pin1 != -1) {
2205                 /*
2206                  * Ok, does IRQ0 through the IOAPIC work?
2207                  */
2208                 unmask_IO_APIC_irq(0);
2209                 if (timer_irq_works()) {
2210                         if (nmi_watchdog == NMI_IO_APIC) {
2211                                 disable_8259A_irq(0);
2212                                 setup_nmi();
2213                                 enable_8259A_irq(0);
2214                         }
2215                         return;
2216                 }
2217                 clear_IO_APIC_pin(0, pin1);
2218                 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
2219         }
2220
2221         printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2222         if (pin2 != -1) {
2223                 printk("\n..... (found pin %d) ...", pin2);
2224                 /*
2225                  * legacy devices should be connected to IO APIC #0
2226                  */
2227                 setup_ExtINT_IRQ0_pin(pin2, vector);
2228                 if (timer_irq_works()) {
2229                         printk("works.\n");
2230                         if (pin1 != -1)
2231                                 replace_pin_at_irq(0, 0, pin1, 0, pin2);
2232                         else
2233                                 add_pin_to_irq(0, 0, pin2);
2234                         if (nmi_watchdog == NMI_IO_APIC) {
2235                                 setup_nmi();
2236                         }
2237                         return;
2238                 }
2239                 /*
2240                  * Cleanup, just in case ...
2241                  */
2242                 clear_IO_APIC_pin(0, pin2);
2243         }
2244         printk(" failed.\n");
2245
2246         if (nmi_watchdog == NMI_IO_APIC) {
2247                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2248                 nmi_watchdog = 0;
2249         }
2250
2251         printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2252
2253         disable_8259A_irq(0);
2254         irq_desc[0].handler = &lapic_irq_type;
2255         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
2256         enable_8259A_irq(0);
2257
2258         if (timer_irq_works()) {
2259                 printk(" works.\n");
2260                 return;
2261         }
2262         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2263         printk(" failed.\n");
2264
2265         printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2266
2267         timer_ack = 0;
2268         init_8259A(0);
2269         make_8259A_irq(0);
2270         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2271
2272         unlock_ExtINT_logic();
2273
2274         if (timer_irq_works()) {
2275                 printk(" works.\n");
2276                 return;
2277         }
2278         printk(" failed :(.\n");
2279         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2280                 "report.  Then try booting with the 'noapic' option");
2281 }
2282
2283 /*
2284  *
2285  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2286  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2287  *   Linux doesn't really care, as it's not actually used
2288  *   for any interrupt handling anyway.
2289  */
2290 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
2291
2292 void __init setup_IO_APIC(void)
2293 {
2294         enable_IO_APIC();
2295
2296         if (acpi_ioapic)
2297                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
2298         else
2299                 io_apic_irqs = ~PIC_IRQS;
2300
2301         printk("ENABLING IO-APIC IRQs\n");
2302
2303         /*
2304          * Set up IO-APIC IRQ routing.
2305          */
2306         if (!acpi_ioapic)
2307                 setup_ioapic_ids_from_mpc();
2308         sync_Arb_IDs();
2309         setup_IO_APIC_irqs();
2310         init_IO_APIC_traps();
2311         check_timer();
2312         if (!acpi_ioapic)
2313                 print_IO_APIC();
2314 }
2315
2316 /*
2317  *      Called after all the initialization is done. If we didnt find any
2318  *      APIC bugs then we can allow the modify fast path
2319  */
2320
2321 static int __init io_apic_bug_finalize(void)
2322 {
2323         if(sis_apic_bug == -1)
2324                 sis_apic_bug = 0;
2325         return 0;
2326 }
2327
2328 late_initcall(io_apic_bug_finalize);
2329
2330 struct sysfs_ioapic_data {
2331         struct sys_device dev;
2332         struct IO_APIC_route_entry entry[0];
2333 };
2334 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2335
2336 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2337 {
2338         struct IO_APIC_route_entry *entry;
2339         struct sysfs_ioapic_data *data;
2340         unsigned long flags;
2341         int i;
2342
2343         data = container_of(dev, struct sysfs_ioapic_data, dev);
2344         entry = data->entry;
2345         spin_lock_irqsave(&ioapic_lock, flags);
2346         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2347                 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
2348                 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
2349         }
2350         spin_unlock_irqrestore(&ioapic_lock, flags);
2351
2352         return 0;
2353 }
2354
2355 static int ioapic_resume(struct sys_device *dev)
2356 {
2357         struct IO_APIC_route_entry *entry;
2358         struct sysfs_ioapic_data *data;
2359         unsigned long flags;
2360         union IO_APIC_reg_00 reg_00;
2361         int i;
2362
2363         data = container_of(dev, struct sysfs_ioapic_data, dev);
2364         entry = data->entry;
2365
2366         spin_lock_irqsave(&ioapic_lock, flags);
2367         reg_00.raw = io_apic_read(dev->id, 0);
2368         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2369                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2370                 io_apic_write(dev->id, 0, reg_00.raw);
2371         }
2372         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2373                 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
2374                 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
2375         }
2376         spin_unlock_irqrestore(&ioapic_lock, flags);
2377
2378         return 0;
2379 }
2380
2381 static struct sysdev_class ioapic_sysdev_class = {
2382         set_kset_name("ioapic"),
2383         .suspend = ioapic_suspend,
2384         .resume = ioapic_resume,
2385 };
2386
2387 static int __init ioapic_init_sysfs(void)
2388 {
2389         struct sys_device * dev;
2390         int i, size, error = 0;
2391
2392         error = sysdev_class_register(&ioapic_sysdev_class);
2393         if (error)
2394                 return error;
2395
2396         for (i = 0; i < nr_ioapics; i++ ) {
2397                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2398                         * sizeof(struct IO_APIC_route_entry);
2399                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2400                 if (!mp_ioapic_data[i]) {
2401                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2402                         continue;
2403                 }
2404                 memset(mp_ioapic_data[i], 0, size);
2405                 dev = &mp_ioapic_data[i]->dev;
2406                 dev->id = i;
2407                 dev->cls = &ioapic_sysdev_class;
2408                 error = sysdev_register(dev);
2409                 if (error) {
2410                         kfree(mp_ioapic_data[i]);
2411                         mp_ioapic_data[i] = NULL;
2412                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2413                         continue;
2414                 }
2415         }
2416
2417         return 0;
2418 }
2419
2420 device_initcall(ioapic_init_sysfs);
2421
2422 /* --------------------------------------------------------------------------
2423                           ACPI-based IOAPIC Configuration
2424    -------------------------------------------------------------------------- */
2425
2426 #ifdef CONFIG_ACPI
2427
2428 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2429 {
2430         union IO_APIC_reg_00 reg_00;
2431         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2432         physid_mask_t tmp;
2433         unsigned long flags;
2434         int i = 0;
2435
2436         /*
2437          * The P4 platform supports up to 256 APIC IDs on two separate APIC
2438          * buses (one for LAPICs, one for IOAPICs), where predecessors only
2439          * supports up to 16 on one shared APIC bus.
2440          *
2441          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2442          *      advantage of new APIC bus architecture.
2443          */
2444
2445         if (physids_empty(apic_id_map))
2446                 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2447
2448         spin_lock_irqsave(&ioapic_lock, flags);
2449         reg_00.raw = io_apic_read(ioapic, 0);
2450         spin_unlock_irqrestore(&ioapic_lock, flags);
2451
2452         if (apic_id >= get_physical_broadcast()) {
2453                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2454                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
2455                 apic_id = reg_00.bits.ID;
2456         }
2457
2458         /*
2459          * Every APIC in a system must have a unique ID or we get lots of nice
2460          * 'stuck on smp_invalidate_needed IPI wait' messages.
2461          */
2462         if (check_apicid_used(apic_id_map, apic_id)) {
2463
2464                 for (i = 0; i < get_physical_broadcast(); i++) {
2465                         if (!check_apicid_used(apic_id_map, i))
2466                                 break;
2467                 }
2468
2469                 if (i == get_physical_broadcast())
2470                         panic("Max apic_id exceeded!\n");
2471
2472                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2473                         "trying %d\n", ioapic, apic_id, i);
2474
2475                 apic_id = i;
2476         }
2477
2478         tmp = apicid_to_cpu_present(apic_id);
2479         physids_or(apic_id_map, apic_id_map, tmp);
2480
2481         if (reg_00.bits.ID != apic_id) {
2482                 reg_00.bits.ID = apic_id;
2483
2484                 spin_lock_irqsave(&ioapic_lock, flags);
2485                 io_apic_write(ioapic, 0, reg_00.raw);
2486                 reg_00.raw = io_apic_read(ioapic, 0);
2487                 spin_unlock_irqrestore(&ioapic_lock, flags);
2488
2489                 /* Sanity check */
2490                 if (reg_00.bits.ID != apic_id)
2491                         panic("IOAPIC[%d]: Unable change apic_id!\n", ioapic);
2492         }
2493
2494         apic_printk(APIC_VERBOSE, KERN_INFO
2495                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2496
2497         return apic_id;
2498 }
2499
2500
2501 int __init io_apic_get_version (int ioapic)
2502 {
2503         union IO_APIC_reg_01    reg_01;
2504         unsigned long flags;
2505
2506         spin_lock_irqsave(&ioapic_lock, flags);
2507         reg_01.raw = io_apic_read(ioapic, 1);
2508         spin_unlock_irqrestore(&ioapic_lock, flags);
2509
2510         return reg_01.bits.version;
2511 }
2512
2513
2514 int __init io_apic_get_redir_entries (int ioapic)
2515 {
2516         union IO_APIC_reg_01    reg_01;
2517         unsigned long flags;
2518
2519         spin_lock_irqsave(&ioapic_lock, flags);
2520         reg_01.raw = io_apic_read(ioapic, 1);
2521         spin_unlock_irqrestore(&ioapic_lock, flags);
2522
2523         return reg_01.bits.entries;
2524 }
2525
2526
2527 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2528 {
2529         struct IO_APIC_route_entry entry;
2530         unsigned long flags;
2531
2532         if (!IO_APIC_IRQ(irq)) {
2533                 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2534                         ioapic);
2535                 return -EINVAL;
2536         }
2537
2538         /*
2539          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2540          * Note that we mask (disable) IRQs now -- these get enabled when the
2541          * corresponding device driver registers for this IRQ.
2542          */
2543
2544         memset(&entry,0,sizeof(entry));
2545
2546         entry.delivery_mode = INT_DELIVERY_MODE;
2547         entry.dest_mode = INT_DEST_MODE;
2548         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2549         entry.trigger = edge_level;
2550         entry.polarity = active_high_low;
2551         entry.mask  = 1;
2552
2553         /*
2554          * IRQs < 16 are already in the irq_2_pin[] map
2555          */
2556         if (irq >= 16)
2557                 add_pin_to_irq(irq, ioapic, pin);
2558
2559         entry.vector = assign_irq_vector(irq);
2560
2561         apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2562                 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2563                 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2564                 edge_level, active_high_low);
2565
2566         ioapic_register_intr(irq, entry.vector, edge_level);
2567
2568         if (!ioapic && (irq < 16))
2569                 disable_8259A_irq(irq);
2570
2571         spin_lock_irqsave(&ioapic_lock, flags);
2572         io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2573         io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2574         set_native_irq_info(use_pci_vector() ? entry.vector : irq, TARGET_CPUS);
2575         spin_unlock_irqrestore(&ioapic_lock, flags);
2576
2577         return 0;
2578 }
2579
2580 #endif /* CONFIG_ACPI */