arch/i386/kernel/cpu/cpufreq/speedstep-centrino.c

   1 /*
   2  * cpufreq driver for Enhanced SpeedStep, as found in Intel's Pentium
   3  * M (part of the Centrino chipset).
   4  *
   5  * Since the original Pentium M, most new Intel CPUs support Enhanced
   6  * SpeedStep.
   7  *
   8  * Despite the "SpeedStep" in the name, this is almost entirely unlike
   9  * traditional SpeedStep.
  10  *
  11  * Modelled on speedstep.c
  12  *
  13  * Copyright (C) 2003 Jeremy Fitzhardinge <jeremy@goop.org>
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/init.h>
  19 #include <linux/cpufreq.h>
  20 #include <linux/config.h>
  21 #include <linux/sched.h>        /* current */
  22 #include <linux/delay.h>
  23 #include <linux/compiler.h>
  24
  25 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
  26 #include <linux/acpi.h>
  27 #include <acpi/processor.h>
  28 #endif
  29
  30 #include <asm/msr.h>
  31 #include <asm/processor.h>
  32 #include <asm/cpufeature.h>
  33
  34 #define PFX             "speedstep-centrino: "
  35 #define MAINTAINER      "cpufreq@lists.linux.org.uk"
  36
  37 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "speedstep-centrino", msg)
  38
  39
  40 struct cpu_id
  41 {
  42         __u8    x86;            /* CPU family */
  43         __u8    x86_model;      /* model */
  44         __u8    x86_mask;       /* stepping */
  45 };
  46
  47 enum {
  48         CPU_BANIAS,
  49         CPU_DOTHAN_A1,
  50         CPU_DOTHAN_A2,
  51         CPU_DOTHAN_B0,
  52         CPU_MP4HT_D0,
  53         CPU_MP4HT_E0,
  54 };
  55
  56 static const struct cpu_id cpu_ids[] = {
  57         [CPU_BANIAS]    = { 6,  9, 5 },
  58         [CPU_DOTHAN_A1] = { 6, 13, 1 },
  59         [CPU_DOTHAN_A2] = { 6, 13, 2 },
  60         [CPU_DOTHAN_B0] = { 6, 13, 6 },
  61         [CPU_MP4HT_D0]  = {15,  3, 4 },
  62         [CPU_MP4HT_E0]  = {15,  4, 1 },
  63 };
  64 #define N_IDS   ARRAY_SIZE(cpu_ids)
  65
  66 struct cpu_model
  67 {
  68         const struct cpu_id *cpu_id;
  69         const char      *model_name;
  70         unsigned        max_freq; /* max clock in kHz */
  71
  72         struct cpufreq_frequency_table *op_points; /* clock/voltage pairs */
  73 };
  74 static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c, const struct cpu_id *x);
  75
  76 /* Operating points for current CPU */
  77 static struct cpu_model *centrino_model[NR_CPUS];
  78 static const struct cpu_id *centrino_cpu[NR_CPUS];
  79
  80 static struct cpufreq_driver centrino_driver;
  81
  82 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE
  83
  84 /* Computes the correct form for IA32_PERF_CTL MSR for a particular
  85    frequency/voltage operating point; frequency in MHz, volts in mV.
  86    This is stored as "index" in the structure. */
  87 #define OP(mhz, mv)                                                     \
  88         {                                                               \
  89                 .frequency = (mhz) * 1000,                              \
  90                 .index = (((mhz)/100) << 8) | ((mv - 700) / 16)         \
  91         }
  92
  93 /*
  94  * These voltage tables were derived from the Intel Pentium M
  95  * datasheet, document 25261202.pdf, Table 5.  I have verified they
  96  * are consistent with my IBM ThinkPad X31, which has a 1.3GHz Pentium
  97  * M.
  98  */
  99
 100 /* Ultra Low Voltage Intel Pentium M processor 900MHz (Banias) */
 101 static struct cpufreq_frequency_table banias_900[] =
 102 {
 103         OP(600,  844),
 104         OP(800,  988),
 105         OP(900, 1004),
 106         { .frequency = CPUFREQ_TABLE_END }
 107 };
 108
 109 /* Ultra Low Voltage Intel Pentium M processor 1000MHz (Banias) */
 110 static struct cpufreq_frequency_table banias_1000[] =
 111 {
 112         OP(600,   844),
 113         OP(800,   972),
 114         OP(900,   988),
 115         OP(1000, 1004),
 116         { .frequency = CPUFREQ_TABLE_END }
 117 };
 118
 119 /* Low Voltage Intel Pentium M processor 1.10GHz (Banias) */
 120 static struct cpufreq_frequency_table banias_1100[] =
 121 {
 122         OP( 600,  956),
 123         OP( 800, 1020),
 124         OP( 900, 1100),
 125         OP(1000, 1164),
 126         OP(1100, 1180),
 127         { .frequency = CPUFREQ_TABLE_END }
 128 };
 129
 130
 131 /* Low Voltage Intel Pentium M processor 1.20GHz (Banias) */
 132 static struct cpufreq_frequency_table banias_1200[] =
 133 {
 134         OP( 600,  956),
 135         OP( 800, 1004),
 136         OP( 900, 1020),
 137         OP(1000, 1100),
 138         OP(1100, 1164),
 139         OP(1200, 1180),
 140         { .frequency = CPUFREQ_TABLE_END }
 141 };
 142
 143 /* Intel Pentium M processor 1.30GHz (Banias) */
 144 static struct cpufreq_frequency_table banias_1300[] =
 145 {
 146         OP( 600,  956),
 147         OP( 800, 1260),
 148         OP(1000, 1292),
 149         OP(1200, 1356),
 150         OP(1300, 1388),
 151         { .frequency = CPUFREQ_TABLE_END }
 152 };
 153
 154 /* Intel Pentium M processor 1.40GHz (Banias) */
 155 static struct cpufreq_frequency_table banias_1400[] =
 156 {
 157         OP( 600,  956),
 158         OP( 800, 1180),
 159         OP(1000, 1308),
 160         OP(1200, 1436),
 161         OP(1400, 1484),
 162         { .frequency = CPUFREQ_TABLE_END }
 163 };
 164
 165 /* Intel Pentium M processor 1.50GHz (Banias) */
 166 static struct cpufreq_frequency_table banias_1500[] =
 167 {
 168         OP( 600,  956),
 169         OP( 800, 1116),
 170         OP(1000, 1228),
 171         OP(1200, 1356),
 172         OP(1400, 1452),
 173         OP(1500, 1484),
 174         { .frequency = CPUFREQ_TABLE_END }
 175 };
 176
 177 /* Intel Pentium M processor 1.60GHz (Banias) */
 178 static struct cpufreq_frequency_table banias_1600[] =
 179 {
 180         OP( 600,  956),
 181         OP( 800, 1036),
 182         OP(1000, 1164),
 183         OP(1200, 1276),
 184         OP(1400, 1420),
 185         OP(1600, 1484),
 186         { .frequency = CPUFREQ_TABLE_END }
 187 };
 188
 189 /* Intel Pentium M processor 1.70GHz (Banias) */
 190 static struct cpufreq_frequency_table banias_1700[] =
 191 {
 192         OP( 600,  956),
 193         OP( 800, 1004),
 194         OP(1000, 1116),
 195         OP(1200, 1228),
 196         OP(1400, 1308),
 197         OP(1700, 1484),
 198         { .frequency = CPUFREQ_TABLE_END }
 199 };
 200 #undef OP
 201
 202 #define _BANIAS(cpuid, max, name)       \
 203 {       .cpu_id         = cpuid,        \
 204         .model_name     = "Intel(R) Pentium(R) M processor " name "MHz", \
 205         .max_freq       = (max)*1000,   \
 206         .op_points      = banias_##max, \
 207 }
 208 #define BANIAS(max)     _BANIAS(&cpu_ids[CPU_BANIAS], max, #max)
 209
 210 /* CPU models, their operating frequency range, and freq/voltage
 211    operating points */
 212 static struct cpu_model models[] =
 213 {
 214         _BANIAS(&cpu_ids[CPU_BANIAS], 900, " 900"),
 215         BANIAS(1000),
 216         BANIAS(1100),
 217         BANIAS(1200),
 218         BANIAS(1300),
 219         BANIAS(1400),
 220         BANIAS(1500),
 221         BANIAS(1600),
 222         BANIAS(1700),
 223
 224         /* NULL model_name is a wildcard */
 225         { &cpu_ids[CPU_DOTHAN_A1], NULL, 0, NULL },
 226         { &cpu_ids[CPU_DOTHAN_A2], NULL, 0, NULL },
 227         { &cpu_ids[CPU_DOTHAN_B0], NULL, 0, NULL },
 228         { &cpu_ids[CPU_MP4HT_D0], NULL, 0, NULL },
 229         { &cpu_ids[CPU_MP4HT_E0], NULL, 0, NULL },
 230
 231         { NULL, }
 232 };
 233 #undef _BANIAS
 234 #undef BANIAS
 235
 236 static int centrino_cpu_init_table(struct cpufreq_policy *policy)
 237 {
 238         struct cpuinfo_x86 *cpu = &cpu_data[policy->cpu];
 239         struct cpu_model *model;
 240
 241         for(model = models; model->cpu_id != NULL; model++)
 242                 if (centrino_verify_cpu_id(cpu, model->cpu_id) &&
 243                     (model->model_name == NULL ||
 244                      strcmp(cpu->x86_model_id, model->model_name) == 0))
 245                         break;
 246
 247         if (model->cpu_id == NULL) {
 248                 /* No match at all */
 249                 dprintk("no support for CPU model \"%s\": "
 250                        "send /proc/cpuinfo to " MAINTAINER "\n",
 251                        cpu->x86_model_id);
 252                 return -ENOENT;
 253         }
 254
 255         if (model->op_points == NULL) {
 256                 /* Matched a non-match */
 257                 dprintk("no table support for CPU model \"%s\"\n",
 258                        cpu->x86_model_id);
 259 #ifndef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
 260                 dprintk("try compiling with CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI enabled\n");
 261 #endif
 262                 return -ENOENT;
 263         }
 264
 265         centrino_model[policy->cpu] = model;
 266
 267         dprintk("found \"%s\": max frequency: %dkHz\n",
 268                model->model_name, model->max_freq);
 269
 270         return 0;
 271 }
 272
 273 #else
 274 static inline int centrino_cpu_init_table(struct cpufreq_policy *policy) { return -ENODEV; }
 275 #endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE */
 276
 277 static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c, const struct cpu_id *x)
 278 {
 279         if ((c->x86 == x->x86) &&
 280             (c->x86_model == x->x86_model) &&
 281             (c->x86_mask == x->x86_mask))
 282                 return 1;
 283         return 0;
 284 }
 285
 286 /* To be called only after centrino_model is initialized */
 287 static unsigned extract_clock(unsigned msr, unsigned int cpu, int failsafe)
 288 {
 289         int i;
 290
 291         /*
 292          * Extract clock in kHz from PERF_CTL value
 293          * for centrino, as some DSDTs are buggy.
 294          * Ideally, this can be done using the acpi_data structure.
 295          */
 296         if ((centrino_cpu[cpu] == &cpu_ids[CPU_BANIAS]) ||
 297             (centrino_cpu[cpu] == &cpu_ids[CPU_DOTHAN_A1]) ||
 298             (centrino_cpu[cpu] == &cpu_ids[CPU_DOTHAN_B0])) {
 299                 msr = (msr >> 8) & 0xff;
 300                 return msr * 100000;
 301         }
 302
 303         if ((!centrino_model[cpu]) || (!centrino_model[cpu]->op_points))
 304                 return 0;
 305
 306         msr &= 0xffff;
 307         for (i=0;centrino_model[cpu]->op_points[i].frequency != CPUFREQ_TABLE_END; i++) {
 308                 if (msr == centrino_model[cpu]->op_points[i].index)
 309                         return centrino_model[cpu]->op_points[i].frequency;
 310         }
 311         if (failsafe)
 312                 return centrino_model[cpu]->op_points[i-1].frequency;
 313         else
 314                 return 0;
 315 }
 316
 317 /* Return the current CPU frequency in kHz */
 318 static unsigned int get_cur_freq(unsigned int cpu)
 319 {
 320         unsigned l, h;
 321         unsigned clock_freq;
 322         cpumask_t saved_mask;
 323
 324         saved_mask = current->cpus_allowed;
 325         set_cpus_allowed(current, cpumask_of_cpu(cpu));
 326         if (smp_processor_id() != cpu)
 327                 return 0;
 328
 329         rdmsr(MSR_IA32_PERF_STATUS, l, h);
 330         clock_freq = extract_clock(l, cpu, 0);
 331
 332         if (unlikely(clock_freq == 0)) {
 333                 /*
 334                  * On some CPUs, we can see transient MSR values (which are
 335                  * not present in _PSS), while CPU is doing some automatic
 336                  * P-state transition (like TM2). Get the last freq set
 337                  * in PERF_CTL.
 338                  */
 339                 rdmsr(MSR_IA32_PERF_CTL, l, h);
 340                 clock_freq = extract_clock(l, cpu, 1);
 341         }
 342
 343         set_cpus_allowed(current, saved_mask);
 344         return clock_freq;
 345 }
 346
 347
 348 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
 349
 350 static struct acpi_processor_performance *acpi_perf_data[NR_CPUS];
 351
 352 /*
 353  * centrino_cpu_early_init_acpi - Do the preregistering with ACPI P-States
 354  * library
 355  *
 356  * Before doing the actual init, we need to do _PSD related setup whenever
 357  * supported by the BIOS. These are handled by this early_init routine.
 358  */
 359 static int centrino_cpu_early_init_acpi(void)
 360 {
 361         unsigned int    i, j;
 362         struct acpi_processor_performance       *data;
 363
 364         for_each_possible_cpu(i) {
 365                 data = kzalloc(sizeof(struct acpi_processor_performance),
 366                                 GFP_KERNEL);
 367                 if (!data) {
 368                         for_each_possible_cpu(j) {
 369                                 kfree(acpi_perf_data[j]);
 370                                 acpi_perf_data[j] = NULL;
 371                         }
 372                         return (-ENOMEM);
 373                 }
 374                 acpi_perf_data[i] = data;
 375         }
 376
 377         acpi_processor_preregister_performance(acpi_perf_data);
 378         return 0;
 379 }
 380
 381 /*
 382  * centrino_cpu_init_acpi - register with ACPI P-States library
 383  *
 384  * Register with the ACPI P-States library (part of drivers/acpi/processor.c)
 385  * in order to determine correct frequency and voltage pairings by reading
 386  * the _PSS of the ACPI DSDT or SSDT tables.
 387  */
 388 static int centrino_cpu_init_acpi(struct cpufreq_policy *policy)
 389 {
 390         unsigned long                   cur_freq;
 391         int                             result = 0, i;
 392         unsigned int                    cpu = policy->cpu;
 393         struct acpi_processor_performance       *p;
 394
 395         p = acpi_perf_data[cpu];
 396
 397         /* register with ACPI core */
 398         if (acpi_processor_register_performance(p, cpu)) {
 399                 dprintk(PFX "obtaining ACPI data failed\n");
 400                 return -EIO;
 401         }
 402         policy->cpus = p->shared_cpu_map;
 403         policy->shared_type = p->shared_type;
 404
 405         /* verify the acpi_data */
 406         if (p->state_count <= 1) {
 407                 dprintk("No P-States\n");
 408                 result = -ENODEV;
 409                 goto err_unreg;
 410         }
 411
 412         if ((p->control_register.space_id != ACPI_ADR_SPACE_FIXED_HARDWARE) ||
 413             (p->status_register.space_id != ACPI_ADR_SPACE_FIXED_HARDWARE)) {
 414                 dprintk("Invalid control/status registers (%x - %x)\n",
 415                         p->control_register.space_id, p->status_register.space_id);
 416                 result = -EIO;
 417                 goto err_unreg;
 418         }
 419
 420         for (i=0; i<p->state_count; i++) {
 421                 if (p->states[i].control != p->states[i].status) {
 422                         dprintk("Different control (%llu) and status values (%llu)\n",
 423                                 p->states[i].control, p->states[i].status);
 424                         result = -EINVAL;
 425                         goto err_unreg;
 426                 }
 427
 428                 if (!p->states[i].core_frequency) {
 429                         dprintk("Zero core frequency for state %u\n", i);
 430                         result = -EINVAL;
 431                         goto err_unreg;
 432                 }
 433
 434                 if (p->states[i].core_frequency > p->states[0].core_frequency) {
 435                         dprintk("P%u has larger frequency (%llu) than P0 (%llu), skipping\n", i,
 436                                 p->states[i].core_frequency, p->states[0].core_frequency);
 437                         p->states[i].core_frequency = 0;
 438                         continue;
 439                 }
 440         }
 441
 442         centrino_model[cpu] = kzalloc(sizeof(struct cpu_model), GFP_KERNEL);
 443         if (!centrino_model[cpu]) {
 444                 result = -ENOMEM;
 445                 goto err_unreg;
 446         }
 447
 448         centrino_model[cpu]->model_name=NULL;
 449         centrino_model[cpu]->max_freq = p->states[0].core_frequency * 1000;
 450         centrino_model[cpu]->op_points =  kmalloc(sizeof(struct cpufreq_frequency_table) *
 451                                              (p->state_count + 1), GFP_KERNEL);
 452         if (!centrino_model[cpu]->op_points) {
 453                 result = -ENOMEM;
 454                 goto err_kfree;
 455         }
 456
 457         for (i=0; i<p->state_count; i++) {
 458                 centrino_model[cpu]->op_points[i].index = p->states[i].control;
 459                 centrino_model[cpu]->op_points[i].frequency = p->states[i].core_frequency * 1000;
 460                 dprintk("adding state %i with frequency %u and control value %04x\n",
 461                         i, centrino_model[cpu]->op_points[i].frequency, centrino_model[cpu]->op_points[i].index);
 462         }
 463         centrino_model[cpu]->op_points[p->state_count].frequency = CPUFREQ_TABLE_END;
 464
 465         cur_freq = get_cur_freq(cpu);
 466
 467         for (i=0; i<p->state_count; i++) {
 468                 if (!p->states[i].core_frequency) {
 469                         dprintk("skipping state %u\n", i);
 470                         centrino_model[cpu]->op_points[i].frequency = CPUFREQ_ENTRY_INVALID;
 471                         continue;
 472                 }
 473
 474                 if (extract_clock(centrino_model[cpu]->op_points[i].index, cpu, 0) !=
 475                     (centrino_model[cpu]->op_points[i].frequency)) {
 476                         dprintk("Invalid encoded frequency (%u vs. %u)\n",
 477                                 extract_clock(centrino_model[cpu]->op_points[i].index, cpu, 0),
 478                                 centrino_model[cpu]->op_points[i].frequency);
 479                         result = -EINVAL;
 480                         goto err_kfree_all;
 481                 }
 482
 483                 if (cur_freq == centrino_model[cpu]->op_points[i].frequency)
 484                         p->state = i;
 485         }
 486
 487         /* notify BIOS that we exist */
 488         acpi_processor_notify_smm(THIS_MODULE);
 489
 490         return 0;
 491
 492  err_kfree_all:
 493         kfree(centrino_model[cpu]->op_points);
 494  err_kfree:
 495         kfree(centrino_model[cpu]);
 496  err_unreg:
 497         acpi_processor_unregister_performance(p, cpu);
 498         dprintk(PFX "invalid ACPI data\n");
 499         return (result);
 500 }
 501 #else
 502 static inline int centrino_cpu_init_acpi(struct cpufreq_policy *policy) { return -ENODEV; }
 503 static inline int centrino_cpu_early_init_acpi(void) { return 0; }
 504 #endif
 505
 506 static int centrino_cpu_init(struct cpufreq_policy *policy)
 507 {
 508         struct cpuinfo_x86 *cpu = &cpu_data[policy->cpu];
 509         unsigned freq;
 510         unsigned l, h;
 511         int ret;
 512         int i;
 513
 514         /* Only Intel makes Enhanced Speedstep-capable CPUs */
 515         if (cpu->x86_vendor != X86_VENDOR_INTEL || !cpu_has(cpu, X86_FEATURE_EST))
 516                 return -ENODEV;
 517
 518         if (cpu_has(cpu, X86_FEATURE_CONSTANT_TSC))
 519                 centrino_driver.flags |= CPUFREQ_CONST_LOOPS;
 520
 521         if (centrino_cpu_init_acpi(policy)) {
 522                 if (policy->cpu != 0)
 523                         return -ENODEV;
 524
 525                 for (i = 0; i < N_IDS; i++)
 526                         if (centrino_verify_cpu_id(cpu, &cpu_ids[i]))
 527                                 break;
 528
 529                 if (i != N_IDS)
 530                         centrino_cpu[policy->cpu] = &cpu_ids[i];
 531
 532                 if (!centrino_cpu[policy->cpu]) {
 533                         dprintk("found unsupported CPU with "
 534                         "Enhanced SpeedStep: send /proc/cpuinfo to "
 535                         MAINTAINER "\n");
 536                         return -ENODEV;
 537                 }
 538
 539                 if (centrino_cpu_init_table(policy)) {
 540                         return -ENODEV;
 541                 }
 542         }
 543
 544         /* Check to see if Enhanced SpeedStep is enabled, and try to
 545            enable it if not. */
 546         rdmsr(MSR_IA32_MISC_ENABLE, l, h);
 547
 548         if (!(l & (1<<16))) {
 549                 l |= (1<<16);
 550                 dprintk("trying to enable Enhanced SpeedStep (%x)\n", l);
 551                 wrmsr(MSR_IA32_MISC_ENABLE, l, h);
 552
 553                 /* check to see if it stuck */
 554                 rdmsr(MSR_IA32_MISC_ENABLE, l, h);
 555                 if (!(l & (1<<16))) {
 556                         printk(KERN_INFO PFX "couldn't enable Enhanced SpeedStep\n");
 557                         return -ENODEV;
 558                 }
 559         }
 560
 561         freq = get_cur_freq(policy->cpu);
 562
 563         policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
 564         policy->cpuinfo.transition_latency = 10000; /* 10uS transition latency */
 565         policy->cur = freq;
 566
 567         dprintk("centrino_cpu_init: cur=%dkHz\n", policy->cur);
 568
 569         ret = cpufreq_frequency_table_cpuinfo(policy, centrino_model[policy->cpu]->op_points);
 570         if (ret)
 571                 return (ret);
 572
 573         cpufreq_frequency_table_get_attr(centrino_model[policy->cpu]->op_points, policy->cpu);
 574
 575         return 0;
 576 }
 577
 578 static int centrino_cpu_exit(struct cpufreq_policy *policy)
 579 {
 580         unsigned int cpu = policy->cpu;
 581
 582         if (!centrino_model[cpu])
 583                 return -ENODEV;
 584
 585         cpufreq_frequency_table_put_attr(cpu);
 586
 587 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
 588         if (!centrino_model[cpu]->model_name) {
 589                 static struct acpi_processor_performance *p;
 590
 591                 if (acpi_perf_data[cpu]) {
 592                         p = acpi_perf_data[cpu];
 593                         dprintk("unregistering and freeing ACPI data\n");
 594                         acpi_processor_unregister_performance(p, cpu);
 595                         kfree(centrino_model[cpu]->op_points);
 596                         kfree(centrino_model[cpu]);
 597                 }
 598         }
 599 #endif
 600
 601         centrino_model[cpu] = NULL;
 602
 603         return 0;
 604 }
 605
 606 /**
 607  * centrino_verify - verifies a new CPUFreq policy
 608  * @policy: new policy
 609  *
 610  * Limit must be within this model's frequency range at least one
 611  * border included.
 612  */
 613 static int centrino_verify (struct cpufreq_policy *policy)
 614 {
 615         return cpufreq_frequency_table_verify(policy, centrino_model[policy->cpu]->op_points);
 616 }
 617
 618 /**
 619  * centrino_setpolicy - set a new CPUFreq policy
 620  * @policy: new policy
 621  * @target_freq: the target frequency
 622  * @relation: how that frequency relates to achieved frequency (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H)
 623  *
 624  * Sets a new CPUFreq policy.
 625  */
 626 static int centrino_target (struct cpufreq_policy *policy,
 627                             unsigned int target_freq,
 628                             unsigned int relation)
 629 {
 630         unsigned int    newstate = 0;
 631         unsigned int    msr, oldmsr = 0, h = 0, cpu = policy->cpu;
 632         struct cpufreq_freqs    freqs;
 633         cpumask_t               online_policy_cpus;
 634         cpumask_t               saved_mask;
 635         cpumask_t               set_mask;
 636         cpumask_t               covered_cpus;
 637         int                     retval = 0;
 638         unsigned int            j, k, first_cpu, tmp;
 639
 640         if (unlikely(centrino_model[cpu] == NULL))
 641                 return -ENODEV;
 642
 643         if (unlikely(cpufreq_frequency_table_target(policy,
 644                         centrino_model[cpu]->op_points,
 645                         target_freq,
 646                         relation,
 647                         &newstate))) {
 648                 return -EINVAL;
 649         }
 650
 651 #ifdef CONFIG_HOTPLUG_CPU
 652         /* cpufreq holds the hotplug lock, so we are safe from here on */
 653         cpus_and(online_policy_cpus, cpu_online_map, policy->cpus);
 654 #else
 655         online_policy_cpus = policy->cpus;
 656 #endif
 657
 658         saved_mask = current->cpus_allowed;
 659         first_cpu = 1;
 660         cpus_clear(covered_cpus);
 661         for_each_cpu_mask(j, online_policy_cpus) {
 662                 /*
 663                  * Support for SMP systems.
 664                  * Make sure we are running on CPU that wants to change freq
 665                  */
 666                 cpus_clear(set_mask);
 667                 if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
 668                         cpus_or(set_mask, set_mask, online_policy_cpus);
 669                 else
 670                         cpu_set(j, set_mask);
 671
 672                 set_cpus_allowed(current, set_mask);
 673                 if (unlikely(!cpu_isset(smp_processor_id(), set_mask))) {
 674                         dprintk("couldn't limit to CPUs in this domain\n");
 675                         retval = -EAGAIN;
 676                         if (first_cpu) {
 677                                 /* We haven't started the transition yet. */
 678                                 goto migrate_end;
 679                         }
 680                         break;
 681                 }
 682
 683                 msr = centrino_model[cpu]->op_points[newstate].index;
 684
 685                 if (first_cpu) {
 686                         rdmsr(MSR_IA32_PERF_CTL, oldmsr, h);
 687                         if (msr == (oldmsr & 0xffff)) {
 688                                 dprintk("no change needed - msr was and needs "
 689                                         "to be %x\n", oldmsr);
 690                                 retval = 0;
 691                                 goto migrate_end;
 692                         }
 693
 694                         freqs.old = extract_clock(oldmsr, cpu, 0);
 695                         freqs.new = extract_clock(msr, cpu, 0);
 696
 697                         dprintk("target=%dkHz old=%d new=%d msr=%04x\n",
 698                                 target_freq, freqs.old, freqs.new, msr);
 699
 700                         for_each_cpu_mask(k, online_policy_cpus) {
 701                                 freqs.cpu = k;
 702                                 cpufreq_notify_transition(&freqs,
 703                                         CPUFREQ_PRECHANGE);
 704                         }
 705
 706                         first_cpu = 0;
 707                         /* all but 16 LSB are reserved, treat them with care */
 708                         oldmsr &= ~0xffff;
 709                         msr &= 0xffff;
 710                         oldmsr |= msr;
 711                 }
 712
 713                 wrmsr(MSR_IA32_PERF_CTL, oldmsr, h);
 714                 if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
 715                         break;
 716
 717                 cpu_set(j, covered_cpus);
 718         }
 719
 720         for_each_cpu_mask(k, online_policy_cpus) {
 721                 freqs.cpu = k;
 722                 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 723         }
 724
 725         if (unlikely(retval)) {
 726                 /*
 727                  * We have failed halfway through the frequency change.
 728                  * We have sent callbacks to policy->cpus and
 729                  * MSRs have already been written on coverd_cpus.
 730                  * Best effort undo..
 731                  */
 732
 733                 if (!cpus_empty(covered_cpus)) {
 734                         for_each_cpu_mask(j, covered_cpus) {
 735                                 set_cpus_allowed(current, cpumask_of_cpu(j));
 736                                 wrmsr(MSR_IA32_PERF_CTL, oldmsr, h);
 737                         }
 738                 }
 739
 740                 tmp = freqs.new;
 741                 freqs.new = freqs.old;
 742                 freqs.old = tmp;
 743                 for_each_cpu_mask(j, online_policy_cpus) {
 744                         freqs.cpu = j;
 745                         cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
 746                         cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 747                 }
 748         }
 749
 750 migrate_end:
 751         set_cpus_allowed(current, saved_mask);
 752         return 0;
 753 }
 754
 755 static struct freq_attr* centrino_attr[] = {
 756         &cpufreq_freq_attr_scaling_available_freqs,
 757         NULL,
 758 };
 759
 760 static struct cpufreq_driver centrino_driver = {
 761         .name           = "centrino", /* should be speedstep-centrino,
 762                                          but there's a 16 char limit */
 763         .init           = centrino_cpu_init,
 764         .exit           = centrino_cpu_exit,
 765         .verify         = centrino_verify,
 766         .target         = centrino_target,
 767         .get            = get_cur_freq,
 768         .attr           = centrino_attr,
 769         .owner          = THIS_MODULE,
 770 };
 771
 772
 773 /**
 774  * centrino_init - initializes the Enhanced SpeedStep CPUFreq driver
 775  *
 776  * Initializes the Enhanced SpeedStep support. Returns -ENODEV on
 777  * unsupported devices, -ENOENT if there's no voltage table for this
 778  * particular CPU model, -EINVAL on problems during initiatization,
 779  * and zero on success.
 780  *
 781  * This is quite picky.  Not only does the CPU have to advertise the
 782  * "est" flag in the cpuid capability flags, we look for a specific
 783  * CPU model and stepping, and we need to have the exact model name in
 784  * our voltage tables.  That is, be paranoid about not releasing
 785  * someone's valuable magic smoke.
 786  */
 787 static int __init centrino_init(void)
 788 {
 789         struct cpuinfo_x86 *cpu = cpu_data;
 790
 791         if (!cpu_has(cpu, X86_FEATURE_EST))
 792                 return -ENODEV;
 793
 794         centrino_cpu_early_init_acpi();
 795
 796         return cpufreq_register_driver(&centrino_driver);
 797 }
 798
 799 static void __exit centrino_exit(void)
 800 {
 801 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
 802         unsigned int j;
 803 #endif
 804
 805         cpufreq_unregister_driver(&centrino_driver);
 806
 807 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
 808         for_each_possible_cpu(j) {
 809                 kfree(acpi_perf_data[j]);
 810                 acpi_perf_data[j] = NULL;
 811         }
 812 #endif
 813 }
 814
 815 MODULE_AUTHOR ("Jeremy Fitzhardinge <jeremy@goop.org>");
 816 MODULE_DESCRIPTION ("Enhanced SpeedStep driver for Intel Pentium M processors.");
 817 MODULE_LICENSE ("GPL");
 818
 819 late_initcall(centrino_init);
 820 module_exit(centrino_exit);