arch/i386/kernel/cpu/cpufreq/longhaul.c

   1 /*
   2  *  (C) 2001-2004  Dave Jones. <davej@codemonkey.org.uk>
   3  *  (C) 2002  Padraig Brady. <padraig@antefacto.com>
   4  *
   5  *  Licensed under the terms of the GNU GPL License version 2.
   6  *  Based upon datasheets & sample CPUs kindly provided by VIA.
   7  *
   8  *  VIA have currently 3 different versions of Longhaul.
   9  *  Version 1 (Longhaul) uses the BCR2 MSR at 0x1147.
  10  *   It is present only in Samuel 1 (C5A), Samuel 2 (C5B) stepping 0.
  11  *  Version 2 of longhaul is backward compatible with v1, but adds
  12  *   LONGHAUL MSR for purpose of both frequency and voltage scaling.
  13  *   Present in Samuel 2 (steppings 1-7 only) (C5B), and Ezra (C5C).
  14  *  Version 3 of longhaul got renamed to Powersaver and redesigned
  15  *   to use only the POWERSAVER MSR at 0x110a.
  16  *   It is present in Ezra-T (C5M), Nehemiah (C5X) and above.
  17  *   It's pretty much the same feature wise to longhaul v2, though
  18  *   there is provision for scaling FSB too, but this doesn't work
  19  *   too well in practice so we don't even try to use this.
  20  *
  21  *  BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/module.h>
  26 #include <linux/moduleparam.h>
  27 #include <linux/init.h>
  28 #include <linux/cpufreq.h>
  29 #include <linux/pci.h>
  30 #include <linux/slab.h>
  31 #include <linux/string.h>
  32 #include <linux/delay.h>
  33
  34 #include <asm/msr.h>
  35 #include <asm/timex.h>
  36 #include <asm/io.h>
  37 #include <asm/acpi.h>
  38 #include <linux/acpi.h>
  39 #include <acpi/processor.h>
  40
  41 #include "longhaul.h"
  42
  43 #define PFX "longhaul: "
  44
  45 #define TYPE_LONGHAUL_V1        1
  46 #define TYPE_LONGHAUL_V2        2
  47 #define TYPE_POWERSAVER         3
  48
  49 #define CPU_SAMUEL      1
  50 #define CPU_SAMUEL2     2
  51 #define CPU_EZRA        3
  52 #define CPU_EZRA_T      4
  53 #define CPU_NEHEMIAH    5
  54 #define CPU_NEHEMIAH_C  6
  55
  56 /* Flags */
  57 #define USE_ACPI_C3             (1 << 1)
  58 #define USE_NORTHBRIDGE         (1 << 2)
  59
  60 static int cpu_model;
  61 static unsigned int numscales=16;
  62 static unsigned int fsb;
  63
  64 static const struct mV_pos *vrm_mV_table;
  65 static const unsigned char *mV_vrm_table;
  66
  67 static unsigned int highest_speed, lowest_speed; /* kHz */
  68 static unsigned int minmult, maxmult;
  69 static int can_scale_voltage;
  70 static struct acpi_processor *pr = NULL;
  71 static struct acpi_processor_cx *cx = NULL;
  72 static u32 acpi_regs_addr;
  73 static u8 longhaul_flags;
  74 static unsigned int longhaul_index;
  75
  76 /* Module parameters */
  77 static int scale_voltage;
  78 static int disable_acpi_c3;
  79
  80 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "longhaul", msg)
  81
  82
  83 /* Clock ratios multiplied by 10 */
  84 static int clock_ratio[32];
  85 static int eblcr_table[32];
  86 static int longhaul_version;
  87 static struct cpufreq_frequency_table *longhaul_table;
  88
  89 #ifdef CONFIG_CPU_FREQ_DEBUG
  90 static char speedbuffer[8];
  91
  92 static char *print_speed(int speed)
  93 {
  94         if (speed < 1000) {
  95                 snprintf(speedbuffer, sizeof(speedbuffer),"%dMHz", speed);
  96                 return speedbuffer;
  97         }
  98
  99         if (speed%1000 == 0)
 100                 snprintf(speedbuffer, sizeof(speedbuffer),
 101                         "%dGHz", speed/1000);
 102         else
 103                 snprintf(speedbuffer, sizeof(speedbuffer),
 104                         "%d.%dGHz", speed/1000, (speed%1000)/100);
 105
 106         return speedbuffer;
 107 }
 108 #endif
 109
 110
 111 static unsigned int calc_speed(int mult)
 112 {
 113         int khz;
 114         khz = (mult/10)*fsb;
 115         if (mult%10)
 116                 khz += fsb/2;
 117         khz *= 1000;
 118         return khz;
 119 }
 120
 121
 122 static int longhaul_get_cpu_mult(void)
 123 {
 124         unsigned long invalue=0,lo, hi;
 125
 126         rdmsr (MSR_IA32_EBL_CR_POWERON, lo, hi);
 127         invalue = (lo & (1<<22|1<<23|1<<24|1<<25)) >>22;
 128         if (longhaul_version==TYPE_LONGHAUL_V2 || longhaul_version==TYPE_POWERSAVER) {
 129                 if (lo & (1<<27))
 130                         invalue+=16;
 131         }
 132         return eblcr_table[invalue];
 133 }
 134
 135 /* For processor with BCR2 MSR */
 136
 137 static void do_longhaul1(unsigned int clock_ratio_index)
 138 {
 139         union msr_bcr2 bcr2;
 140
 141         rdmsrl(MSR_VIA_BCR2, bcr2.val);
 142         /* Enable software clock multiplier */
 143         bcr2.bits.ESOFTBF = 1;
 144         bcr2.bits.CLOCKMUL = clock_ratio_index & 0xff;
 145
 146         /* Sync to timer tick */
 147         safe_halt();
 148         /* Change frequency on next halt or sleep */
 149         wrmsrl(MSR_VIA_BCR2, bcr2.val);
 150         /* Invoke transition */
 151         ACPI_FLUSH_CPU_CACHE();
 152         halt();
 153
 154         /* Disable software clock multiplier */
 155         local_irq_disable();
 156         rdmsrl(MSR_VIA_BCR2, bcr2.val);
 157         bcr2.bits.ESOFTBF = 0;
 158         wrmsrl(MSR_VIA_BCR2, bcr2.val);
 159 }
 160
 161 /* For processor with Longhaul MSR */
 162
 163 static void do_powersaver(int cx_address, unsigned int clock_ratio_index,
 164                           unsigned int dir)
 165 {
 166         union msr_longhaul longhaul;
 167         u32 t;
 168
 169         rdmsrl(MSR_VIA_LONGHAUL, longhaul.val);
 170         /* Setup new frequency */
 171         longhaul.bits.RevisionKey = longhaul.bits.RevisionID;
 172         longhaul.bits.SoftBusRatio = clock_ratio_index & 0xf;
 173         longhaul.bits.SoftBusRatio4 = (clock_ratio_index & 0x10) >> 4;
 174         /* Setup new voltage */
 175         if (can_scale_voltage)
 176                 longhaul.bits.SoftVID = (clock_ratio_index >> 8) & 0x1f;
 177         /* Sync to timer tick */
 178         safe_halt();
 179         /* Raise voltage if necessary */
 180         if (can_scale_voltage && dir) {
 181                 longhaul.bits.EnableSoftVID = 1;
 182                 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
 183                 /* Change voltage */
 184                 if (!cx_address) {
 185                         ACPI_FLUSH_CPU_CACHE();
 186                         halt();
 187                 } else {
 188                         ACPI_FLUSH_CPU_CACHE();
 189                         /* Invoke C3 */
 190                         inb(cx_address);
 191                         /* Dummy op - must do something useless after P_LVL3
 192                          * read */
 193                         t = inl(acpi_gbl_FADT.xpm_timer_block.address);
 194                 }
 195                 longhaul.bits.EnableSoftVID = 0;
 196                 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
 197         }
 198
 199         /* Change frequency on next halt or sleep */
 200         longhaul.bits.EnableSoftBusRatio = 1;
 201         wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
 202         if (!cx_address) {
 203                 ACPI_FLUSH_CPU_CACHE();
 204                 halt();
 205         } else {
 206                 ACPI_FLUSH_CPU_CACHE();
 207                 /* Invoke C3 */
 208                 inb(cx_address);
 209                 /* Dummy op - must do something useless after P_LVL3 read */
 210                 t = inl(acpi_gbl_FADT.xpm_timer_block.address);
 211         }
 212         /* Disable bus ratio bit */
 213         longhaul.bits.EnableSoftBusRatio = 0;
 214         wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
 215
 216         /* Reduce voltage if necessary */
 217         if (can_scale_voltage && !dir) {
 218                 longhaul.bits.EnableSoftVID = 1;
 219                 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
 220                 /* Change voltage */
 221                 if (!cx_address) {
 222                         ACPI_FLUSH_CPU_CACHE();
 223                         halt();
 224                 } else {
 225                         ACPI_FLUSH_CPU_CACHE();
 226                         /* Invoke C3 */
 227                         inb(cx_address);
 228                         /* Dummy op - must do something useless after P_LVL3
 229                          * read */
 230                         t = inl(acpi_gbl_FADT.xpm_timer_block.address);
 231                 }
 232                 longhaul.bits.EnableSoftVID = 0;
 233                 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
 234         }
 235 }
 236
 237 /**
 238  * longhaul_set_cpu_frequency()
 239  * @clock_ratio_index : bitpattern of the new multiplier.
 240  *
 241  * Sets a new clock ratio.
 242  */
 243
 244 static void longhaul_setstate(unsigned int table_index)
 245 {
 246         unsigned int clock_ratio_index;
 247         int speed, mult;
 248         struct cpufreq_freqs freqs;
 249         unsigned long flags;
 250         unsigned int pic1_mask, pic2_mask;
 251         u16 bm_status = 0;
 252         u32 bm_timeout = 1000;
 253         unsigned int dir = 0;
 254
 255         clock_ratio_index = longhaul_table[table_index].index;
 256         /* Safety precautions */
 257         mult = clock_ratio[clock_ratio_index & 0x1f];
 258         if (mult == -1)
 259                 return;
 260         speed = calc_speed(mult);
 261         if ((speed > highest_speed) || (speed < lowest_speed))
 262                 return;
 263         /* Voltage transition before frequency transition? */
 264         if (can_scale_voltage && longhaul_index < table_index)
 265                 dir = 1;
 266
 267         freqs.old = calc_speed(longhaul_get_cpu_mult());
 268         freqs.new = speed;
 269         freqs.cpu = 0; /* longhaul.c is UP only driver */
 270
 271         cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
 272
 273         dprintk ("Setting to FSB:%dMHz Mult:%d.%dx (%s)\n",
 274                         fsb, mult/10, mult%10, print_speed(speed/1000));
 275
 276         preempt_disable();
 277         local_irq_save(flags);
 278
 279         pic2_mask = inb(0xA1);
 280         pic1_mask = inb(0x21);  /* works on C3. save mask. */
 281         outb(0xFF,0xA1);        /* Overkill */
 282         outb(0xFE,0x21);        /* TMR0 only */
 283
 284         /* Wait while PCI bus is busy. */
 285         if (acpi_regs_addr && (longhaul_flags & USE_NORTHBRIDGE
 286             || ((pr != NULL) && pr->flags.bm_control))) {
 287                 bm_status = inw(acpi_regs_addr);
 288                 bm_status &= 1 << 4;
 289                 while (bm_status && bm_timeout) {
 290                         outw(1 << 4, acpi_regs_addr);
 291                         bm_timeout--;
 292                         bm_status = inw(acpi_regs_addr);
 293                         bm_status &= 1 << 4;
 294                 }
 295         }
 296
 297         if (longhaul_flags & USE_NORTHBRIDGE) {
 298                 /* Disable AGP and PCI arbiters */
 299                 outb(3, 0x22);
 300         } else if ((pr != NULL) && pr->flags.bm_control) {
 301                 /* Disable bus master arbitration */
 302                 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 1);
 303         }
 304         switch (longhaul_version) {
 305
 306         /*
 307          * Longhaul v1. (Samuel[C5A] and Samuel2 stepping 0[C5B])
 308          * Software controlled multipliers only.
 309          */
 310         case TYPE_LONGHAUL_V1:
 311                 do_longhaul1(clock_ratio_index);
 312                 break;
 313
 314         /*
 315          * Longhaul v2 appears in Samuel2 Steppings 1->7 [C5B] and Ezra [C5C]
 316          *
 317          * Longhaul v3 (aka Powersaver). (Ezra-T [C5M] & Nehemiah [C5N])
 318          * Nehemiah can do FSB scaling too, but this has never been proven
 319          * to work in practice.
 320          */
 321         case TYPE_LONGHAUL_V2:
 322         case TYPE_POWERSAVER:
 323                 if (longhaul_flags & USE_ACPI_C3) {
 324                         /* Don't allow wakeup */
 325                         acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0);
 326                         do_powersaver(cx->address, clock_ratio_index, dir);
 327                 } else {
 328                         do_powersaver(0, clock_ratio_index, dir);
 329                 }
 330                 break;
 331         }
 332
 333         if (longhaul_flags & USE_NORTHBRIDGE) {
 334                 /* Enable arbiters */
 335                 outb(0, 0x22);
 336         } else if ((pr != NULL) && pr->flags.bm_control) {
 337                 /* Enable bus master arbitration */
 338                 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0);
 339         }
 340         outb(pic2_mask,0xA1);   /* restore mask */
 341         outb(pic1_mask,0x21);
 342
 343         local_irq_restore(flags);
 344         preempt_enable();
 345
 346         freqs.new = calc_speed(longhaul_get_cpu_mult());
 347         cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 348
 349         if (!bm_timeout)
 350                 printk(KERN_INFO PFX "Warning: Timeout while waiting for idle PCI bus.\n");
 351 }
 352
 353 /*
 354  * Centaur decided to make life a little more tricky.
 355  * Only longhaul v1 is allowed to read EBLCR BSEL[0:1].
 356  * Samuel2 and above have to try and guess what the FSB is.
 357  * We do this by assuming we booted at maximum multiplier, and interpolate
 358  * between that value multiplied by possible FSBs and cpu_mhz which
 359  * was calculated at boot time. Really ugly, but no other way to do this.
 360  */
 361
 362 #define ROUNDING        0xf
 363
 364 static int guess_fsb(int mult)
 365 {
 366         int speed = cpu_khz / 1000;
 367         int i;
 368         int speeds[] = { 666, 1000, 1333, 2000 };
 369         int f_max, f_min;
 370
 371         for (i = 0; i < 4; i++) {
 372                 f_max = ((speeds[i] * mult) + 50) / 100;
 373                 f_max += (ROUNDING / 2);
 374                 f_min = f_max - ROUNDING;
 375                 if ((speed <= f_max) && (speed >= f_min))
 376                         return speeds[i] / 10;
 377         }
 378         return 0;
 379 }
 380
 381
 382 static int __init longhaul_get_ranges(void)
 383 {
 384         unsigned int i, j, k = 0;
 385         unsigned int ratio;
 386         int mult;
 387
 388         /* Get current frequency */
 389         mult = longhaul_get_cpu_mult();
 390         if (mult == -1) {
 391                 printk(KERN_INFO PFX "Invalid (reserved) multiplier!\n");
 392                 return -EINVAL;
 393         }
 394         fsb = guess_fsb(mult);
 395         if (fsb == 0) {
 396                 printk(KERN_INFO PFX "Invalid (reserved) FSB!\n");
 397                 return -EINVAL;
 398         }
 399         /* Get max multiplier - as we always did.
 400          * Longhaul MSR is usefull only when voltage scaling is enabled.
 401          * C3 is booting at max anyway. */
 402         maxmult = mult;
 403         /* Get min multiplier */
 404         switch (cpu_model) {
 405         case CPU_NEHEMIAH:
 406                 minmult = 50;
 407                 break;
 408         case CPU_NEHEMIAH_C:
 409                 minmult = 40;
 410                 break;
 411         default:
 412                 minmult = 30;
 413                 break;
 414         }
 415
 416         dprintk ("MinMult:%d.%dx MaxMult:%d.%dx\n",
 417                  minmult/10, minmult%10, maxmult/10, maxmult%10);
 418
 419         highest_speed = calc_speed(maxmult);
 420         lowest_speed = calc_speed(minmult);
 421         dprintk ("FSB:%dMHz  Lowest speed: %s   Highest speed:%s\n", fsb,
 422                  print_speed(lowest_speed/1000),
 423                  print_speed(highest_speed/1000));
 424
 425         if (lowest_speed == highest_speed) {
 426                 printk (KERN_INFO PFX "highestspeed == lowest, aborting.\n");
 427                 return -EINVAL;
 428         }
 429         if (lowest_speed > highest_speed) {
 430                 printk (KERN_INFO PFX "nonsense! lowest (%d > %d) !\n",
 431                         lowest_speed, highest_speed);
 432                 return -EINVAL;
 433         }
 434
 435         longhaul_table = kmalloc((numscales + 1) * sizeof(struct cpufreq_frequency_table), GFP_KERNEL);
 436         if(!longhaul_table)
 437                 return -ENOMEM;
 438
 439         for (j = 0; j < numscales; j++) {
 440                 ratio = clock_ratio[j];
 441                 if (ratio == -1)
 442                         continue;
 443                 if (ratio > maxmult || ratio < minmult)
 444                         continue;
 445                 longhaul_table[k].frequency = calc_speed(ratio);
 446                 longhaul_table[k].index = j;
 447                 k++;
 448         }
 449         if (k <= 1) {
 450                 kfree(longhaul_table);
 451                 return -ENODEV;
 452         }
 453         /* Sort */
 454         for (j = 0; j < k - 1; j++) {
 455                 unsigned int min_f, min_i;
 456                 min_f = longhaul_table[j].frequency;
 457                 min_i = j;
 458                 for (i = j + 1; i < k; i++) {
 459                         if (longhaul_table[i].frequency < min_f) {
 460                                 min_f = longhaul_table[i].frequency;
 461                                 min_i = i;
 462                         }
 463                 }
 464                 if (min_i != j) {
 465                         unsigned int temp;
 466                         temp = longhaul_table[j].frequency;
 467                         longhaul_table[j].frequency = longhaul_table[min_i].frequency;
 468                         longhaul_table[min_i].frequency = temp;
 469                         temp = longhaul_table[j].index;
 470                         longhaul_table[j].index = longhaul_table[min_i].index;
 471                         longhaul_table[min_i].index = temp;
 472                 }
 473         }
 474
 475         longhaul_table[k].frequency = CPUFREQ_TABLE_END;
 476
 477         /* Find index we are running on */
 478         for (j = 0; j < k; j++) {
 479                 if (clock_ratio[longhaul_table[j].index & 0x1f] == mult) {
 480                         longhaul_index = j;
 481                         break;
 482                 }
 483         }
 484         return 0;
 485 }
 486
 487
 488 static void __init longhaul_setup_voltagescaling(void)
 489 {
 490         union msr_longhaul longhaul;
 491         struct mV_pos minvid, maxvid, vid;
 492         unsigned int j, speed, pos, kHz_step, numvscales;
 493         int min_vid_speed;
 494
 495         rdmsrl(MSR_VIA_LONGHAUL, longhaul.val);
 496         if (!(longhaul.bits.RevisionID & 1)) {
 497                 printk(KERN_INFO PFX "Voltage scaling not supported by CPU.\n");
 498                 return;
 499         }
 500
 501         if (!longhaul.bits.VRMRev) {
 502                 printk(KERN_INFO PFX "VRM 8.5\n");
 503                 vrm_mV_table = &vrm85_mV[0];
 504                 mV_vrm_table = &mV_vrm85[0];
 505         } else {
 506                 printk(KERN_INFO PFX "Mobile VRM\n");
 507                 if (cpu_model < CPU_NEHEMIAH)
 508                         return;
 509                 vrm_mV_table = &mobilevrm_mV[0];
 510                 mV_vrm_table = &mV_mobilevrm[0];
 511         }
 512
 513         minvid = vrm_mV_table[longhaul.bits.MinimumVID];
 514         maxvid = vrm_mV_table[longhaul.bits.MaximumVID];
 515
 516         if (minvid.mV == 0 || maxvid.mV == 0 || minvid.mV > maxvid.mV) {
 517                 printk (KERN_INFO PFX "Bogus values Min:%d.%03d Max:%d.%03d. "
 518                                         "Voltage scaling disabled.\n",
 519                                         minvid.mV/1000, minvid.mV%1000, maxvid.mV/1000, maxvid.mV%1000);
 520                 return;
 521         }
 522
 523         if (minvid.mV == maxvid.mV) {
 524                 printk (KERN_INFO PFX "Claims to support voltage scaling but min & max are "
 525                                 "both %d.%03d. Voltage scaling disabled\n",
 526                                 maxvid.mV/1000, maxvid.mV%1000);
 527                 return;
 528         }
 529
 530         /* How many voltage steps */
 531         numvscales = maxvid.pos - minvid.pos + 1;
 532         printk(KERN_INFO PFX
 533                 "Max VID=%d.%03d  "
 534                 "Min VID=%d.%03d, "
 535                 "%d possible voltage scales\n",
 536                 maxvid.mV/1000, maxvid.mV%1000,
 537                 minvid.mV/1000, minvid.mV%1000,
 538                 numvscales);
 539
 540         /* Calculate max frequency at min voltage */
 541         j = longhaul.bits.MinMHzBR;
 542         if (longhaul.bits.MinMHzBR4)
 543                 j += 16;
 544         min_vid_speed = eblcr_table[j];
 545         if (min_vid_speed == -1)
 546                 return;
 547         switch (longhaul.bits.MinMHzFSB) {
 548         case 0:
 549                 min_vid_speed *= 13333;
 550                 break;
 551         case 1:
 552                 min_vid_speed *= 10000;
 553                 break;
 554         case 3:
 555                 min_vid_speed *= 6666;
 556                 break;
 557         default:
 558                 return;
 559                 break;
 560         }
 561         if (min_vid_speed >= highest_speed)
 562                 return;
 563         /* Calculate kHz for one voltage step */
 564         kHz_step = (highest_speed - min_vid_speed) / numvscales;
 565
 566         j = 0;
 567         while (longhaul_table[j].frequency != CPUFREQ_TABLE_END) {
 568                 speed = longhaul_table[j].frequency;
 569                 if (speed > min_vid_speed)
 570                         pos = (speed - min_vid_speed) / kHz_step + minvid.pos;
 571                 else
 572                         pos = minvid.pos;
 573                 longhaul_table[j].index |= mV_vrm_table[pos] << 8;
 574                 vid = vrm_mV_table[mV_vrm_table[pos]];
 575                 printk(KERN_INFO PFX "f: %d kHz, index: %d, vid: %d mV\n", speed, j, vid.mV);
 576                 j++;
 577         }
 578
 579         can_scale_voltage = 1;
 580         printk(KERN_INFO PFX "Voltage scaling enabled.\n");
 581 }
 582
 583
 584 static int longhaul_verify(struct cpufreq_policy *policy)
 585 {
 586         return cpufreq_frequency_table_verify(policy, longhaul_table);
 587 }
 588
 589
 590 static int longhaul_target(struct cpufreq_policy *policy,
 591                             unsigned int target_freq, unsigned int relation)
 592 {
 593         unsigned int table_index = 0;
 594         unsigned int i;
 595         unsigned int dir = 0;
 596         u8 vid, current_vid;
 597
 598         if (cpufreq_frequency_table_target(policy, longhaul_table, target_freq, relation, &table_index))
 599                 return -EINVAL;
 600
 601         /* Don't set same frequency again */
 602         if (longhaul_index == table_index)
 603                 return 0;
 604
 605         if (!can_scale_voltage)
 606                 longhaul_setstate(table_index);
 607         else {
 608                 /* On test system voltage transitions exceeding single
 609                  * step up or down were turning motherboard off. Both
 610                  * "ondemand" and "userspace" are unsafe. C7 is doing
 611                  * this in hardware, C3 is old and we need to do this
 612                  * in software. */
 613                 i = longhaul_index;
 614                 current_vid = (longhaul_table[longhaul_index].index >> 8) & 0x1f;
 615                 if (table_index > longhaul_index)
 616                         dir = 1;
 617                 while (i != table_index) {
 618                         vid = (longhaul_table[i].index >> 8) & 0x1f;
 619                         if (vid != current_vid) {
 620                                 longhaul_setstate(i);
 621                                 current_vid = vid;
 622                                 msleep(200);
 623                         }
 624                         if (dir)
 625                                 i++;
 626                         else
 627                                 i--;
 628                 }
 629                 longhaul_setstate(table_index);
 630         }
 631         longhaul_index = table_index;
 632         return 0;
 633 }
 634
 635
 636 static unsigned int longhaul_get(unsigned int cpu)
 637 {
 638         if (cpu)
 639                 return 0;
 640         return calc_speed(longhaul_get_cpu_mult());
 641 }
 642
 643 static acpi_status longhaul_walk_callback(acpi_handle obj_handle,
 644                                           u32 nesting_level,
 645                                           void *context, void **return_value)
 646 {
 647         struct acpi_device *d;
 648
 649         if ( acpi_bus_get_device(obj_handle, &d) ) {
 650                 return 0;
 651         }
 652         *return_value = (void *)acpi_driver_data(d);
 653         return 1;
 654 }
 655
 656 /* VIA don't support PM2 reg, but have something similar */
 657 static int enable_arbiter_disable(void)
 658 {
 659         struct pci_dev *dev;
 660         int status = 1;
 661         int reg;
 662         u8 pci_cmd;
 663
 664         /* Find PLE133 host bridge */
 665         reg = 0x78;
 666         dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8601_0,
 667                              NULL);
 668         /* Find CLE266 host bridge */
 669         if (dev == NULL) {
 670                 reg = 0x76;
 671                 dev = pci_get_device(PCI_VENDOR_ID_VIA,
 672                                      PCI_DEVICE_ID_VIA_862X_0, NULL);
 673                 /* Find CN400 V-Link host bridge */
 674                 if (dev == NULL)
 675                         dev = pci_get_device(PCI_VENDOR_ID_VIA, 0x7259, NULL);
 676         }
 677         if (dev != NULL) {
 678                 /* Enable access to port 0x22 */
 679                 pci_read_config_byte(dev, reg, &pci_cmd);
 680                 if (!(pci_cmd & 1<<7)) {
 681                         pci_cmd |= 1<<7;
 682                         pci_write_config_byte(dev, reg, pci_cmd);
 683                         pci_read_config_byte(dev, reg, &pci_cmd);
 684                         if (!(pci_cmd & 1<<7)) {
 685                                 printk(KERN_ERR PFX
 686                                         "Can't enable access to port 0x22.\n");
 687                                 status = 0;
 688                         }
 689                 }
 690                 pci_dev_put(dev);
 691                 return status;
 692         }
 693         return 0;
 694 }
 695
 696 static int longhaul_setup_southbridge(void)
 697 {
 698         struct pci_dev *dev;
 699         u8 pci_cmd;
 700
 701         /* Find VT8235 southbridge */
 702         dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, NULL);
 703         if (dev == NULL)
 704         /* Find VT8237 southbridge */
 705                 dev = pci_get_device(PCI_VENDOR_ID_VIA,
 706                                      PCI_DEVICE_ID_VIA_8237, NULL);
 707         if (dev != NULL) {
 708                 /* Set transition time to max */
 709                 pci_read_config_byte(dev, 0xec, &pci_cmd);
 710                 pci_cmd &= ~(1 << 2);
 711                 pci_write_config_byte(dev, 0xec, pci_cmd);
 712                 pci_read_config_byte(dev, 0xe4, &pci_cmd);
 713                 pci_cmd &= ~(1 << 7);
 714                 pci_write_config_byte(dev, 0xe4, pci_cmd);
 715                 pci_read_config_byte(dev, 0xe5, &pci_cmd);
 716                 pci_cmd |= 1 << 7;
 717                 pci_write_config_byte(dev, 0xe5, pci_cmd);
 718                 /* Get address of ACPI registers block*/
 719                 pci_read_config_byte(dev, 0x81, &pci_cmd);
 720                 if (pci_cmd & 1 << 7) {
 721                         pci_read_config_dword(dev, 0x88, &acpi_regs_addr);
 722                         acpi_regs_addr &= 0xff00;
 723                         printk(KERN_INFO PFX "ACPI I/O at 0x%x\n", acpi_regs_addr);
 724                 }
 725
 726                 pci_dev_put(dev);
 727                 return 1;
 728         }
 729         return 0;
 730 }
 731
 732 static int __init longhaul_cpu_init(struct cpufreq_policy *policy)
 733 {
 734         struct cpuinfo_x86 *c = cpu_data;
 735         char *cpuname=NULL;
 736         int ret;
 737         u32 lo, hi;
 738
 739         /* Check what we have on this motherboard */
 740         switch (c->x86_model) {
 741         case 6:
 742                 cpu_model = CPU_SAMUEL;
 743                 cpuname = "C3 'Samuel' [C5A]";
 744                 longhaul_version = TYPE_LONGHAUL_V1;
 745                 memcpy (clock_ratio, samuel1_clock_ratio, sizeof(samuel1_clock_ratio));
 746                 memcpy (eblcr_table, samuel1_eblcr, sizeof(samuel1_eblcr));
 747                 break;
 748
 749         case 7:
 750                 switch (c->x86_mask) {
 751                 case 0:
 752                         longhaul_version = TYPE_LONGHAUL_V1;
 753                         cpu_model = CPU_SAMUEL2;
 754                         cpuname = "C3 'Samuel 2' [C5B]";
 755                         /* Note, this is not a typo, early Samuel2's had
 756                          * Samuel1 ratios. */
 757                         memcpy(clock_ratio, samuel1_clock_ratio,
 758                                 sizeof(samuel1_clock_ratio));
 759                         memcpy(eblcr_table, samuel2_eblcr,
 760                                 sizeof(samuel2_eblcr));
 761                         break;
 762                 case 1 ... 15:
 763                         longhaul_version = TYPE_LONGHAUL_V1;
 764                         if (c->x86_mask < 8) {
 765                                 cpu_model = CPU_SAMUEL2;
 766                                 cpuname = "C3 'Samuel 2' [C5B]";
 767                         } else {
 768                                 cpu_model = CPU_EZRA;
 769                                 cpuname = "C3 'Ezra' [C5C]";
 770                         }
 771                         memcpy(clock_ratio, ezra_clock_ratio,
 772                                 sizeof(ezra_clock_ratio));
 773                         memcpy(eblcr_table, ezra_eblcr,
 774                                 sizeof(ezra_eblcr));
 775                         break;
 776                 }
 777                 break;
 778
 779         case 8:
 780                 cpu_model = CPU_EZRA_T;
 781                 cpuname = "C3 'Ezra-T' [C5M]";
 782                 longhaul_version = TYPE_POWERSAVER;
 783                 numscales=32;
 784                 memcpy (clock_ratio, ezrat_clock_ratio, sizeof(ezrat_clock_ratio));
 785                 memcpy (eblcr_table, ezrat_eblcr, sizeof(ezrat_eblcr));
 786                 break;
 787
 788         case 9:
 789                 longhaul_version = TYPE_POWERSAVER;
 790                 numscales = 32;
 791                 memcpy(clock_ratio,
 792                        nehemiah_clock_ratio,
 793                        sizeof(nehemiah_clock_ratio));
 794                 memcpy(eblcr_table, nehemiah_eblcr, sizeof(nehemiah_eblcr));
 795                 switch (c->x86_mask) {
 796                 case 0 ... 1:
 797                         cpu_model = CPU_NEHEMIAH;
 798                         cpuname = "C3 'Nehemiah A' [C5XLOE]";
 799                         break;
 800                 case 2 ... 4:
 801                         cpu_model = CPU_NEHEMIAH;
 802                         cpuname = "C3 'Nehemiah B' [C5XLOH]";
 803                         break;
 804                 case 5 ... 15:
 805                         cpu_model = CPU_NEHEMIAH_C;
 806                         cpuname = "C3 'Nehemiah C' [C5P]";
 807                         break;
 808                 }
 809                 break;
 810
 811         default:
 812                 cpuname = "Unknown";
 813                 break;
 814         }
 815         /* Check Longhaul ver. 2 */
 816         if (longhaul_version == TYPE_LONGHAUL_V2) {
 817                 rdmsr(MSR_VIA_LONGHAUL, lo, hi);
 818                 if (lo == 0 && hi == 0)
 819                         /* Looks like MSR isn't present */
 820                         longhaul_version = TYPE_LONGHAUL_V1;
 821         }
 822
 823         printk (KERN_INFO PFX "VIA %s CPU detected.  ", cpuname);
 824         switch (longhaul_version) {
 825         case TYPE_LONGHAUL_V1:
 826         case TYPE_LONGHAUL_V2:
 827                 printk ("Longhaul v%d supported.\n", longhaul_version);
 828                 break;
 829         case TYPE_POWERSAVER:
 830                 printk ("Powersaver supported.\n");
 831                 break;
 832         };
 833
 834         /* Doesn't hurt */
 835         longhaul_setup_southbridge();
 836
 837         /* Find ACPI data for processor */
 838         acpi_walk_namespace(ACPI_TYPE_PROCESSOR, ACPI_ROOT_OBJECT,
 839                                 ACPI_UINT32_MAX, &longhaul_walk_callback,
 840                                 NULL, (void *)&pr);
 841
 842         /* Check ACPI support for C3 state */
 843         if (pr != NULL && longhaul_version == TYPE_POWERSAVER) {
 844                 cx = &pr->power.states[ACPI_STATE_C3];
 845                 if (cx->address > 0 && cx->latency <= 1000)
 846                         longhaul_flags |= USE_ACPI_C3;
 847         }
 848         /* Disable if it isn't working */
 849         if (disable_acpi_c3)
 850                 longhaul_flags &= ~USE_ACPI_C3;
 851         /* Check if northbridge is friendly */
 852         if (enable_arbiter_disable())
 853                 longhaul_flags |= USE_NORTHBRIDGE;
 854
 855         /* Check ACPI support for bus master arbiter disable */
 856         if (!(longhaul_flags & USE_ACPI_C3
 857              || longhaul_flags & USE_NORTHBRIDGE)
 858             && ((pr == NULL) || !(pr->flags.bm_control))) {
 859                 printk(KERN_ERR PFX
 860                         "No ACPI support. Unsupported northbridge.\n");
 861                 return -ENODEV;
 862         }
 863
 864         if (longhaul_flags & USE_NORTHBRIDGE)
 865                 printk(KERN_INFO PFX "Using northbridge support.\n");
 866         if (longhaul_flags & USE_ACPI_C3)
 867                 printk(KERN_INFO PFX "Using ACPI support.\n");
 868
 869         ret = longhaul_get_ranges();
 870         if (ret != 0)
 871                 return ret;
 872
 873         if ((longhaul_version != TYPE_LONGHAUL_V1) && (scale_voltage != 0))
 874                 longhaul_setup_voltagescaling();
 875
 876         policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
 877         policy->cpuinfo.transition_latency = 200000;    /* nsec */
 878         policy->cur = calc_speed(longhaul_get_cpu_mult());
 879
 880         ret = cpufreq_frequency_table_cpuinfo(policy, longhaul_table);
 881         if (ret)
 882                 return ret;
 883
 884         cpufreq_frequency_table_get_attr(longhaul_table, policy->cpu);
 885
 886         return 0;
 887 }
 888
 889 static int __devexit longhaul_cpu_exit(struct cpufreq_policy *policy)
 890 {
 891         cpufreq_frequency_table_put_attr(policy->cpu);
 892         return 0;
 893 }
 894
 895 static struct freq_attr* longhaul_attr[] = {
 896         &cpufreq_freq_attr_scaling_available_freqs,
 897         NULL,
 898 };
 899
 900 static struct cpufreq_driver longhaul_driver = {
 901         .verify = longhaul_verify,
 902         .target = longhaul_target,
 903         .get    = longhaul_get,
 904         .init   = longhaul_cpu_init,
 905         .exit   = __devexit_p(longhaul_cpu_exit),
 906         .name   = "longhaul",
 907         .owner  = THIS_MODULE,
 908         .attr   = longhaul_attr,
 909 };
 910
 911
 912 static int __init longhaul_init(void)
 913 {
 914         struct cpuinfo_x86 *c = cpu_data;
 915
 916         if (c->x86_vendor != X86_VENDOR_CENTAUR || c->x86 != 6)
 917                 return -ENODEV;
 918
 919 #ifdef CONFIG_SMP
 920         if (num_online_cpus() > 1) {
 921                 printk(KERN_ERR PFX "More than 1 CPU detected, longhaul disabled.\n");
 922                 return -ENODEV;
 923         }
 924 #endif
 925 #ifdef CONFIG_X86_IO_APIC
 926         if (cpu_has_apic) {
 927                 printk(KERN_ERR PFX "APIC detected. Longhaul is currently broken in this configuration.\n");
 928                 return -ENODEV;
 929         }
 930 #endif
 931         switch (c->x86_model) {
 932         case 6 ... 9:
 933                 return cpufreq_register_driver(&longhaul_driver);
 934         case 10:
 935                 printk(KERN_ERR PFX "Use acpi-cpufreq driver for VIA C7\n");
 936         default:
 937                 ;;
 938         }
 939
 940         return -ENODEV;
 941 }
 942
 943
 944 static void __exit longhaul_exit(void)
 945 {
 946         int i;
 947
 948         for (i=0; i < numscales; i++) {
 949                 if (clock_ratio[i] == maxmult) {
 950                         longhaul_setstate(i);
 951                         break;
 952                 }
 953         }
 954
 955         cpufreq_unregister_driver(&longhaul_driver);
 956         kfree(longhaul_table);
 957 }
 958
 959 module_param (disable_acpi_c3, int, 0644);
 960 MODULE_PARM_DESC(disable_acpi_c3, "Don't use ACPI C3 support");
 961
 962 module_param (scale_voltage, int, 0644);
 963 MODULE_PARM_DESC(scale_voltage, "Scale voltage of processor");
 964
 965 MODULE_AUTHOR ("Dave Jones <davej@codemonkey.org.uk>");
 966 MODULE_DESCRIPTION ("Longhaul driver for VIA Cyrix processors.");
 967 MODULE_LICENSE ("GPL");
 968
 969 late_initcall(longhaul_init);
 970 module_exit(longhaul_exit);