arch/i386/kernel/cpu/amd.c

   1 #include <linux/init.h>
   2 #include <linux/bitops.h>
   3 #include <linux/mm.h>
   4 #include <asm/io.h>
   5 #include <asm/processor.h>
   6
   7 #include "cpu.h"
   8
   9 /*
  10  *      B step AMD K6 before B 9730xxxx have hardware bugs that can cause
  11  *      misexecution of code under Linux. Owners of such processors should
  12  *      contact AMD for precise details and a CPU swap.
  13  *
  14  *      See     http://www.multimania.com/poulot/k6bug.html
  15  *              http://www.amd.com/K6/k6docs/revgd.html
  16  *
  17  *      The following test is erm.. interesting. AMD neglected to up
  18  *      the chip setting when fixing the bug but they also tweaked some
  19  *      performance at the same time..
  20  */
  21
  22 extern void vide(void);
  23 __asm__(".align 4\nvide: ret");
  24
  25 #define ENABLE_C1E_MASK         0x18000000
  26 #define CPUID_PROCESSOR_SIGNATURE       1
  27 #define CPUID_XFAM              0x0ff00000
  28 #define CPUID_XFAM_K8           0x00000000
  29 #define CPUID_XFAM_10H          0x00100000
  30 #define CPUID_XFAM_11H          0x00200000
  31 #define CPUID_XMOD              0x000f0000
  32 #define CPUID_XMOD_REV_F        0x00040000
  33
  34 /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
  35 static __cpuinit int amd_apic_timer_broken(void)
  36 {
  37         u32 lo, hi;
  38         u32 eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
  39         switch (eax & CPUID_XFAM) {
  40         case CPUID_XFAM_K8:
  41                 if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
  42                         break;
  43         case CPUID_XFAM_10H:
  44         case CPUID_XFAM_11H:
  45                 rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
  46                 if (lo & ENABLE_C1E_MASK)
  47                         return 1;
  48                 break;
  49         default:
  50                 /* err on the side of caution */
  51                 return 1;
  52         }
  53         return 0;
  54 }
  55
  56 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
  57 {
  58         u32 l, h;
  59         int mbytes = num_physpages >> (20-PAGE_SHIFT);
  60         int r;
  61
  62 #ifdef CONFIG_SMP
  63         unsigned long long value;
  64
  65         /* Disable TLB flush filter by setting HWCR.FFDIS on K8
  66          * bit 6 of msr C001_0015
  67          *
  68          * Errata 63 for SH-B3 steppings
  69          * Errata 122 for all steppings (F+ have it disabled by default)
  70          */
  71         if (c->x86 == 15) {
  72                 rdmsrl(MSR_K7_HWCR, value);
  73                 value |= 1 << 6;
  74                 wrmsrl(MSR_K7_HWCR, value);
  75         }
  76 #endif
  77
  78         /*
  79          *      FIXME: We should handle the K5 here. Set up the write
  80          *      range and also turn on MSR 83 bits 4 and 31 (write alloc,
  81          *      no bus pipeline)
  82          */
  83
  84         /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
  85            3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
  86         clear_bit(0*32+31, c->x86_capability);
  87
  88         r = get_model_name(c);
  89
  90         switch(c->x86)
  91         {
  92                 case 4:
  93                 /*
  94                  * General Systems BIOSen alias the cpu frequency registers
  95                  * of the Elan at 0x000df000. Unfortuantly, one of the Linux
  96                  * drivers subsequently pokes it, and changes the CPU speed.
  97                  * Workaround : Remove the unneeded alias.
  98                  */
  99 #define CBAR            (0xfffc) /* Configuration Base Address  (32-bit) */
 100 #define CBAR_ENB        (0x80000000)
 101 #define CBAR_KEY        (0X000000CB)
 102                         if (c->x86_model==9 || c->x86_model == 10) {
 103                                 if (inl (CBAR) & CBAR_ENB)
 104                                         outl (0 | CBAR_KEY, CBAR);
 105                         }
 106                         break;
 107                 case 5:
 108                         if( c->x86_model < 6 )
 109                         {
 110                                 /* Based on AMD doc 20734R - June 2000 */
 111                                 if ( c->x86_model == 0 ) {
 112                                         clear_bit(X86_FEATURE_APIC, c->x86_capability);
 113                                         set_bit(X86_FEATURE_PGE, c->x86_capability);
 114                                 }
 115                                 break;
 116                         }
 117
 118                         if ( c->x86_model == 6 && c->x86_mask == 1 ) {
 119                                 const int K6_BUG_LOOP = 1000000;
 120                                 int n;
 121                                 void (*f_vide)(void);
 122                                 unsigned long d, d2;
 123
 124                                 printk(KERN_INFO "AMD K6 stepping B detected - ");
 125
 126                                 /*
 127                                  * It looks like AMD fixed the 2.6.2 bug and improved indirect
 128                                  * calls at the same time.
 129                                  */
 130
 131                                 n = K6_BUG_LOOP;
 132                                 f_vide = vide;
 133                                 rdtscl(d);
 134                                 while (n--)
 135                                         f_vide();
 136                                 rdtscl(d2);
 137                                 d = d2-d;
 138
 139                                 if (d > 20*K6_BUG_LOOP)
 140                                         printk("system stability may be impaired when more than 32 MB are used.\n");
 141                                 else
 142                                         printk("probably OK (after B9730xxxx).\n");
 143                                 printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
 144                         }
 145
 146                         /* K6 with old style WHCR */
 147                         if (c->x86_model < 8 ||
 148                            (c->x86_model== 8 && c->x86_mask < 8)) {
 149                                 /* We can only write allocate on the low 508Mb */
 150                                 if(mbytes>508)
 151                                         mbytes=508;
 152
 153                                 rdmsr(MSR_K6_WHCR, l, h);
 154                                 if ((l&0x0000FFFF)==0) {
 155                                         unsigned long flags;
 156                                         l=(1<<0)|((mbytes/4)<<1);
 157                                         local_irq_save(flags);
 158                                         wbinvd();
 159                                         wrmsr(MSR_K6_WHCR, l, h);
 160                                         local_irq_restore(flags);
 161                                         printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
 162                                                 mbytes);
 163                                 }
 164                                 break;
 165                         }
 166
 167                         if ((c->x86_model == 8 && c->x86_mask >7) ||
 168                              c->x86_model == 9 || c->x86_model == 13) {
 169                                 /* The more serious chips .. */
 170
 171                                 if(mbytes>4092)
 172                                         mbytes=4092;
 173
 174                                 rdmsr(MSR_K6_WHCR, l, h);
 175                                 if ((l&0xFFFF0000)==0) {
 176                                         unsigned long flags;
 177                                         l=((mbytes>>2)<<22)|(1<<16);
 178                                         local_irq_save(flags);
 179                                         wbinvd();
 180                                         wrmsr(MSR_K6_WHCR, l, h);
 181                                         local_irq_restore(flags);
 182                                         printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
 183                                                 mbytes);
 184                                 }
 185
 186                                 /*  Set MTRR capability flag if appropriate */
 187                                 if (c->x86_model == 13 || c->x86_model == 9 ||
 188                                    (c->x86_model == 8 && c->x86_mask >= 8))
 189                                         set_bit(X86_FEATURE_K6_MTRR, c->x86_capability);
 190                                 break;
 191                         }
 192
 193                         if (c->x86_model == 10) {
 194                                 /* AMD Geode LX is model 10 */
 195                                 /* placeholder for any needed mods */
 196                                 break;
 197                         }
 198                         break;
 199                 case 6: /* An Athlon/Duron */
 200
 201                         /* Bit 15 of Athlon specific MSR 15, needs to be 0
 202                          * to enable SSE on Palomino/Morgan/Barton CPU's.
 203                          * If the BIOS didn't enable it already, enable it here.
 204                          */
 205                         if (c->x86_model >= 6 && c->x86_model <= 10) {
 206                                 if (!cpu_has(c, X86_FEATURE_XMM)) {
 207                                         printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
 208                                         rdmsr(MSR_K7_HWCR, l, h);
 209                                         l &= ~0x00008000;
 210                                         wrmsr(MSR_K7_HWCR, l, h);
 211                                         set_bit(X86_FEATURE_XMM, c->x86_capability);
 212                                 }
 213                         }
 214
 215                         /* It's been determined by AMD that Athlons since model 8 stepping 1
 216                          * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
 217                          * As per AMD technical note 27212 0.2
 218                          */
 219                         if ((c->x86_model == 8 && c->x86_mask>=1) || (c->x86_model > 8)) {
 220                                 rdmsr(MSR_K7_CLK_CTL, l, h);
 221                                 if ((l & 0xfff00000) != 0x20000000) {
 222                                         printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l,
 223                                                 ((l & 0x000fffff)|0x20000000));
 224                                         wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
 225                                 }
 226                         }
 227                         break;
 228         }
 229
 230         switch (c->x86) {
 231         case 15:
 232                 set_bit(X86_FEATURE_K8, c->x86_capability);
 233                 break;
 234         case 6:
 235                 set_bit(X86_FEATURE_K7, c->x86_capability);
 236                 break;
 237         }
 238         if (c->x86 >= 6)
 239                 set_bit(X86_FEATURE_FXSAVE_LEAK, c->x86_capability);
 240
 241         display_cacheinfo(c);
 242
 243         if (cpuid_eax(0x80000000) >= 0x80000008) {
 244                 c->x86_max_cores = (cpuid_ecx(0x80000008) & 0xff) + 1;
 245         }
 246
 247         if (cpuid_eax(0x80000000) >= 0x80000007) {
 248                 c->x86_power = cpuid_edx(0x80000007);
 249                 if (c->x86_power & (1<<8))
 250                         set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
 251         }
 252
 253 #ifdef CONFIG_X86_HT
 254         /*
 255          * On a AMD multi core setup the lower bits of the APIC id
 256          * distingush the cores.
 257          */
 258         if (c->x86_max_cores > 1) {
 259                 int cpu = smp_processor_id();
 260                 unsigned bits = (cpuid_ecx(0x80000008) >> 12) & 0xf;
 261
 262                 if (bits == 0) {
 263                         while ((1 << bits) < c->x86_max_cores)
 264                                 bits++;
 265                 }
 266                 c->cpu_core_id = c->phys_proc_id & ((1<<bits)-1);
 267                 c->phys_proc_id >>= bits;
 268                 printk(KERN_INFO "CPU %d(%d) -> Core %d\n",
 269                        cpu, c->x86_max_cores, c->cpu_core_id);
 270         }
 271 #endif
 272
 273         if (cpuid_eax(0x80000000) >= 0x80000006)
 274                 num_cache_leaves = 3;
 275
 276         if (amd_apic_timer_broken())
 277                 set_bit(X86_FEATURE_LAPIC_TIMER_BROKEN, c->x86_capability);
 278 }
 279
 280 static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 * c, unsigned int size)
 281 {
 282         /* AMD errata T13 (order #21922) */
 283         if ((c->x86 == 6)) {
 284                 if (c->x86_model == 3 && c->x86_mask == 0)      /* Duron Rev A0 */
 285                         size = 64;
 286                 if (c->x86_model == 4 &&
 287                     (c->x86_mask==0 || c->x86_mask==1)) /* Tbird rev A1/A2 */
 288                         size = 256;
 289         }
 290         return size;
 291 }
 292
 293 static struct cpu_dev amd_cpu_dev __cpuinitdata = {
 294         .c_vendor       = "AMD",
 295         .c_ident        = { "AuthenticAMD" },
 296         .c_models = {
 297                 { .vendor = X86_VENDOR_AMD, .family = 4, .model_names =
 298                   {
 299                           [3] = "486 DX/2",
 300                           [7] = "486 DX/2-WB",
 301                           [8] = "486 DX/4",
 302                           [9] = "486 DX/4-WB",
 303                           [14] = "Am5x86-WT",
 304                           [15] = "Am5x86-WB"
 305                   }
 306                 },
 307         },
 308         .c_init         = init_amd,
 309         .c_size_cache   = amd_size_cache,
 310 };
 311
 312 int __init amd_init_cpu(void)
 313 {
 314         cpu_devs[X86_VENDOR_AMD] = &amd_cpu_dev;
 315         return 0;
 316 }
 317
 318 //early_arch_initcall(amd_init_cpu);
 319
 320 static int __init amd_exit_cpu(void)
 321 {
 322         cpu_devs[X86_VENDOR_AMD] = NULL;
 323         return 0;
 324 }
 325
 326 late_initcall(amd_exit_cpu);