arch/blackfin/mach-common/smp.c

   1 /*
   2  * IPI management based on arch/arm/kernel/smp.c (Copyright 2002 ARM Limited)
   3  *
   4  * Copyright 2007-2009 Analog Devices Inc.
   5  *                         Philippe Gerum <rpm@xenomai.org>
   6  *
   7  * Licensed under the GPL-2.
   8  */
   9
  10 #include <linux/module.h>
  11 #include <linux/delay.h>
  12 #include <linux/init.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/sched.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/cache.h>
  17 #include <linux/profile.h>
  18 #include <linux/errno.h>
  19 #include <linux/mm.h>
  20 #include <linux/cpu.h>
  21 #include <linux/smp.h>
  22 #include <linux/cpumask.h>
  23 #include <linux/seq_file.h>
  24 #include <linux/irq.h>
  25 #include <linux/slab.h>
  26 #include <asm/atomic.h>
  27 #include <asm/cacheflush.h>
  28 #include <asm/mmu_context.h>
  29 #include <asm/pgtable.h>
  30 #include <asm/pgalloc.h>
  31 #include <asm/processor.h>
  32 #include <asm/ptrace.h>
  33 #include <asm/cpu.h>
  34 #include <asm/time.h>
  35 #include <linux/err.h>
  36
  37 /*
  38  * Anomaly notes:
  39  * 05000120 - we always define corelock as 32-bit integer in L2
  40  */
  41 struct corelock_slot corelock __attribute__ ((__section__(".l2.bss")));
  42
  43 #ifdef CONFIG_ICACHE_FLUSH_L1
  44 unsigned long blackfin_iflush_l1_entry[NR_CPUS];
  45 #endif
  46
  47 void __cpuinitdata *init_retx_coreb, *init_saved_retx_coreb,
  48         *init_saved_seqstat_coreb, *init_saved_icplb_fault_addr_coreb,
  49         *init_saved_dcplb_fault_addr_coreb;
  50
  51 #define BFIN_IPI_RESCHEDULE   0
  52 #define BFIN_IPI_CALL_FUNC    1
  53 #define BFIN_IPI_CPU_STOP     2
  54
  55 struct blackfin_flush_data {
  56         unsigned long start;
  57         unsigned long end;
  58 };
  59
  60 void *secondary_stack;
  61
  62
  63 struct smp_call_struct {
  64         void (*func)(void *info);
  65         void *info;
  66         int wait;
  67         cpumask_t *waitmask;
  68 };
  69
  70 static struct blackfin_flush_data smp_flush_data;
  71
  72 static DEFINE_SPINLOCK(stop_lock);
  73
  74 struct ipi_message {
  75         unsigned long type;
  76         struct smp_call_struct call_struct;
  77 };
  78
  79 /* A magic number - stress test shows this is safe for common cases */
  80 #define BFIN_IPI_MSGQ_LEN 5
  81
  82 /* Simple FIFO buffer, overflow leads to panic */
  83 struct ipi_message_queue {
  84         spinlock_t lock;
  85         unsigned long count;
  86         unsigned long head; /* head of the queue */
  87         struct ipi_message ipi_message[BFIN_IPI_MSGQ_LEN];
  88 };
  89
  90 static DEFINE_PER_CPU(struct ipi_message_queue, ipi_msg_queue);
  91
  92 static void ipi_cpu_stop(unsigned int cpu)
  93 {
  94         spin_lock(&stop_lock);
  95         printk(KERN_CRIT "CPU%u: stopping\n", cpu);
  96         dump_stack();
  97         spin_unlock(&stop_lock);
  98
  99         cpu_clear(cpu, cpu_online_map);
 100
 101         local_irq_disable();
 102
 103         while (1)
 104                 SSYNC();
 105 }
 106
 107 static void ipi_flush_icache(void *info)
 108 {
 109         struct blackfin_flush_data *fdata = info;
 110
 111         /* Invalidate the memory holding the bounds of the flushed region. */
 112         blackfin_dcache_invalidate_range((unsigned long)fdata,
 113                                          (unsigned long)fdata + sizeof(*fdata));
 114
 115         /* Make sure all write buffers in the data side of the core
 116          * are flushed before trying to invalidate the icache.  This
 117          * needs to be after the data flush and before the icache
 118          * flush so that the SSYNC does the right thing in preventing
 119          * the instruction prefetcher from hitting things in cached
 120          * memory at the wrong time -- it runs much further ahead than
 121          * the pipeline.
 122          */
 123         SSYNC();
 124
 125         /* ipi_flaush_icache is invoked by generic flush_icache_range,
 126          * so call blackfin arch icache flush directly here.
 127          */
 128         blackfin_icache_flush_range(fdata->start, fdata->end);
 129 }
 130
 131 static void ipi_call_function(unsigned int cpu, struct ipi_message *msg)
 132 {
 133         int wait;
 134         void (*func)(void *info);
 135         void *info;
 136         func = msg->call_struct.func;
 137         info = msg->call_struct.info;
 138         wait = msg->call_struct.wait;
 139         func(info);
 140         if (wait) {
 141 #ifdef __ARCH_SYNC_CORE_DCACHE
 142                 /*
 143                  * 'wait' usually means synchronization between CPUs.
 144                  * Invalidate D cache in case shared data was changed
 145                  * by func() to ensure cache coherence.
 146                  */
 147                 resync_core_dcache();
 148 #endif
 149                 cpu_clear(cpu, *msg->call_struct.waitmask);
 150         }
 151 }
 152
 153 /* Use IRQ_SUPPLE_0 to request reschedule.
 154  * When returning from interrupt to user space,
 155  * there is chance to reschedule */
 156 static irqreturn_t ipi_handler_int0(int irq, void *dev_instance)
 157 {
 158         unsigned int cpu = smp_processor_id();
 159
 160         platform_clear_ipi(cpu, IRQ_SUPPLE_0);
 161         return IRQ_HANDLED;
 162 }
 163
 164 static irqreturn_t ipi_handler_int1(int irq, void *dev_instance)
 165 {
 166         struct ipi_message *msg;
 167         struct ipi_message_queue *msg_queue;
 168         unsigned int cpu = smp_processor_id();
 169         unsigned long flags;
 170
 171         platform_clear_ipi(cpu, IRQ_SUPPLE_1);
 172
 173         msg_queue = &__get_cpu_var(ipi_msg_queue);
 174
 175         spin_lock_irqsave(&msg_queue->lock, flags);
 176
 177         while (msg_queue->count) {
 178                 msg = &msg_queue->ipi_message[msg_queue->head];
 179                 switch (msg->type) {
 180                 case BFIN_IPI_RESCHEDULE:
 181                         scheduler_ipi();
 182                         break;
 183                 case BFIN_IPI_CALL_FUNC:
 184                         spin_unlock_irqrestore(&msg_queue->lock, flags);
 185                         ipi_call_function(cpu, msg);
 186                         spin_lock_irqsave(&msg_queue->lock, flags);
 187                         break;
 188                 case BFIN_IPI_CPU_STOP:
 189                         spin_unlock_irqrestore(&msg_queue->lock, flags);
 190                         ipi_cpu_stop(cpu);
 191                         spin_lock_irqsave(&msg_queue->lock, flags);
 192                         break;
 193                 default:
 194                         printk(KERN_CRIT "CPU%u: Unknown IPI message 0x%lx\n",
 195                                cpu, msg->type);
 196                         break;
 197                 }
 198                 msg_queue->head++;
 199                 msg_queue->head %= BFIN_IPI_MSGQ_LEN;
 200                 msg_queue->count--;
 201         }
 202         spin_unlock_irqrestore(&msg_queue->lock, flags);
 203         return IRQ_HANDLED;
 204 }
 205
 206 static void ipi_queue_init(void)
 207 {
 208         unsigned int cpu;
 209         struct ipi_message_queue *msg_queue;
 210         for_each_possible_cpu(cpu) {
 211                 msg_queue = &per_cpu(ipi_msg_queue, cpu);
 212                 spin_lock_init(&msg_queue->lock);
 213                 msg_queue->count = 0;
 214                 msg_queue->head = 0;
 215         }
 216 }
 217
 218 static inline void smp_send_message(cpumask_t callmap, unsigned long type,
 219                                         void (*func) (void *info), void *info, int wait)
 220 {
 221         unsigned int cpu;
 222         struct ipi_message_queue *msg_queue;
 223         struct ipi_message *msg;
 224         unsigned long flags, next_msg;
 225         cpumask_t waitmask = callmap; /* waitmask is shared by all cpus */
 226
 227         for_each_cpu_mask(cpu, callmap) {
 228                 msg_queue = &per_cpu(ipi_msg_queue, cpu);
 229                 spin_lock_irqsave(&msg_queue->lock, flags);
 230                 if (msg_queue->count < BFIN_IPI_MSGQ_LEN) {
 231                         next_msg = (msg_queue->head + msg_queue->count)
 232                                         % BFIN_IPI_MSGQ_LEN;
 233                         msg = &msg_queue->ipi_message[next_msg];
 234                         msg->type = type;
 235                         if (type == BFIN_IPI_CALL_FUNC) {
 236                                 msg->call_struct.func = func;
 237                                 msg->call_struct.info = info;
 238                                 msg->call_struct.wait = wait;
 239                                 msg->call_struct.waitmask = &waitmask;
 240                         }
 241                         msg_queue->count++;
 242                 } else
 243                         panic("IPI message queue overflow\n");
 244                 spin_unlock_irqrestore(&msg_queue->lock, flags);
 245                 platform_send_ipi_cpu(cpu, IRQ_SUPPLE_1);
 246         }
 247
 248         if (wait) {
 249                 while (!cpus_empty(waitmask))
 250                         blackfin_dcache_invalidate_range(
 251                                 (unsigned long)(&waitmask),
 252                                 (unsigned long)(&waitmask));
 253 #ifdef __ARCH_SYNC_CORE_DCACHE
 254                 /*
 255                  * Invalidate D cache in case shared data was changed by
 256                  * other processors to ensure cache coherence.
 257                  */
 258                 resync_core_dcache();
 259 #endif
 260         }
 261 }
 262
 263 int smp_call_function(void (*func)(void *info), void *info, int wait)
 264 {
 265         cpumask_t callmap;
 266
 267         preempt_disable();
 268         callmap = cpu_online_map;
 269         cpu_clear(smp_processor_id(), callmap);
 270         if (!cpus_empty(callmap))
 271                 smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait);
 272
 273         preempt_enable();
 274
 275         return 0;
 276 }
 277 EXPORT_SYMBOL_GPL(smp_call_function);
 278
 279 int smp_call_function_single(int cpuid, void (*func) (void *info), void *info,
 280                                 int wait)
 281 {
 282         unsigned int cpu = cpuid;
 283         cpumask_t callmap;
 284
 285         if (cpu_is_offline(cpu))
 286                 return 0;
 287         cpus_clear(callmap);
 288         cpu_set(cpu, callmap);
 289
 290         smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait);
 291
 292         return 0;
 293 }
 294 EXPORT_SYMBOL_GPL(smp_call_function_single);
 295
 296 void smp_send_reschedule(int cpu)
 297 {
 298         /* simply trigger an ipi */
 299         if (cpu_is_offline(cpu))
 300                 return;
 301         platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);
 302
 303         return;
 304 }
 305
 306 void smp_send_stop(void)
 307 {
 308         cpumask_t callmap;
 309
 310         preempt_disable();
 311         callmap = cpu_online_map;
 312         cpu_clear(smp_processor_id(), callmap);
 313         if (!cpus_empty(callmap))
 314                 smp_send_message(callmap, BFIN_IPI_CPU_STOP, NULL, NULL, 0);
 315
 316         preempt_enable();
 317
 318         return;
 319 }
 320
 321 int __cpuinit __cpu_up(unsigned int cpu)
 322 {
 323         int ret;
 324         static struct task_struct *idle;
 325
 326         if (idle)
 327                 free_task(idle);
 328
 329         idle = fork_idle(cpu);
 330         if (IS_ERR(idle)) {
 331                 printk(KERN_ERR "CPU%u: fork() failed\n", cpu);
 332                 return PTR_ERR(idle);
 333         }
 334
 335         secondary_stack = task_stack_page(idle) + THREAD_SIZE;
 336
 337         ret = platform_boot_secondary(cpu, idle);
 338
 339         secondary_stack = NULL;
 340
 341         return ret;
 342 }
 343
 344 static void __cpuinit setup_secondary(unsigned int cpu)
 345 {
 346         unsigned long ilat;
 347
 348         bfin_write_IMASK(0);
 349         CSYNC();
 350         ilat = bfin_read_ILAT();
 351         CSYNC();
 352         bfin_write_ILAT(ilat);
 353         CSYNC();
 354
 355         /* Enable interrupt levels IVG7-15. IARs have been already
 356          * programmed by the boot CPU.  */
 357         bfin_irq_flags |= IMASK_IVG15 |
 358             IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
 359             IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
 360 }
 361
 362 void __cpuinit secondary_start_kernel(void)
 363 {
 364         unsigned int cpu = smp_processor_id();
 365         struct mm_struct *mm = &init_mm;
 366
 367         if (_bfin_swrst & SWRST_DBL_FAULT_B) {
 368                 printk(KERN_EMERG "CoreB Recovering from DOUBLE FAULT event\n");
 369 #ifdef CONFIG_DEBUG_DOUBLEFAULT
 370                 printk(KERN_EMERG " While handling exception (EXCAUSE = 0x%x) at %pF\n",
 371                         (int)init_saved_seqstat_coreb & SEQSTAT_EXCAUSE, init_saved_retx_coreb);
 372                 printk(KERN_NOTICE "   DCPLB_FAULT_ADDR: %pF\n", init_saved_dcplb_fault_addr_coreb);
 373                 printk(KERN_NOTICE "   ICPLB_FAULT_ADDR: %pF\n", init_saved_icplb_fault_addr_coreb);
 374 #endif
 375                 printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
 376                         init_retx_coreb);
 377         }
 378
 379         /*
 380          * We want the D-cache to be enabled early, in case the atomic
 381          * support code emulates cache coherence (see
 382          * __ARCH_SYNC_CORE_DCACHE).
 383          */
 384         init_exception_vectors();
 385
 386         local_irq_disable();
 387
 388         /* Attach the new idle task to the global mm. */
 389         atomic_inc(&mm->mm_users);
 390         atomic_inc(&mm->mm_count);
 391         current->active_mm = mm;
 392
 393         preempt_disable();
 394
 395         setup_secondary(cpu);
 396
 397         platform_secondary_init(cpu);
 398
 399         /* setup local core timer */
 400         bfin_local_timer_setup();
 401
 402         local_irq_enable();
 403
 404         bfin_setup_caches(cpu);
 405
 406         /*
 407          * Calibrate loops per jiffy value.
 408          * IRQs need to be enabled here - D-cache can be invalidated
 409          * in timer irq handler, so core B can read correct jiffies.
 410          */
 411         calibrate_delay();
 412
 413         cpu_idle();
 414 }
 415
 416 void __init smp_prepare_boot_cpu(void)
 417 {
 418 }
 419
 420 void __init smp_prepare_cpus(unsigned int max_cpus)
 421 {
 422         platform_prepare_cpus(max_cpus);
 423         ipi_queue_init();
 424         platform_request_ipi(IRQ_SUPPLE_0, ipi_handler_int0);
 425         platform_request_ipi(IRQ_SUPPLE_1, ipi_handler_int1);
 426 }
 427
 428 void __init smp_cpus_done(unsigned int max_cpus)
 429 {
 430         unsigned long bogosum = 0;
 431         unsigned int cpu;
 432
 433         for_each_online_cpu(cpu)
 434                 bogosum += loops_per_jiffy;
 435
 436         printk(KERN_INFO "SMP: Total of %d processors activated "
 437                "(%lu.%02lu BogoMIPS).\n",
 438                num_online_cpus(),
 439                bogosum / (500000/HZ),
 440                (bogosum / (5000/HZ)) % 100);
 441 }
 442
 443 void smp_icache_flush_range_others(unsigned long start, unsigned long end)
 444 {
 445         smp_flush_data.start = start;
 446         smp_flush_data.end = end;
 447
 448         if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 0))
 449                 printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n");
 450 }
 451 EXPORT_SYMBOL_GPL(smp_icache_flush_range_others);
 452
 453 #ifdef __ARCH_SYNC_CORE_ICACHE
 454 unsigned long icache_invld_count[NR_CPUS];
 455 void resync_core_icache(void)
 456 {
 457         unsigned int cpu = get_cpu();
 458         blackfin_invalidate_entire_icache();
 459         icache_invld_count[cpu]++;
 460         put_cpu();
 461 }
 462 EXPORT_SYMBOL(resync_core_icache);
 463 #endif
 464
 465 #ifdef __ARCH_SYNC_CORE_DCACHE
 466 unsigned long dcache_invld_count[NR_CPUS];
 467 unsigned long barrier_mask __attribute__ ((__section__(".l2.bss")));
 468
 469 void resync_core_dcache(void)
 470 {
 471         unsigned int cpu = get_cpu();
 472         blackfin_invalidate_entire_dcache();
 473         dcache_invld_count[cpu]++;
 474         put_cpu();
 475 }
 476 EXPORT_SYMBOL(resync_core_dcache);
 477 #endif
 478
 479 #ifdef CONFIG_HOTPLUG_CPU
 480 int __cpuexit __cpu_disable(void)
 481 {
 482         unsigned int cpu = smp_processor_id();
 483
 484         if (cpu == 0)
 485                 return -EPERM;
 486
 487         set_cpu_online(cpu, false);
 488         return 0;
 489 }
 490
 491 static DECLARE_COMPLETION(cpu_killed);
 492
 493 int __cpuexit __cpu_die(unsigned int cpu)
 494 {
 495         return wait_for_completion_timeout(&cpu_killed, 5000);
 496 }
 497
 498 void cpu_die(void)
 499 {
 500         complete(&cpu_killed);
 501
 502         atomic_dec(&init_mm.mm_users);
 503         atomic_dec(&init_mm.mm_count);
 504
 505         local_irq_disable();
 506         platform_cpu_die();
 507 }
 508 #endif