2 * Blackfin power management
4 * Copyright 2006-2009 Analog Devices Inc.
6 * Licensed under the GPL-2
7 * based on arm/mach-omap/pm.c
8 * Copyright 2001, Cliff Brake <cbrake@accelent.com> and others
11 #include <linux/suspend.h>
12 #include <linux/sched.h>
13 #include <linux/proc_fs.h>
14 #include <linux/slab.h>
16 #include <linux/irq.h>
24 void bfin_pm_suspend_standby_enter(void)
28 local_irq_save_hw(flags);
29 bfin_pm_standby_setup();
31 #ifdef CONFIG_PM_BFIN_SLEEP_DEEPER
32 sleep_deeper(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
34 sleep_mode(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
37 bfin_pm_standby_restore();
40 bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
42 /* BF52x system reset does not properly reset SIC_IWR1 which
43 * will screw up the bootrom as it relies on MDMA0/1 waking it
44 * up from IDLE instructions. See this report for more info:
45 * http://blackfin.uclinux.org/gf/tracker/4323
48 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
50 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
53 bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
56 bfin_write_SIC_IWR(IWR_DISABLE_ALL);
59 local_irq_restore_hw(flags);
62 int bf53x_suspend_l1_mem(unsigned char *memptr)
64 dma_memcpy(memptr, (const void *) L1_CODE_START, L1_CODE_LENGTH);
65 dma_memcpy(memptr + L1_CODE_LENGTH, (const void *) L1_DATA_A_START,
67 dma_memcpy(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH,
68 (const void *) L1_DATA_B_START, L1_DATA_B_LENGTH);
69 memcpy(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH +
70 L1_DATA_B_LENGTH, (const void *) L1_SCRATCH_START,
76 int bf53x_resume_l1_mem(unsigned char *memptr)
78 dma_memcpy((void *) L1_CODE_START, memptr, L1_CODE_LENGTH);
79 dma_memcpy((void *) L1_DATA_A_START, memptr + L1_CODE_LENGTH,
81 dma_memcpy((void *) L1_DATA_B_START, memptr + L1_CODE_LENGTH +
82 L1_DATA_A_LENGTH, L1_DATA_B_LENGTH);
83 memcpy((void *) L1_SCRATCH_START, memptr + L1_CODE_LENGTH +
84 L1_DATA_A_LENGTH + L1_DATA_B_LENGTH, L1_SCRATCH_LENGTH);
89 #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
90 static void flushinv_all_dcache(void)
92 u32 way, bank, subbank, set;
94 u32 dmem_ctl = bfin_read_DMEM_CONTROL();
96 for (bank = 0; bank < 2; ++bank) {
97 if (!(dmem_ctl & (1 << (DMC1_P - bank))))
100 for (way = 0; way < 2; ++way)
101 for (subbank = 0; subbank < 4; ++subbank)
102 for (set = 0; set < 64; ++set) {
104 bfin_write_DTEST_COMMAND(
111 status = bfin_read_DTEST_DATA0();
113 /* only worry about valid/dirty entries */
114 if ((status & 0x3) != 0x3)
117 /* construct the address using the tag */
118 addr = (status & 0xFFFFC800) | (subbank << 12) | (set << 5);
121 __asm__ __volatile__("FLUSHINV[%0];" : : "a"(addr));
127 int bfin_pm_suspend_mem_enter(void)
132 unsigned char *memptr = kmalloc(L1_CODE_LENGTH + L1_DATA_A_LENGTH
133 + L1_DATA_B_LENGTH + L1_SCRATCH_LENGTH,
136 if (memptr == NULL) {
137 panic("bf53x_suspend_l1_mem malloc failed");
141 wakeup = bfin_read_VR_CTL() & ~FREQ;
144 #ifdef CONFIG_PM_BFIN_WAKE_PH6
147 #ifdef CONFIG_PM_BFIN_WAKE_GP
151 local_irq_save_hw(flags);
153 ret = blackfin_dma_suspend();
156 local_irq_restore_hw(flags);
161 bfin_gpio_pm_hibernate_suspend();
163 #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
164 flushinv_all_dcache();
168 bf53x_suspend_l1_mem(memptr);
170 do_hibernate(wakeup | vr_wakeup); /* Goodbye */
172 bf53x_resume_l1_mem(memptr);
177 bfin_gpio_pm_hibernate_restore();
178 blackfin_dma_resume();
180 local_irq_restore_hw(flags);
187 * bfin_pm_valid - Tell the PM core that we only support the standby sleep
189 * @state: suspend state we're checking.
192 static int bfin_pm_valid(suspend_state_t state)
194 return (state == PM_SUSPEND_STANDBY
195 #if !(defined(BF533_FAMILY) || defined(CONFIG_BF561))
198 * If we enter Hibernate the SCKE Pin is driven Low,
199 * so that the SDRAM enters Self Refresh Mode.
200 * However when the reset sequence that follows hibernate
201 * state is executed, SCKE is driven High, taking the
202 * SDRAM out of Self Refresh.
204 * If you reconfigure and access the SDRAM "very quickly",
205 * you are likely to avoid errors, otherwise the SDRAM
206 * start losing its contents.
207 * An external HW workaround is possible using logic gates.
209 || state == PM_SUSPEND_MEM
215 * bfin_pm_enter - Actually enter a sleep state.
216 * @state: State we're entering.
219 static int bfin_pm_enter(suspend_state_t state)
222 case PM_SUSPEND_STANDBY:
223 bfin_pm_suspend_standby_enter();
226 bfin_pm_suspend_mem_enter();
235 struct platform_suspend_ops bfin_pm_ops = {
236 .enter = bfin_pm_enter,
237 .valid = bfin_pm_valid,
240 static int __init bfin_pm_init(void)
242 suspend_set_ops(&bfin_pm_ops);
246 __initcall(bfin_pm_init);