arch/blackfin/mach-common/ints-priority.c

   1 /*
   2  * Set up the interrupt priorities
   3  *
   4  * Copyright  2004-2009 Analog Devices Inc.
   5  *                 2003 Bas Vermeulen <bas@buyways.nl>
   6  *                 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
   7  *            2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
   8  *                 1999 D. Jeff Dionne <jeff@uclinux.org>
   9  *                 1996 Roman Zippel
  10  *
  11  * Licensed under the GPL-2
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/kernel_stat.h>
  16 #include <linux/seq_file.h>
  17 #include <linux/irq.h>
  18 #ifdef CONFIG_IPIPE
  19 #include <linux/ipipe.h>
  20 #endif
  21 #ifdef CONFIG_KGDB
  22 #include <linux/kgdb.h>
  23 #endif
  24 #include <asm/traps.h>
  25 #include <asm/blackfin.h>
  26 #include <asm/gpio.h>
  27 #include <asm/irq_handler.h>
  28 #include <asm/dpmc.h>
  29 #include <asm/bfin5xx_spi.h>
  30 #include <asm/bfin_sport.h>
  31 #include <asm/bfin_can.h>
  32
  33 #define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
  34
  35 #ifdef BF537_FAMILY
  36 # define BF537_GENERIC_ERROR_INT_DEMUX
  37 # define SPI_ERR_MASK   (BIT_STAT_TXCOL | BIT_STAT_RBSY | BIT_STAT_MODF | BIT_STAT_TXE) /* SPI_STAT */
  38 # define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF)     /* SPORT_STAT */
  39 # define PPI_ERR_MASK   (0xFFFF & ~FLD) /* PPI_STATUS */
  40 # define EMAC_ERR_MASK  (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */
  41 # define UART_ERR_MASK  (0x6)   /* UART_IIR */
  42 # define CAN_ERR_MASK   (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF)      /* CAN_GIF */
  43 #else
  44 # undef BF537_GENERIC_ERROR_INT_DEMUX
  45 #endif
  46
  47 /*
  48  * NOTES:
  49  * - we have separated the physical Hardware interrupt from the
  50  * levels that the LINUX kernel sees (see the description in irq.h)
  51  * -
  52  */
  53
  54 #ifndef CONFIG_SMP
  55 /* Initialize this to an actual value to force it into the .data
  56  * section so that we know it is properly initialized at entry into
  57  * the kernel but before bss is initialized to zero (which is where
  58  * it would live otherwise).  The 0x1f magic represents the IRQs we
  59  * cannot actually mask out in hardware.
  60  */
  61 unsigned long bfin_irq_flags = 0x1f;
  62 EXPORT_SYMBOL(bfin_irq_flags);
  63 #endif
  64
  65 /* The number of spurious interrupts */
  66 atomic_t num_spurious;
  67
  68 #ifdef CONFIG_PM
  69 unsigned long bfin_sic_iwr[3];  /* Up to 3 SIC_IWRx registers */
  70 unsigned vr_wakeup;
  71 #endif
  72
  73 struct ivgx {
  74         /* irq number for request_irq, available in mach-bf5xx/irq.h */
  75         unsigned int irqno;
  76         /* corresponding bit in the SIC_ISR register */
  77         unsigned int isrflag;
  78 } ivg_table[NR_PERI_INTS];
  79
  80 struct ivg_slice {
  81         /* position of first irq in ivg_table for given ivg */
  82         struct ivgx *ifirst;
  83         struct ivgx *istop;
  84 } ivg7_13[IVG13 - IVG7 + 1];
  85
  86
  87 /*
  88  * Search SIC_IAR and fill tables with the irqvalues
  89  * and their positions in the SIC_ISR register.
  90  */
  91 static void __init search_IAR(void)
  92 {
  93         unsigned ivg, irq_pos = 0;
  94         for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
  95                 int irqN;
  96
  97                 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
  98
  99                 for (irqN = 0; irqN < NR_PERI_INTS; irqN += 4) {
 100                         int irqn;
 101                         u32 iar = bfin_read32((unsigned long *)SIC_IAR0 +
 102 #if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || \
 103         defined(CONFIG_BF538) || defined(CONFIG_BF539)
 104                                 ((irqN % 32) >> 3) + ((irqN / 32) * ((SIC_IAR4 - SIC_IAR0) / 4))
 105 #else
 106                                 (irqN >> 3)
 107 #endif
 108                                 );
 109
 110                         for (irqn = irqN; irqn < irqN + 4; ++irqn) {
 111                                 int iar_shift = (irqn & 7) * 4;
 112                                 if (ivg == (0xf & (iar >> iar_shift))) {
 113                                         ivg_table[irq_pos].irqno = IVG7 + irqn;
 114                                         ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
 115                                         ivg7_13[ivg].istop++;
 116                                         irq_pos++;
 117                                 }
 118                         }
 119                 }
 120         }
 121 }
 122
 123 /*
 124  * This is for core internal IRQs
 125  */
 126
 127 static void bfin_ack_noop(unsigned int irq)
 128 {
 129         /* Dummy function.  */
 130 }
 131
 132 static void bfin_core_mask_irq(unsigned int irq)
 133 {
 134         bfin_irq_flags &= ~(1 << irq);
 135         if (!hard_irqs_disabled())
 136                 hard_local_irq_enable();
 137 }
 138
 139 static void bfin_core_unmask_irq(unsigned int irq)
 140 {
 141         bfin_irq_flags |= 1 << irq;
 142         /*
 143          * If interrupts are enabled, IMASK must contain the same value
 144          * as bfin_irq_flags.  Make sure that invariant holds.  If interrupts
 145          * are currently disabled we need not do anything; one of the
 146          * callers will take care of setting IMASK to the proper value
 147          * when reenabling interrupts.
 148          * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
 149          * what we need.
 150          */
 151         if (!hard_irqs_disabled())
 152                 hard_local_irq_enable();
 153         return;
 154 }
 155
 156 static void bfin_internal_mask_irq(unsigned int irq)
 157 {
 158         unsigned long flags;
 159
 160 #ifdef CONFIG_BF53x
 161         flags = hard_local_irq_save();
 162         bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
 163                              ~(1 << SIC_SYSIRQ(irq)));
 164 #else
 165         unsigned mask_bank, mask_bit;
 166         flags = hard_local_irq_save();
 167         mask_bank = SIC_SYSIRQ(irq) / 32;
 168         mask_bit = SIC_SYSIRQ(irq) % 32;
 169         bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
 170                              ~(1 << mask_bit));
 171 #ifdef CONFIG_SMP
 172         bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
 173                              ~(1 << mask_bit));
 174 #endif
 175 #endif
 176         hard_local_irq_restore(flags);
 177 }
 178
 179 #ifdef CONFIG_SMP
 180 static void bfin_internal_unmask_irq_affinity(unsigned int irq,
 181                 const struct cpumask *affinity)
 182 #else
 183 static void bfin_internal_unmask_irq(unsigned int irq)
 184 #endif
 185 {
 186         unsigned long flags;
 187
 188 #ifdef CONFIG_BF53x
 189         flags = hard_local_irq_save();
 190         bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
 191                              (1 << SIC_SYSIRQ(irq)));
 192 #else
 193         unsigned mask_bank, mask_bit;
 194         flags = hard_local_irq_save();
 195         mask_bank = SIC_SYSIRQ(irq) / 32;
 196         mask_bit = SIC_SYSIRQ(irq) % 32;
 197 #ifdef CONFIG_SMP
 198         if (cpumask_test_cpu(0, affinity))
 199 #endif
 200                 bfin_write_SIC_IMASK(mask_bank,
 201                         bfin_read_SIC_IMASK(mask_bank) |
 202                         (1 << mask_bit));
 203 #ifdef CONFIG_SMP
 204         if (cpumask_test_cpu(1, affinity))
 205                 bfin_write_SICB_IMASK(mask_bank,
 206                         bfin_read_SICB_IMASK(mask_bank) |
 207                         (1 << mask_bit));
 208 #endif
 209 #endif
 210         hard_local_irq_restore(flags);
 211 }
 212
 213 #ifdef CONFIG_SMP
 214 static void bfin_internal_unmask_irq(unsigned int irq)
 215 {
 216         struct irq_desc *desc = irq_to_desc(irq);
 217         bfin_internal_unmask_irq_affinity(irq, desc->affinity);
 218 }
 219
 220 static int bfin_internal_set_affinity(unsigned int irq, const struct cpumask *mask)
 221 {
 222         bfin_internal_mask_irq(irq);
 223         bfin_internal_unmask_irq_affinity(irq, mask);
 224
 225         return 0;
 226 }
 227 #endif
 228
 229 #ifdef CONFIG_PM
 230 int bfin_internal_set_wake(unsigned int irq, unsigned int state)
 231 {
 232         u32 bank, bit, wakeup = 0;
 233         unsigned long flags;
 234         bank = SIC_SYSIRQ(irq) / 32;
 235         bit = SIC_SYSIRQ(irq) % 32;
 236
 237         switch (irq) {
 238 #ifdef IRQ_RTC
 239         case IRQ_RTC:
 240         wakeup |= WAKE;
 241         break;
 242 #endif
 243 #ifdef IRQ_CAN0_RX
 244         case IRQ_CAN0_RX:
 245         wakeup |= CANWE;
 246         break;
 247 #endif
 248 #ifdef IRQ_CAN1_RX
 249         case IRQ_CAN1_RX:
 250         wakeup |= CANWE;
 251         break;
 252 #endif
 253 #ifdef IRQ_USB_INT0
 254         case IRQ_USB_INT0:
 255         wakeup |= USBWE;
 256         break;
 257 #endif
 258 #ifdef CONFIG_BF54x
 259         case IRQ_CNT:
 260         wakeup |= ROTWE;
 261         break;
 262 #endif
 263         default:
 264         break;
 265         }
 266
 267         flags = hard_local_irq_save();
 268
 269         if (state) {
 270                 bfin_sic_iwr[bank] |= (1 << bit);
 271                 vr_wakeup  |= wakeup;
 272
 273         } else {
 274                 bfin_sic_iwr[bank] &= ~(1 << bit);
 275                 vr_wakeup  &= ~wakeup;
 276         }
 277
 278         hard_local_irq_restore(flags);
 279
 280         return 0;
 281 }
 282 #endif
 283
 284 static struct irq_chip bfin_core_irqchip = {
 285         .name = "CORE",
 286         .ack = bfin_ack_noop,
 287         .mask = bfin_core_mask_irq,
 288         .unmask = bfin_core_unmask_irq,
 289 };
 290
 291 static struct irq_chip bfin_internal_irqchip = {
 292         .name = "INTN",
 293         .ack = bfin_ack_noop,
 294         .mask = bfin_internal_mask_irq,
 295         .unmask = bfin_internal_unmask_irq,
 296         .mask_ack = bfin_internal_mask_irq,
 297         .disable = bfin_internal_mask_irq,
 298         .enable = bfin_internal_unmask_irq,
 299 #ifdef CONFIG_SMP
 300         .set_affinity = bfin_internal_set_affinity,
 301 #endif
 302 #ifdef CONFIG_PM
 303         .set_wake = bfin_internal_set_wake,
 304 #endif
 305 };
 306
 307 static void bfin_handle_irq(unsigned irq)
 308 {
 309 #ifdef CONFIG_IPIPE
 310         struct pt_regs regs;    /* Contents not used. */
 311         ipipe_trace_irq_entry(irq);
 312         __ipipe_handle_irq(irq, &regs);
 313         ipipe_trace_irq_exit(irq);
 314 #else /* !CONFIG_IPIPE */
 315         struct irq_desc *desc = irq_desc + irq;
 316         desc->handle_irq(irq, desc);
 317 #endif  /* !CONFIG_IPIPE */
 318 }
 319
 320 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
 321 static int error_int_mask;
 322
 323 static void bfin_generic_error_mask_irq(unsigned int irq)
 324 {
 325         error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR));
 326         if (!error_int_mask)
 327                 bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
 328 }
 329
 330 static void bfin_generic_error_unmask_irq(unsigned int irq)
 331 {
 332         bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
 333         error_int_mask |= 1L << (irq - IRQ_PPI_ERROR);
 334 }
 335
 336 static struct irq_chip bfin_generic_error_irqchip = {
 337         .name = "ERROR",
 338         .ack = bfin_ack_noop,
 339         .mask_ack = bfin_generic_error_mask_irq,
 340         .mask = bfin_generic_error_mask_irq,
 341         .unmask = bfin_generic_error_unmask_irq,
 342 };
 343
 344 static void bfin_demux_error_irq(unsigned int int_err_irq,
 345                                  struct irq_desc *inta_desc)
 346 {
 347         int irq = 0;
 348
 349 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
 350         if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
 351                 irq = IRQ_MAC_ERROR;
 352         else
 353 #endif
 354         if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
 355                 irq = IRQ_SPORT0_ERROR;
 356         else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
 357                 irq = IRQ_SPORT1_ERROR;
 358         else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
 359                 irq = IRQ_PPI_ERROR;
 360         else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
 361                 irq = IRQ_CAN_ERROR;
 362         else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
 363                 irq = IRQ_SPI_ERROR;
 364         else if ((bfin_read_UART0_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
 365                 irq = IRQ_UART0_ERROR;
 366         else if ((bfin_read_UART1_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
 367                 irq = IRQ_UART1_ERROR;
 368
 369         if (irq) {
 370                 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR)))
 371                         bfin_handle_irq(irq);
 372                 else {
 373
 374                         switch (irq) {
 375                         case IRQ_PPI_ERROR:
 376                                 bfin_write_PPI_STATUS(PPI_ERR_MASK);
 377                                 break;
 378 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
 379                         case IRQ_MAC_ERROR:
 380                                 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
 381                                 break;
 382 #endif
 383                         case IRQ_SPORT0_ERROR:
 384                                 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
 385                                 break;
 386
 387                         case IRQ_SPORT1_ERROR:
 388                                 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
 389                                 break;
 390
 391                         case IRQ_CAN_ERROR:
 392                                 bfin_write_CAN_GIS(CAN_ERR_MASK);
 393                                 break;
 394
 395                         case IRQ_SPI_ERROR:
 396                                 bfin_write_SPI_STAT(SPI_ERR_MASK);
 397                                 break;
 398
 399                         default:
 400                                 break;
 401                         }
 402
 403                         pr_debug("IRQ %d:"
 404                                  " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
 405                                  irq);
 406                 }
 407         } else
 408                 printk(KERN_ERR
 409                        "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
 410                        " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
 411                        __func__, __FILE__, __LINE__);
 412
 413 }
 414 #endif                          /* BF537_GENERIC_ERROR_INT_DEMUX */
 415
 416 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
 417 static int mac_stat_int_mask;
 418
 419 static void bfin_mac_status_ack_irq(unsigned int irq)
 420 {
 421         switch (irq) {
 422         case IRQ_MAC_MMCINT:
 423                 bfin_write_EMAC_MMC_TIRQS(
 424                         bfin_read_EMAC_MMC_TIRQE() &
 425                         bfin_read_EMAC_MMC_TIRQS());
 426                 bfin_write_EMAC_MMC_RIRQS(
 427                         bfin_read_EMAC_MMC_RIRQE() &
 428                         bfin_read_EMAC_MMC_RIRQS());
 429                 break;
 430         case IRQ_MAC_RXFSINT:
 431                 bfin_write_EMAC_RX_STKY(
 432                         bfin_read_EMAC_RX_IRQE() &
 433                         bfin_read_EMAC_RX_STKY());
 434                 break;
 435         case IRQ_MAC_TXFSINT:
 436                 bfin_write_EMAC_TX_STKY(
 437                         bfin_read_EMAC_TX_IRQE() &
 438                         bfin_read_EMAC_TX_STKY());
 439                 break;
 440         case IRQ_MAC_WAKEDET:
 441                  bfin_write_EMAC_WKUP_CTL(
 442                         bfin_read_EMAC_WKUP_CTL() | MPKS | RWKS);
 443                 break;
 444         default:
 445                 /* These bits are W1C */
 446                 bfin_write_EMAC_SYSTAT(1L << (irq - IRQ_MAC_PHYINT));
 447                 break;
 448         }
 449 }
 450
 451 static void bfin_mac_status_mask_irq(unsigned int irq)
 452 {
 453         mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT));
 454 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
 455         switch (irq) {
 456         case IRQ_MAC_PHYINT:
 457                 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() & ~PHYIE);
 458                 break;
 459         default:
 460                 break;
 461         }
 462 #else
 463         if (!mac_stat_int_mask)
 464                 bfin_internal_mask_irq(IRQ_MAC_ERROR);
 465 #endif
 466         bfin_mac_status_ack_irq(irq);
 467 }
 468
 469 static void bfin_mac_status_unmask_irq(unsigned int irq)
 470 {
 471 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
 472         switch (irq) {
 473         case IRQ_MAC_PHYINT:
 474                 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() | PHYIE);
 475                 break;
 476         default:
 477                 break;
 478         }
 479 #else
 480         if (!mac_stat_int_mask)
 481                 bfin_internal_unmask_irq(IRQ_MAC_ERROR);
 482 #endif
 483         mac_stat_int_mask |= 1L << (irq - IRQ_MAC_PHYINT);
 484 }
 485
 486 #ifdef CONFIG_PM
 487 int bfin_mac_status_set_wake(unsigned int irq, unsigned int state)
 488 {
 489 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
 490         return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state);
 491 #else
 492         return bfin_internal_set_wake(IRQ_MAC_ERROR, state);
 493 #endif
 494 }
 495 #endif
 496
 497 static struct irq_chip bfin_mac_status_irqchip = {
 498         .name = "MACST",
 499         .ack = bfin_ack_noop,
 500         .mask_ack = bfin_mac_status_mask_irq,
 501         .mask = bfin_mac_status_mask_irq,
 502         .unmask = bfin_mac_status_unmask_irq,
 503 #ifdef CONFIG_PM
 504         .set_wake = bfin_mac_status_set_wake,
 505 #endif
 506 };
 507
 508 static void bfin_demux_mac_status_irq(unsigned int int_err_irq,
 509                                  struct irq_desc *inta_desc)
 510 {
 511         int i, irq = 0;
 512         u32 status = bfin_read_EMAC_SYSTAT();
 513
 514         for (i = 0; i <= (IRQ_MAC_STMDONE - IRQ_MAC_PHYINT); i++)
 515                 if (status & (1L << i)) {
 516                         irq = IRQ_MAC_PHYINT + i;
 517                         break;
 518                 }
 519
 520         if (irq) {
 521                 if (mac_stat_int_mask & (1L << (irq - IRQ_MAC_PHYINT))) {
 522                         bfin_handle_irq(irq);
 523                 } else {
 524                         bfin_mac_status_ack_irq(irq);
 525                         pr_debug("IRQ %d:"
 526                                  " MASKED MAC ERROR INTERRUPT ASSERTED\n",
 527                                  irq);
 528                 }
 529         } else
 530                 printk(KERN_ERR
 531                        "%s : %s : LINE %d :\nIRQ ?: MAC ERROR"
 532                        " INTERRUPT ASSERTED BUT NO SOURCE FOUND"
 533                        "(EMAC_SYSTAT=0x%X)\n",
 534                        __func__, __FILE__, __LINE__, status);
 535 }
 536 #endif
 537
 538 static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
 539 {
 540 #ifdef CONFIG_IPIPE
 541         _set_irq_handler(irq, handle_level_irq);
 542 #else
 543         struct irq_desc *desc = irq_desc + irq;
 544         /* May not call generic set_irq_handler() due to spinlock
 545            recursion. */
 546         desc->handle_irq = handle;
 547 #endif
 548 }
 549
 550 static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
 551 extern void bfin_gpio_irq_prepare(unsigned gpio);
 552
 553 #if !defined(CONFIG_BF54x)
 554
 555 static void bfin_gpio_ack_irq(unsigned int irq)
 556 {
 557         /* AFAIK ack_irq in case mask_ack is provided
 558          * get's only called for edge sense irqs
 559          */
 560         set_gpio_data(irq_to_gpio(irq), 0);
 561 }
 562
 563 static void bfin_gpio_mask_ack_irq(unsigned int irq)
 564 {
 565         struct irq_desc *desc = irq_desc + irq;
 566         u32 gpionr = irq_to_gpio(irq);
 567
 568         if (desc->handle_irq == handle_edge_irq)
 569                 set_gpio_data(gpionr, 0);
 570
 571         set_gpio_maska(gpionr, 0);
 572 }
 573
 574 static void bfin_gpio_mask_irq(unsigned int irq)
 575 {
 576         set_gpio_maska(irq_to_gpio(irq), 0);
 577 }
 578
 579 static void bfin_gpio_unmask_irq(unsigned int irq)
 580 {
 581         set_gpio_maska(irq_to_gpio(irq), 1);
 582 }
 583
 584 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
 585 {
 586         u32 gpionr = irq_to_gpio(irq);
 587
 588         if (__test_and_set_bit(gpionr, gpio_enabled))
 589                 bfin_gpio_irq_prepare(gpionr);
 590
 591         bfin_gpio_unmask_irq(irq);
 592
 593         return 0;
 594 }
 595
 596 static void bfin_gpio_irq_shutdown(unsigned int irq)
 597 {
 598         u32 gpionr = irq_to_gpio(irq);
 599
 600         bfin_gpio_mask_irq(irq);
 601         __clear_bit(gpionr, gpio_enabled);
 602         bfin_gpio_irq_free(gpionr);
 603 }
 604
 605 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
 606 {
 607         int ret;
 608         char buf[16];
 609         u32 gpionr = irq_to_gpio(irq);
 610
 611         if (type == IRQ_TYPE_PROBE) {
 612                 /* only probe unenabled GPIO interrupt lines */
 613                 if (test_bit(gpionr, gpio_enabled))
 614                         return 0;
 615                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
 616         }
 617
 618         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
 619                     IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
 620
 621                 snprintf(buf, 16, "gpio-irq%d", irq);
 622                 ret = bfin_gpio_irq_request(gpionr, buf);
 623                 if (ret)
 624                         return ret;
 625
 626                 if (__test_and_set_bit(gpionr, gpio_enabled))
 627                         bfin_gpio_irq_prepare(gpionr);
 628
 629         } else {
 630                 __clear_bit(gpionr, gpio_enabled);
 631                 return 0;
 632         }
 633
 634         set_gpio_inen(gpionr, 0);
 635         set_gpio_dir(gpionr, 0);
 636
 637         if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 638             == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 639                 set_gpio_both(gpionr, 1);
 640         else
 641                 set_gpio_both(gpionr, 0);
 642
 643         if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
 644                 set_gpio_polar(gpionr, 1);      /* low or falling edge denoted by one */
 645         else
 646                 set_gpio_polar(gpionr, 0);      /* high or rising edge denoted by zero */
 647
 648         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
 649                 set_gpio_edge(gpionr, 1);
 650                 set_gpio_inen(gpionr, 1);
 651                 set_gpio_data(gpionr, 0);
 652
 653         } else {
 654                 set_gpio_edge(gpionr, 0);
 655                 set_gpio_inen(gpionr, 1);
 656         }
 657
 658         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 659                 bfin_set_irq_handler(irq, handle_edge_irq);
 660         else
 661                 bfin_set_irq_handler(irq, handle_level_irq);
 662
 663         return 0;
 664 }
 665
 666 #ifdef CONFIG_PM
 667 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
 668 {
 669         return gpio_pm_wakeup_ctrl(irq_to_gpio(irq), state);
 670 }
 671 #endif
 672
 673 static void bfin_demux_gpio_irq(unsigned int inta_irq,
 674                                 struct irq_desc *desc)
 675 {
 676         unsigned int i, gpio, mask, irq, search = 0;
 677
 678         switch (inta_irq) {
 679 #if defined(CONFIG_BF53x)
 680         case IRQ_PROG_INTA:
 681                 irq = IRQ_PF0;
 682                 search = 1;
 683                 break;
 684 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
 685         case IRQ_MAC_RX:
 686                 irq = IRQ_PH0;
 687                 break;
 688 # endif
 689 #elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
 690         case IRQ_PORTF_INTA:
 691                 irq = IRQ_PF0;
 692                 break;
 693 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
 694         case IRQ_PORTF_INTA:
 695                 irq = IRQ_PF0;
 696                 break;
 697         case IRQ_PORTG_INTA:
 698                 irq = IRQ_PG0;
 699                 break;
 700         case IRQ_PORTH_INTA:
 701                 irq = IRQ_PH0;
 702                 break;
 703 #elif defined(CONFIG_BF561)
 704         case IRQ_PROG0_INTA:
 705                 irq = IRQ_PF0;
 706                 break;
 707         case IRQ_PROG1_INTA:
 708                 irq = IRQ_PF16;
 709                 break;
 710         case IRQ_PROG2_INTA:
 711                 irq = IRQ_PF32;
 712                 break;
 713 #endif
 714         default:
 715                 BUG();
 716                 return;
 717         }
 718
 719         if (search) {
 720                 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
 721                         irq += i;
 722
 723                         mask = get_gpiop_data(i) & get_gpiop_maska(i);
 724
 725                         while (mask) {
 726                                 if (mask & 1)
 727                                         bfin_handle_irq(irq);
 728                                 irq++;
 729                                 mask >>= 1;
 730                         }
 731                 }
 732         } else {
 733                         gpio = irq_to_gpio(irq);
 734                         mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
 735
 736                         do {
 737                                 if (mask & 1)
 738                                         bfin_handle_irq(irq);
 739                                 irq++;
 740                                 mask >>= 1;
 741                         } while (mask);
 742         }
 743
 744 }
 745
 746 #else                           /* CONFIG_BF54x */
 747
 748 #define NR_PINT_SYS_IRQS        4
 749 #define NR_PINT_BITS            32
 750 #define NR_PINTS                160
 751 #define IRQ_NOT_AVAIL           0xFF
 752
 753 #define PINT_2_BANK(x)          ((x) >> 5)
 754 #define PINT_2_BIT(x)           ((x) & 0x1F)
 755 #define PINT_BIT(x)             (1 << (PINT_2_BIT(x)))
 756
 757 static unsigned char irq2pint_lut[NR_PINTS];
 758 static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
 759
 760 struct pin_int_t {
 761         unsigned int mask_set;
 762         unsigned int mask_clear;
 763         unsigned int request;
 764         unsigned int assign;
 765         unsigned int edge_set;
 766         unsigned int edge_clear;
 767         unsigned int invert_set;
 768         unsigned int invert_clear;
 769         unsigned int pinstate;
 770         unsigned int latch;
 771 };
 772
 773 static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
 774         (struct pin_int_t *)PINT0_MASK_SET,
 775         (struct pin_int_t *)PINT1_MASK_SET,
 776         (struct pin_int_t *)PINT2_MASK_SET,
 777         (struct pin_int_t *)PINT3_MASK_SET,
 778 };
 779
 780 inline unsigned int get_irq_base(u32 bank, u8 bmap)
 781 {
 782         unsigned int irq_base;
 783
 784         if (bank < 2) {         /*PA-PB */
 785                 irq_base = IRQ_PA0 + bmap * 16;
 786         } else {                /*PC-PJ */
 787                 irq_base = IRQ_PC0 + bmap * 16;
 788         }
 789
 790         return irq_base;
 791 }
 792
 793         /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
 794 void init_pint_lut(void)
 795 {
 796         u16 bank, bit, irq_base, bit_pos;
 797         u32 pint_assign;
 798         u8 bmap;
 799
 800         memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
 801
 802         for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
 803
 804                 pint_assign = pint[bank]->assign;
 805
 806                 for (bit = 0; bit < NR_PINT_BITS; bit++) {
 807
 808                         bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
 809
 810                         irq_base = get_irq_base(bank, bmap);
 811
 812                         irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
 813                         bit_pos = bit + bank * NR_PINT_BITS;
 814
 815                         pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
 816                         irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
 817                 }
 818         }
 819 }
 820
 821 static void bfin_gpio_ack_irq(unsigned int irq)
 822 {
 823         struct irq_desc *desc = irq_desc + irq;
 824         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 825         u32 pintbit = PINT_BIT(pint_val);
 826         u32 bank = PINT_2_BANK(pint_val);
 827
 828         if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
 829                 if (pint[bank]->invert_set & pintbit)
 830                         pint[bank]->invert_clear = pintbit;
 831                 else
 832                         pint[bank]->invert_set = pintbit;
 833         }
 834         pint[bank]->request = pintbit;
 835
 836 }
 837
 838 static void bfin_gpio_mask_ack_irq(unsigned int irq)
 839 {
 840         struct irq_desc *desc = irq_desc + irq;
 841         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 842         u32 pintbit = PINT_BIT(pint_val);
 843         u32 bank = PINT_2_BANK(pint_val);
 844
 845         if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
 846                 if (pint[bank]->invert_set & pintbit)
 847                         pint[bank]->invert_clear = pintbit;
 848                 else
 849                         pint[bank]->invert_set = pintbit;
 850         }
 851
 852         pint[bank]->request = pintbit;
 853         pint[bank]->mask_clear = pintbit;
 854 }
 855
 856 static void bfin_gpio_mask_irq(unsigned int irq)
 857 {
 858         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 859
 860         pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
 861 }
 862
 863 static void bfin_gpio_unmask_irq(unsigned int irq)
 864 {
 865         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 866         u32 pintbit = PINT_BIT(pint_val);
 867         u32 bank = PINT_2_BANK(pint_val);
 868
 869         pint[bank]->request = pintbit;
 870         pint[bank]->mask_set = pintbit;
 871 }
 872
 873 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
 874 {
 875         u32 gpionr = irq_to_gpio(irq);
 876         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 877
 878         if (pint_val == IRQ_NOT_AVAIL) {
 879                 printk(KERN_ERR
 880                 "GPIO IRQ %d :Not in PINT Assign table "
 881                 "Reconfigure Interrupt to Port Assignemt\n", irq);
 882                 return -ENODEV;
 883         }
 884
 885         if (__test_and_set_bit(gpionr, gpio_enabled))
 886                 bfin_gpio_irq_prepare(gpionr);
 887
 888         bfin_gpio_unmask_irq(irq);
 889
 890         return 0;
 891 }
 892
 893 static void bfin_gpio_irq_shutdown(unsigned int irq)
 894 {
 895         u32 gpionr = irq_to_gpio(irq);
 896
 897         bfin_gpio_mask_irq(irq);
 898         __clear_bit(gpionr, gpio_enabled);
 899         bfin_gpio_irq_free(gpionr);
 900 }
 901
 902 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
 903 {
 904         int ret;
 905         char buf[16];
 906         u32 gpionr = irq_to_gpio(irq);
 907         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 908         u32 pintbit = PINT_BIT(pint_val);
 909         u32 bank = PINT_2_BANK(pint_val);
 910
 911         if (pint_val == IRQ_NOT_AVAIL)
 912                 return -ENODEV;
 913
 914         if (type == IRQ_TYPE_PROBE) {
 915                 /* only probe unenabled GPIO interrupt lines */
 916                 if (test_bit(gpionr, gpio_enabled))
 917                         return 0;
 918                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
 919         }
 920
 921         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
 922                     IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
 923
 924                 snprintf(buf, 16, "gpio-irq%d", irq);
 925                 ret = bfin_gpio_irq_request(gpionr, buf);
 926                 if (ret)
 927                         return ret;
 928
 929                 if (__test_and_set_bit(gpionr, gpio_enabled))
 930                         bfin_gpio_irq_prepare(gpionr);
 931
 932         } else {
 933                 __clear_bit(gpionr, gpio_enabled);
 934                 return 0;
 935         }
 936
 937         if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
 938                 pint[bank]->invert_set = pintbit;       /* low or falling edge denoted by one */
 939         else
 940                 pint[bank]->invert_clear = pintbit;     /* high or rising edge denoted by zero */
 941
 942         if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 943             == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
 944                 if (gpio_get_value(gpionr))
 945                         pint[bank]->invert_set = pintbit;
 946                 else
 947                         pint[bank]->invert_clear = pintbit;
 948         }
 949
 950         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
 951                 pint[bank]->edge_set = pintbit;
 952                 bfin_set_irq_handler(irq, handle_edge_irq);
 953         } else {
 954                 pint[bank]->edge_clear = pintbit;
 955                 bfin_set_irq_handler(irq, handle_level_irq);
 956         }
 957
 958         return 0;
 959 }
 960
 961 #ifdef CONFIG_PM
 962 u32 pint_saved_masks[NR_PINT_SYS_IRQS];
 963 u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
 964
 965 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
 966 {
 967         u32 pint_irq;
 968         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 969         u32 bank = PINT_2_BANK(pint_val);
 970         u32 pintbit = PINT_BIT(pint_val);
 971
 972         switch (bank) {
 973         case 0:
 974                 pint_irq = IRQ_PINT0;
 975                 break;
 976         case 2:
 977                 pint_irq = IRQ_PINT2;
 978                 break;
 979         case 3:
 980                 pint_irq = IRQ_PINT3;
 981                 break;
 982         case 1:
 983                 pint_irq = IRQ_PINT1;
 984                 break;
 985         default:
 986                 return -EINVAL;
 987         }
 988
 989         bfin_internal_set_wake(pint_irq, state);
 990
 991         if (state)
 992                 pint_wakeup_masks[bank] |= pintbit;
 993         else
 994                 pint_wakeup_masks[bank] &= ~pintbit;
 995
 996         return 0;
 997 }
 998
 999 u32 bfin_pm_setup(void)
1000 {
1001         u32 val, i;
1002
1003         for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
1004                 val = pint[i]->mask_clear;
1005                 pint_saved_masks[i] = val;
1006                 if (val ^ pint_wakeup_masks[i]) {
1007                         pint[i]->mask_clear = val;
1008                         pint[i]->mask_set = pint_wakeup_masks[i];
1009                 }
1010         }
1011
1012         return 0;
1013 }
1014
1015 void bfin_pm_restore(void)
1016 {
1017         u32 i, val;
1018
1019         for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
1020                 val = pint_saved_masks[i];
1021                 if (val ^ pint_wakeup_masks[i]) {
1022                         pint[i]->mask_clear = pint[i]->mask_clear;
1023                         pint[i]->mask_set = val;
1024                 }
1025         }
1026 }
1027 #endif
1028
1029 static void bfin_demux_gpio_irq(unsigned int inta_irq,
1030                                 struct irq_desc *desc)
1031 {
1032         u32 bank, pint_val;
1033         u32 request, irq;
1034
1035         switch (inta_irq) {
1036         case IRQ_PINT0:
1037                 bank = 0;
1038                 break;
1039         case IRQ_PINT2:
1040                 bank = 2;
1041                 break;
1042         case IRQ_PINT3:
1043                 bank = 3;
1044                 break;
1045         case IRQ_PINT1:
1046                 bank = 1;
1047                 break;
1048         default:
1049                 return;
1050         }
1051
1052         pint_val = bank * NR_PINT_BITS;
1053
1054         request = pint[bank]->request;
1055
1056         while (request) {
1057                 if (request & 1) {
1058                         irq = pint2irq_lut[pint_val] + SYS_IRQS;
1059                         bfin_handle_irq(irq);
1060                 }
1061                 pint_val++;
1062                 request >>= 1;
1063         }
1064
1065 }
1066 #endif
1067
1068 static struct irq_chip bfin_gpio_irqchip = {
1069         .name = "GPIO",
1070         .ack = bfin_gpio_ack_irq,
1071         .mask = bfin_gpio_mask_irq,
1072         .mask_ack = bfin_gpio_mask_ack_irq,
1073         .unmask = bfin_gpio_unmask_irq,
1074         .disable = bfin_gpio_mask_irq,
1075         .enable = bfin_gpio_unmask_irq,
1076         .set_type = bfin_gpio_irq_type,
1077         .startup = bfin_gpio_irq_startup,
1078         .shutdown = bfin_gpio_irq_shutdown,
1079 #ifdef CONFIG_PM
1080         .set_wake = bfin_gpio_set_wake,
1081 #endif
1082 };
1083
1084 void __cpuinit init_exception_vectors(void)
1085 {
1086         /* cannot program in software:
1087          * evt0 - emulation (jtag)
1088          * evt1 - reset
1089          */
1090         bfin_write_EVT2(evt_nmi);
1091         bfin_write_EVT3(trap);
1092         bfin_write_EVT5(evt_ivhw);
1093         bfin_write_EVT6(evt_timer);
1094         bfin_write_EVT7(evt_evt7);
1095         bfin_write_EVT8(evt_evt8);
1096         bfin_write_EVT9(evt_evt9);
1097         bfin_write_EVT10(evt_evt10);
1098         bfin_write_EVT11(evt_evt11);
1099         bfin_write_EVT12(evt_evt12);
1100         bfin_write_EVT13(evt_evt13);
1101         bfin_write_EVT14(evt_evt14);
1102         bfin_write_EVT15(evt_system_call);
1103         CSYNC();
1104 }
1105
1106 /*
1107  * This function should be called during kernel startup to initialize
1108  * the BFin IRQ handling routines.
1109  */
1110
1111 int __init init_arch_irq(void)
1112 {
1113         int irq;
1114         unsigned long ilat = 0;
1115         /*  Disable all the peripheral intrs  - page 4-29 HW Ref manual */
1116 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
1117         || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
1118         bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
1119         bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
1120 # ifdef CONFIG_BF54x
1121         bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
1122 # endif
1123 # ifdef CONFIG_SMP
1124         bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
1125         bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
1126 # endif
1127 #else
1128         bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
1129 #endif
1130
1131         local_irq_disable();
1132
1133 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
1134         /* Clear EMAC Interrupt Status bits so we can demux it later */
1135         bfin_write_EMAC_SYSTAT(-1);
1136 #endif
1137
1138 #ifdef CONFIG_BF54x
1139 # ifdef CONFIG_PINTx_REASSIGN
1140         pint[0]->assign = CONFIG_PINT0_ASSIGN;
1141         pint[1]->assign = CONFIG_PINT1_ASSIGN;
1142         pint[2]->assign = CONFIG_PINT2_ASSIGN;
1143         pint[3]->assign = CONFIG_PINT3_ASSIGN;
1144 # endif
1145         /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
1146         init_pint_lut();
1147 #endif
1148
1149         for (irq = 0; irq <= SYS_IRQS; irq++) {
1150                 if (irq <= IRQ_CORETMR)
1151                         set_irq_chip(irq, &bfin_core_irqchip);
1152                 else
1153                         set_irq_chip(irq, &bfin_internal_irqchip);
1154
1155                 switch (irq) {
1156 #if defined(CONFIG_BF53x)
1157                 case IRQ_PROG_INTA:
1158 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
1159                 case IRQ_MAC_RX:
1160 # endif
1161 #elif defined(CONFIG_BF54x)
1162                 case IRQ_PINT0:
1163                 case IRQ_PINT1:
1164                 case IRQ_PINT2:
1165                 case IRQ_PINT3:
1166 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
1167                 case IRQ_PORTF_INTA:
1168                 case IRQ_PORTG_INTA:
1169                 case IRQ_PORTH_INTA:
1170 #elif defined(CONFIG_BF561)
1171                 case IRQ_PROG0_INTA:
1172                 case IRQ_PROG1_INTA:
1173                 case IRQ_PROG2_INTA:
1174 #elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
1175                 case IRQ_PORTF_INTA:
1176 #endif
1177                         set_irq_chained_handler(irq,
1178                                                 bfin_demux_gpio_irq);
1179                         break;
1180 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1181                 case IRQ_GENERIC_ERROR:
1182                         set_irq_chained_handler(irq, bfin_demux_error_irq);
1183                         break;
1184 #endif
1185 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1186                 case IRQ_MAC_ERROR:
1187                         set_irq_chained_handler(irq, bfin_demux_mac_status_irq);
1188                         break;
1189 #endif
1190 #ifdef CONFIG_SMP
1191                 case IRQ_SUPPLE_0:
1192                 case IRQ_SUPPLE_1:
1193                         set_irq_handler(irq, handle_percpu_irq);
1194                         break;
1195 #endif
1196
1197 #ifdef CONFIG_TICKSOURCE_CORETMR
1198                 case IRQ_CORETMR:
1199 # ifdef CONFIG_SMP
1200                         set_irq_handler(irq, handle_percpu_irq);
1201                         break;
1202 # else
1203                         set_irq_handler(irq, handle_simple_irq);
1204                         break;
1205 # endif
1206 #endif
1207
1208 #ifdef CONFIG_TICKSOURCE_GPTMR0
1209                 case IRQ_TIMER0:
1210                         set_irq_handler(irq, handle_simple_irq);
1211                         break;
1212 #endif
1213
1214 #ifdef CONFIG_IPIPE
1215                 default:
1216                         set_irq_handler(irq, handle_level_irq);
1217                         break;
1218 #else /* !CONFIG_IPIPE */
1219                 default:
1220                         set_irq_handler(irq, handle_simple_irq);
1221                         break;
1222 #endif /* !CONFIG_IPIPE */
1223                 }
1224         }
1225
1226 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1227         for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
1228                 set_irq_chip_and_handler(irq, &bfin_generic_error_irqchip,
1229                                          handle_level_irq);
1230 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1231         set_irq_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq);
1232 #endif
1233 #endif
1234
1235 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1236         for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++)
1237                 set_irq_chip_and_handler(irq, &bfin_mac_status_irqchip,
1238                                          handle_level_irq);
1239 #endif
1240         /* if configured as edge, then will be changed to do_edge_IRQ */
1241         for (irq = GPIO_IRQ_BASE;
1242                 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
1243                 set_irq_chip_and_handler(irq, &bfin_gpio_irqchip,
1244                                          handle_level_irq);
1245
1246         bfin_write_IMASK(0);
1247         CSYNC();
1248         ilat = bfin_read_ILAT();
1249         CSYNC();
1250         bfin_write_ILAT(ilat);
1251         CSYNC();
1252
1253         printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1254         /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
1255          * local_irq_enable()
1256          */
1257         program_IAR();
1258         /* Therefore it's better to setup IARs before interrupts enabled */
1259         search_IAR();
1260
1261         /* Enable interrupts IVG7-15 */
1262         bfin_irq_flags |= IMASK_IVG15 |
1263             IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1264             IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1265
1266         /* This implicitly covers ANOMALY_05000171
1267          * Boot-ROM code modifies SICA_IWRx wakeup registers
1268          */
1269 #ifdef SIC_IWR0
1270         bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
1271 # ifdef SIC_IWR1
1272         /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
1273          * will screw up the bootrom as it relies on MDMA0/1 waking it
1274          * up from IDLE instructions.  See this report for more info:
1275          * http://blackfin.uclinux.org/gf/tracker/4323
1276          */
1277         if (ANOMALY_05000435)
1278                 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1279         else
1280                 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
1281 # endif
1282 # ifdef SIC_IWR2
1283         bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
1284 # endif
1285 #else
1286         bfin_write_SIC_IWR(IWR_DISABLE_ALL);
1287 #endif
1288
1289         return 0;
1290 }
1291
1292 #ifdef CONFIG_DO_IRQ_L1
1293 __attribute__((l1_text))
1294 #endif
1295 void do_irq(int vec, struct pt_regs *fp)
1296 {
1297         if (vec == EVT_IVTMR_P) {
1298                 vec = IRQ_CORETMR;
1299         } else {
1300                 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1301                 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1302 #if defined(SIC_ISR0)
1303                 unsigned long sic_status[3];
1304
1305                 if (smp_processor_id()) {
1306 # ifdef SICB_ISR0
1307                         /* This will be optimized out in UP mode. */
1308                         sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
1309                         sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
1310 # endif
1311                 } else {
1312                         sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1313                         sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1314                 }
1315 # ifdef SIC_ISR2
1316                 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1317 # endif
1318                 for (;; ivg++) {
1319                         if (ivg >= ivg_stop) {
1320                                 atomic_inc(&num_spurious);
1321                                 return;
1322                         }
1323                         if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1324                                 break;
1325                 }
1326 #else
1327                 unsigned long sic_status;
1328
1329                 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1330
1331                 for (;; ivg++) {
1332                         if (ivg >= ivg_stop) {
1333                                 atomic_inc(&num_spurious);
1334                                 return;
1335                         } else if (sic_status & ivg->isrflag)
1336                                 break;
1337                 }
1338 #endif
1339                 vec = ivg->irqno;
1340         }
1341         asm_do_IRQ(vec, fp);
1342 }
1343
1344 #ifdef CONFIG_IPIPE
1345
1346 int __ipipe_get_irq_priority(unsigned irq)
1347 {
1348         int ient, prio;
1349
1350         if (irq <= IRQ_CORETMR)
1351                 return irq;
1352
1353         for (ient = 0; ient < NR_PERI_INTS; ient++) {
1354                 struct ivgx *ivg = ivg_table + ient;
1355                 if (ivg->irqno == irq) {
1356                         for (prio = 0; prio <= IVG13-IVG7; prio++) {
1357                                 if (ivg7_13[prio].ifirst <= ivg &&
1358                                     ivg7_13[prio].istop > ivg)
1359                                         return IVG7 + prio;
1360                         }
1361                 }
1362         }
1363
1364         return IVG15;
1365 }
1366
1367 /* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */
1368 #ifdef CONFIG_DO_IRQ_L1
1369 __attribute__((l1_text))
1370 #endif
1371 asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1372 {
1373         struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
1374         struct ipipe_domain *this_domain = __ipipe_current_domain;
1375         struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop;
1376         struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst;
1377         int irq, s;
1378
1379         if (likely(vec == EVT_IVTMR_P))
1380                 irq = IRQ_CORETMR;
1381         else {
1382 #if defined(SIC_ISR0)
1383                 unsigned long sic_status[3];
1384
1385                 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1386                 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1387 # ifdef SIC_ISR2
1388                 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1389 # endif
1390                 for (;; ivg++) {
1391                         if (ivg >= ivg_stop) {
1392                                 atomic_inc(&num_spurious);
1393                                 return 0;
1394                         }
1395                         if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1396                                 break;
1397                 }
1398 #else
1399                 unsigned long sic_status;
1400
1401                 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1402
1403                 for (;; ivg++) {
1404                         if (ivg >= ivg_stop) {
1405                                 atomic_inc(&num_spurious);
1406                                 return 0;
1407                         } else if (sic_status & ivg->isrflag)
1408                                 break;
1409                 }
1410 #endif
1411                 irq = ivg->irqno;
1412         }
1413
1414         if (irq == IRQ_SYSTMR) {
1415 #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0)
1416                 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
1417 #endif
1418                 /* This is basically what we need from the register frame. */
1419                 __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend;
1420                 __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc;
1421                 if (this_domain != ipipe_root_domain)
1422                         __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10;
1423                 else
1424                         __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10;
1425         }
1426
1427         if (this_domain == ipipe_root_domain) {
1428                 s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1429                 barrier();
1430         }
1431
1432         ipipe_trace_irq_entry(irq);
1433         __ipipe_handle_irq(irq, regs);
1434         ipipe_trace_irq_exit(irq);
1435
1436         if (this_domain == ipipe_root_domain) {
1437                 set_thread_flag(TIF_IRQ_SYNC);
1438                 if (!s) {
1439                         __clear_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1440                         return !test_bit(IPIPE_STALL_FLAG, &p->status);
1441                 }
1442         }
1443
1444         return 0;
1445 }
1446
1447 #endif /* CONFIG_IPIPE */