arch/blackfin/mach-common/cpufreq.c

   1 /*
   2  * Blackfin core clock scaling
   3  *
   4  * Copyright 2008-2011 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/types.h>
  12 #include <linux/init.h>
  13 #include <linux/cpufreq.h>
  14 #include <linux/fs.h>
  15 #include <linux/delay.h>
  16 #include <asm/blackfin.h>
  17 #include <asm/time.h>
  18 #include <asm/dpmc.h>
  19
  20 /* this is the table of CCLK frequencies, in Hz */
  21 /* .index is the entry in the auxiliary dpm_state_table[] */
  22 static struct cpufreq_frequency_table bfin_freq_table[] = {
  23         {
  24                 .frequency = CPUFREQ_TABLE_END,
  25                 .index = 0,
  26         },
  27         {
  28                 .frequency = CPUFREQ_TABLE_END,
  29                 .index = 1,
  30         },
  31         {
  32                 .frequency = CPUFREQ_TABLE_END,
  33                 .index = 2,
  34         },
  35         {
  36                 .frequency = CPUFREQ_TABLE_END,
  37                 .index = 0,
  38         },
  39 };
  40
  41 static struct bfin_dpm_state {
  42         unsigned int csel; /* system clock divider */
  43         unsigned int tscale; /* change the divider on the core timer interrupt */
  44 } dpm_state_table[3];
  45
  46 #if defined(CONFIG_CYCLES_CLOCKSOURCE)
  47 /*
  48  * normalized to maximum frequency offset for CYCLES,
  49  * used in time-ts cycles clock source, but could be used
  50  * somewhere also.
  51  */
  52 unsigned long long __bfin_cycles_off;
  53 unsigned int __bfin_cycles_mod;
  54 #endif
  55
  56 /**************************************************************************/
  57 static void __init bfin_init_tables(unsigned long cclk, unsigned long sclk)
  58 {
  59
  60         unsigned long csel, min_cclk;
  61         int index;
  62
  63         /* Anomaly 273 seems to still exist on non-BF54x w/dcache turned on */
  64 #if ANOMALY_05000273 || ANOMALY_05000274 || \
  65         (!defined(CONFIG_BF54x) && defined(CONFIG_BFIN_EXTMEM_DCACHEABLE))
  66         min_cclk = sclk * 2;
  67 #else
  68         min_cclk = sclk;
  69 #endif
  70         csel = ((bfin_read_PLL_DIV() & CSEL) >> 4);
  71
  72         for (index = 0;  (cclk >> index) >= min_cclk && csel <= 3; index++, csel++) {
  73                 bfin_freq_table[index].frequency = cclk >> index;
  74                 dpm_state_table[index].csel = csel << 4; /* Shift now into PLL_DIV bitpos */
  75                 dpm_state_table[index].tscale =  (TIME_SCALE / (1 << csel)) - 1;
  76
  77                 pr_debug("cpufreq: freq:%d csel:0x%x tscale:%d\n",
  78                                                  bfin_freq_table[index].frequency,
  79                                                  dpm_state_table[index].csel,
  80                                                  dpm_state_table[index].tscale);
  81         }
  82         return;
  83 }
  84
  85 static void bfin_adjust_core_timer(void *info)
  86 {
  87         unsigned int tscale;
  88         unsigned int index = *(unsigned int *)info;
  89
  90         /* we have to adjust the core timer, because it is using cclk */
  91         tscale = dpm_state_table[index].tscale;
  92         bfin_write_TSCALE(tscale);
  93         return;
  94 }
  95
  96 static unsigned int bfin_getfreq_khz(unsigned int cpu)
  97 {
  98         /* Both CoreA/B have the same core clock */
  99         return get_cclk() / 1000;
 100 }
 101
 102 static int bfin_target(struct cpufreq_policy *poli,
 103                         unsigned int target_freq, unsigned int relation)
 104 {
 105         unsigned int index, plldiv, cpu;
 106         unsigned long flags, cclk_hz;
 107         struct cpufreq_freqs freqs;
 108         static unsigned long lpj_ref;
 109         static unsigned int  lpj_ref_freq;
 110
 111 #if defined(CONFIG_CYCLES_CLOCKSOURCE)
 112         cycles_t cycles;
 113 #endif
 114
 115         for_each_online_cpu(cpu) {
 116                 struct cpufreq_policy *policy = cpufreq_cpu_get(cpu);
 117
 118                 if (!policy)
 119                         continue;
 120
 121                 if (cpufreq_frequency_table_target(policy, bfin_freq_table,
 122                                  target_freq, relation, &index))
 123                         return -EINVAL;
 124
 125                 cclk_hz = bfin_freq_table[index].frequency;
 126
 127                 freqs.old = bfin_getfreq_khz(0);
 128                 freqs.new = cclk_hz;
 129                 freqs.cpu = cpu;
 130
 131                 pr_debug("cpufreq: changing cclk to %lu; target = %u, oldfreq = %u\n",
 132                          cclk_hz, target_freq, freqs.old);
 133
 134                 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
 135                 if (cpu == CPUFREQ_CPU) {
 136                         flags = hard_local_irq_save();
 137                         plldiv = (bfin_read_PLL_DIV() & SSEL) |
 138                                                 dpm_state_table[index].csel;
 139                         bfin_write_PLL_DIV(plldiv);
 140                         on_each_cpu(bfin_adjust_core_timer, &index, 1);
 141 #if defined(CONFIG_CYCLES_CLOCKSOURCE)
 142                         cycles = get_cycles();
 143                         SSYNC();
 144                         cycles += 10; /* ~10 cycles we lose after get_cycles() */
 145                         __bfin_cycles_off +=
 146                             (cycles << __bfin_cycles_mod) - (cycles << index);
 147                         __bfin_cycles_mod = index;
 148 #endif
 149                         if (!lpj_ref_freq) {
 150                                 lpj_ref = loops_per_jiffy;
 151                                 lpj_ref_freq = freqs.old;
 152                         }
 153                         if (freqs.new != freqs.old) {
 154                                 loops_per_jiffy = cpufreq_scale(lpj_ref,
 155                                                 lpj_ref_freq, freqs.new);
 156                         }
 157                         hard_local_irq_restore(flags);
 158                 }
 159                 /* TODO: just test case for cycles clock source, remove later */
 160                 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 161         }
 162
 163         pr_debug("cpufreq: done\n");
 164         return 0;
 165 }
 166
 167 static int bfin_verify_speed(struct cpufreq_policy *policy)
 168 {
 169         return cpufreq_frequency_table_verify(policy, bfin_freq_table);
 170 }
 171
 172 static int __init __bfin_cpu_init(struct cpufreq_policy *policy)
 173 {
 174
 175         unsigned long cclk, sclk;
 176
 177         cclk = get_cclk() / 1000;
 178         sclk = get_sclk() / 1000;
 179
 180         if (policy->cpu == CPUFREQ_CPU)
 181                 bfin_init_tables(cclk, sclk);
 182
 183         policy->cpuinfo.transition_latency = 50000; /* 50us assumed */
 184
 185         policy->cur = cclk;
 186         cpufreq_frequency_table_get_attr(bfin_freq_table, policy->cpu);
 187         return cpufreq_frequency_table_cpuinfo(policy, bfin_freq_table);
 188 }
 189
 190 static struct freq_attr *bfin_freq_attr[] = {
 191         &cpufreq_freq_attr_scaling_available_freqs,
 192         NULL,
 193 };
 194
 195 static struct cpufreq_driver bfin_driver = {
 196         .verify = bfin_verify_speed,
 197         .target = bfin_target,
 198         .get = bfin_getfreq_khz,
 199         .init = __bfin_cpu_init,
 200         .name = "bfin cpufreq",
 201         .owner = THIS_MODULE,
 202         .attr = bfin_freq_attr,
 203 };
 204
 205 static int __init bfin_cpu_init(void)
 206 {
 207         return cpufreq_register_driver(&bfin_driver);
 208 }
 209
 210 static void __exit bfin_cpu_exit(void)
 211 {
 212         cpufreq_unregister_driver(&bfin_driver);
 213 }
 214
 215 MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
 216 MODULE_DESCRIPTION("cpufreq driver for Blackfin");
 217 MODULE_LICENSE("GPL");
 218
 219 module_init(bfin_cpu_init);
 220 module_exit(bfin_cpu_exit);