arch/blackfin/mach-bf561/include/mach/mem_map.h

   1 /*
   2  * BF561 memory map
   3  *
   4  * Copyright 2004-2009 Analog Devices Inc.
   5  * Licensed under the GPL-2 or later.
   6  */
   7
   8 #ifndef __BFIN_MACH_MEM_MAP_H__
   9 #define __BFIN_MACH_MEM_MAP_H__
  10
  11 #ifndef __BFIN_MEM_MAP_H__
  12 # error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
  13 #endif
  14
  15 /* Async Memory Banks */
  16 #define ASYNC_BANK3_BASE        0x2C000000       /* Async Bank 3 */
  17 #define ASYNC_BANK3_SIZE        0x04000000      /* 64M */
  18 #define ASYNC_BANK2_BASE        0x28000000       /* Async Bank 2 */
  19 #define ASYNC_BANK2_SIZE        0x04000000      /* 64M */
  20 #define ASYNC_BANK1_BASE        0x24000000       /* Async Bank 1 */
  21 #define ASYNC_BANK1_SIZE        0x04000000      /* 64M */
  22 #define ASYNC_BANK0_BASE        0x20000000       /* Async Bank 0 */
  23 #define ASYNC_BANK0_SIZE        0x04000000      /* 64M */
  24
  25 /* Boot ROM Memory */
  26
  27 #define BOOT_ROM_START          0xEF000000
  28 #define BOOT_ROM_LENGTH         0x800
  29
  30 /* Level 1 Memory */
  31
  32 #ifdef CONFIG_BFIN_ICACHE
  33 #define BFIN_ICACHESIZE (16*1024)
  34 #else
  35 #define BFIN_ICACHESIZE (0*1024)
  36 #endif
  37
  38 /* Memory Map for ADSP-BF561 processors */
  39
  40 #ifdef CONFIG_BF561
  41 #define COREA_L1_CODE_START       0xFFA00000
  42 #define COREA_L1_DATA_A_START     0xFF800000
  43 #define COREA_L1_DATA_B_START     0xFF900000
  44 #define COREB_L1_CODE_START       0xFF600000
  45 #define COREB_L1_DATA_A_START     0xFF400000
  46 #define COREB_L1_DATA_B_START     0xFF500000
  47
  48 #define L1_CODE_START       COREA_L1_CODE_START
  49 #define L1_DATA_A_START     COREA_L1_DATA_A_START
  50 #define L1_DATA_B_START     COREA_L1_DATA_B_START
  51
  52 #define L1_CODE_LENGTH      0x4000
  53
  54 #ifdef CONFIG_BFIN_DCACHE
  55
  56 #ifdef CONFIG_BFIN_DCACHE_BANKA
  57 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
  58 #define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
  59 #define L1_DATA_B_LENGTH      0x8000
  60 #define BFIN_DCACHESIZE (16*1024)
  61 #define BFIN_DSUPBANKS  1
  62 #else
  63 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
  64 #define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
  65 #define L1_DATA_B_LENGTH      (0x8000 - 0x4000)
  66 #define BFIN_DCACHESIZE (32*1024)
  67 #define BFIN_DSUPBANKS  2
  68 #endif
  69
  70 #else
  71 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
  72 #define L1_DATA_A_LENGTH      0x8000
  73 #define L1_DATA_B_LENGTH      0x8000
  74 #define BFIN_DCACHESIZE (0*1024)
  75 #define BFIN_DSUPBANKS  0
  76 #endif /*CONFIG_BFIN_DCACHE*/
  77 #endif
  78
  79 /* Level 2 Memory */
  80 #define L2_START                0xFEB00000
  81 #define L2_LENGTH               0x20000
  82
  83 /* Scratch Pad Memory */
  84
  85 #define COREA_L1_SCRATCH_START  0xFFB00000
  86 #define COREB_L1_SCRATCH_START  0xFF700000
  87
  88 #ifdef __ASSEMBLY__
  89
  90 /*
  91  * The following macros both return the address of the PDA for the
  92  * current core.
  93  *
  94  * In its first safe (and hairy) form, the macro neither clobbers any
  95  * register aside of the output Preg, nor uses the stack, since it
  96  * could be called with an invalid stack pointer, or the current stack
  97  * space being uncovered by any CPLB (e.g. early exception handling).
  98  *
  99  * The constraints on the second form are a bit relaxed, and the code
 100  * is allowed to use the specified Dreg for determining the PDA
 101  * address to be returned into Preg.
 102  */
 103 #ifdef CONFIG_SMP
 104 #define GET_PDA_SAFE(preg)              \
 105         preg.l = lo(DSPID);             \
 106         preg.h = hi(DSPID);             \
 107         preg = [preg];                  \
 108         preg = preg << 2;               \
 109         preg = preg << 2;               \
 110         preg = preg << 2;               \
 111         preg = preg << 2;               \
 112         preg = preg << 2;               \
 113         preg = preg << 2;               \
 114         preg = preg << 2;               \
 115         preg = preg << 2;               \
 116         preg = preg << 2;               \
 117         preg = preg << 2;               \
 118         preg = preg << 2;               \
 119         preg = preg << 2;               \
 120         if cc jump 2f;                  \
 121         cc = preg == 0x0;               \
 122         preg.l = _cpu_pda;              \
 123         preg.h = _cpu_pda;              \
 124         if !cc jump 3f;                 \
 125 1:                                      \
 126         /* preg = 0x0; */               \
 127         cc = !cc; /* restore cc to 0 */ \
 128         jump 4f;                        \
 129 2:                                      \
 130         cc = preg == 0x0;               \
 131         preg.l = _cpu_pda;              \
 132         preg.h = _cpu_pda;              \
 133         if cc jump 4f;                  \
 134         /* preg = 0x1000000; */         \
 135         cc = !cc; /* restore cc to 1 */ \
 136 3:                                      \
 137         preg = [preg];                  \
 138 4:
 139
 140 #define GET_PDA(preg, dreg)             \
 141         preg.l = lo(DSPID);             \
 142         preg.h = hi(DSPID);             \
 143         dreg = [preg];                  \
 144         preg.l = _cpu_pda;              \
 145         preg.h = _cpu_pda;              \
 146         cc = bittst(dreg, 0);           \
 147         if !cc jump 1f;                 \
 148         preg = [preg];                  \
 149 1:                                      \
 150
 151 #define GET_CPUID(preg, dreg)           \
 152         preg.l = lo(DSPID);             \
 153         preg.h = hi(DSPID);             \
 154         dreg = [preg];                  \
 155         dreg = ROT dreg BY -1;          \
 156         dreg = CC;
 157
 158 static inline unsigned long get_l1_scratch_start_cpu(int cpu)
 159 {
 160         return cpu ? COREB_L1_SCRATCH_START : COREA_L1_SCRATCH_START;
 161 }
 162 static inline unsigned long get_l1_code_start_cpu(int cpu)
 163 {
 164         return cpu ? COREB_L1_CODE_START : COREA_L1_CODE_START;
 165 }
 166 static inline unsigned long get_l1_data_a_start_cpu(int cpu)
 167 {
 168         return cpu ? COREB_L1_DATA_A_START : COREA_L1_DATA_A_START;
 169 }
 170 static inline unsigned long get_l1_data_b_start_cpu(int cpu)
 171 {
 172         return cpu ? COREB_L1_DATA_B_START : COREA_L1_DATA_B_START;
 173 }
 174
 175 static inline unsigned long get_l1_scratch_start(void)
 176 {
 177         return get_l1_scratch_start_cpu(blackfin_core_id());
 178 }
 179 static inline unsigned long get_l1_code_start(void)
 180 {
 181         return get_l1_code_start_cpu(blackfin_core_id());
 182 }
 183 static inline unsigned long get_l1_data_a_start(void)
 184 {
 185         return get_l1_data_a_start_cpu(blackfin_core_id());
 186 }
 187 static inline unsigned long get_l1_data_b_start(void)
 188 {
 189         return get_l1_data_b_start_cpu(blackfin_core_id());
 190 }
 191
 192 #endif /* CONFIG_SMP */
 193
 194 #endif /* __ASSEMBLY__ */
 195
 196 #endif