arch/blackfin/mach-bf537/boards/dnp5370.c

   1 /*
   2  * This is the configuration for SSV Dil/NetPC DNP/5370 board.
   3  *
   4  * DIL module:         http://www.dilnetpc.com/dnp0086.htm
   5  * SK28 (starter kit): http://www.dilnetpc.com/dnp0088.htm
   6  *
   7  * Copyright 2010 3ality Digital Systems
   8  * Copyright 2005 National ICT Australia (NICTA)
   9  * Copyright 2004-2006 Analog Devices Inc.
  10  *
  11  * Licensed under the GPL-2 or later.
  12  */
  13
  14 #include <linux/device.h>
  15 #include <linux/kernel.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/io.h>
  18 #include <linux/mtd/mtd.h>
  19 #include <linux/mtd/nand.h>
  20 #include <linux/mtd/partitions.h>
  21 #include <linux/mtd/plat-ram.h>
  22 #include <linux/mtd/physmap.h>
  23 #include <linux/spi/spi.h>
  24 #include <linux/spi/flash.h>
  25 #include <linux/irq.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/i2c.h>
  28 #include <linux/spi/mmc_spi.h>
  29 #include <linux/phy.h>
  30 #include <asm/dma.h>
  31 #include <asm/bfin5xx_spi.h>
  32 #include <asm/reboot.h>
  33 #include <asm/portmux.h>
  34 #include <asm/dpmc.h>
  35
  36 /*
  37  * Name the Board for the /proc/cpuinfo
  38  */
  39 const char bfin_board_name[] = "DNP/5370";
  40 #define FLASH_MAC               0x202f0000
  41 #define CONFIG_MTD_PHYSMAP_LEN  0x300000
  42
  43 #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  44 static struct platform_device rtc_device = {
  45         .name = "rtc-bfin",
  46         .id   = -1,
  47 };
  48 #endif
  49
  50 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  51 #include <linux/bfin_mac.h>
  52 static const unsigned short bfin_mac_peripherals[] = P_RMII0;
  53
  54 static struct bfin_phydev_platform_data bfin_phydev_data[] = {
  55         {
  56                 .addr = 1,
  57                 .irq = PHY_POLL, /* IRQ_MAC_PHYINT */
  58         },
  59 };
  60
  61 static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
  62         .phydev_number   = 1,
  63         .phydev_data     = bfin_phydev_data,
  64         .phy_mode        = PHY_INTERFACE_MODE_RMII,
  65         .mac_peripherals = bfin_mac_peripherals,
  66 };
  67
  68 static struct platform_device bfin_mii_bus = {
  69         .name = "bfin_mii_bus",
  70         .dev = {
  71                 .platform_data = &bfin_mii_bus_data,
  72         }
  73 };
  74
  75 static struct platform_device bfin_mac_device = {
  76         .name = "bfin_mac",
  77         .dev = {
  78                 .platform_data = &bfin_mii_bus,
  79         }
  80 };
  81 #endif
  82
  83 #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
  84 static struct mtd_partition asmb_flash_partitions[] = {
  85         {
  86                 .name       = "bootloader(nor)",
  87                 .size       = 0x30000,
  88                 .offset     = 0,
  89         }, {
  90                 .name       = "linux kernel and rootfs(nor)",
  91                 .size       = 0x300000 - 0x30000 - 0x10000,
  92                 .offset     = MTDPART_OFS_APPEND,
  93         }, {
  94                 .name       = "MAC address(nor)",
  95                 .size       = 0x10000,
  96                 .offset     = MTDPART_OFS_APPEND,
  97                 .mask_flags = MTD_WRITEABLE,
  98         }
  99 };
 100
 101 static struct physmap_flash_data asmb_flash_data = {
 102         .width      = 1,
 103         .parts      = asmb_flash_partitions,
 104         .nr_parts   = ARRAY_SIZE(asmb_flash_partitions),
 105 };
 106
 107 static struct resource asmb_flash_resource = {
 108         .start = 0x20000000,
 109         .end   = 0x202fffff,
 110         .flags = IORESOURCE_MEM,
 111 };
 112
 113 /* 4 MB NOR flash attached to async memory banks 0-2,
 114  * therefore only 3 MB visible.
 115  */
 116 static struct platform_device asmb_flash_device = {
 117         .name     = "physmap-flash",
 118         .id       = 0,
 119         .dev = {
 120                 .platform_data = &asmb_flash_data,
 121         },
 122         .num_resources = 1,
 123         .resource      = &asmb_flash_resource,
 124 };
 125 #endif
 126
 127 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
 128
 129 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
 130
 131 #define MMC_SPI_CARD_DETECT_INT IRQ_PF5
 132
 133 static int bfin_mmc_spi_init(struct device *dev,
 134         irqreturn_t (*detect_int)(int, void *), void *data)
 135 {
 136         return request_irq(MMC_SPI_CARD_DETECT_INT, detect_int,
 137                 IRQF_TRIGGER_FALLING, "mmc-spi-detect", data);
 138 }
 139
 140 static void bfin_mmc_spi_exit(struct device *dev, void *data)
 141 {
 142         free_irq(MMC_SPI_CARD_DETECT_INT, data);
 143 }
 144
 145 static struct bfin5xx_spi_chip mmc_spi_chip_info = {
 146         .enable_dma    = 0,      /* use no dma transfer with this chip*/
 147         .bits_per_word = 8,
 148 };
 149
 150 static struct mmc_spi_platform_data bfin_mmc_spi_pdata = {
 151         .init = bfin_mmc_spi_init,
 152         .exit = bfin_mmc_spi_exit,
 153         .detect_delay = 100, /* msecs */
 154 };
 155 #endif
 156
 157 #if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
 158 /* This mapping is for at45db642 it has 1056 page size,
 159  * partition size and offset should be page aligned
 160  */
 161 static struct mtd_partition bfin_spi_dataflash_partitions[] = {
 162         {
 163                 .name   = "JFFS2 dataflash(nor)",
 164 #ifdef CONFIG_MTD_PAGESIZE_1024
 165                 .offset = 0x40000,
 166                 .size   = 0x7C0000,
 167 #else
 168                 .offset = 0x0,
 169                 .size   = 0x840000,
 170 #endif
 171         }
 172 };
 173
 174 static struct flash_platform_data bfin_spi_dataflash_data = {
 175         .name     = "mtd_dataflash",
 176         .parts    = bfin_spi_dataflash_partitions,
 177         .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
 178         .type     = "mtd_dataflash",
 179 };
 180
 181 static struct bfin5xx_spi_chip spi_dataflash_chip_info = {
 182         .enable_dma    = 0,      /* use no dma transfer with this chip*/
 183         .bits_per_word = 8,
 184 };
 185 #endif
 186
 187 static struct spi_board_info bfin_spi_board_info[] __initdata = {
 188 /* SD/MMC card reader at SPI bus */
 189 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
 190         {
 191                 .modalias        = "mmc_spi",
 192                 .max_speed_hz    = 20000000,
 193                 .bus_num         = 0,
 194                 .chip_select     = 1,
 195                 .platform_data   = &bfin_mmc_spi_pdata,
 196                 .controller_data = &mmc_spi_chip_info,
 197                 .mode            = SPI_MODE_3,
 198         },
 199 #endif
 200
 201 /* 8 Megabyte Atmel NOR flash chip at SPI bus */
 202 #if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
 203         {
 204         .modalias        = "mtd_dataflash",
 205         .max_speed_hz    = 16700000,
 206         .bus_num         = 0,
 207         .chip_select     = 2,
 208         .platform_data   = &bfin_spi_dataflash_data,
 209         .controller_data = &spi_dataflash_chip_info,
 210         .mode            = SPI_MODE_3, /* SPI_CPHA and SPI_CPOL */
 211         },
 212 #endif
 213 };
 214
 215 /* SPI controller data */
 216 /* SPI (0) */
 217 static struct resource bfin_spi0_resource[] = {
 218         [0] = {
 219                 .start = SPI0_REGBASE,
 220                 .end   = SPI0_REGBASE + 0xFF,
 221                 .flags = IORESOURCE_MEM,
 222         },
 223         [1] = {
 224                 .start = CH_SPI,
 225                 .end   = CH_SPI,
 226                 .flags = IORESOURCE_DMA,
 227         },
 228         [2] = {
 229                 .start = IRQ_SPI,
 230                 .end   = IRQ_SPI,
 231                 .flags = IORESOURCE_IRQ,
 232         },
 233 };
 234
 235 static struct bfin5xx_spi_master spi_bfin_master_info = {
 236         .num_chipselect = 8,
 237         .enable_dma     = 1,  /* master has the ability to do dma transfer */
 238         .pin_req        = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
 239 };
 240
 241 static struct platform_device spi_bfin_master_device = {
 242         .name          = "bfin-spi",
 243         .id            = 0, /* Bus number */
 244         .num_resources = ARRAY_SIZE(bfin_spi0_resource),
 245         .resource      = bfin_spi0_resource,
 246         .dev           = {
 247                 .platform_data = &spi_bfin_master_info, /* Passed to driver */
 248         },
 249 };
 250 #endif
 251
 252 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
 253 #ifdef CONFIG_SERIAL_BFIN_UART0
 254 static struct resource bfin_uart0_resources[] = {
 255         {
 256                 .start = UART0_THR,
 257                 .end = UART0_GCTL+2,
 258                 .flags = IORESOURCE_MEM,
 259         },
 260         {
 261                 .start = IRQ_UART0_RX,
 262                 .end = IRQ_UART0_RX+1,
 263                 .flags = IORESOURCE_IRQ,
 264         },
 265         {
 266                 .start = IRQ_UART0_ERROR,
 267                 .end = IRQ_UART0_ERROR,
 268                 .flags = IORESOURCE_IRQ,
 269         },
 270         {
 271                 .start = CH_UART0_TX,
 272                 .end = CH_UART0_TX,
 273                 .flags = IORESOURCE_DMA,
 274         },
 275         {
 276                 .start = CH_UART0_RX,
 277                 .end = CH_UART0_RX,
 278                 .flags = IORESOURCE_DMA,
 279         },
 280 };
 281
 282 static unsigned short bfin_uart0_peripherals[] = {
 283         P_UART0_TX, P_UART0_RX, 0
 284 };
 285
 286 static struct platform_device bfin_uart0_device = {
 287         .name = "bfin-uart",
 288         .id = 0,
 289         .num_resources = ARRAY_SIZE(bfin_uart0_resources),
 290         .resource = bfin_uart0_resources,
 291         .dev = {
 292                 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
 293         },
 294 };
 295 #endif
 296
 297 #ifdef CONFIG_SERIAL_BFIN_UART1
 298 static struct resource bfin_uart1_resources[] = {
 299         {
 300                 .start = UART1_THR,
 301                 .end   = UART1_GCTL+2,
 302                 .flags = IORESOURCE_MEM,
 303         },
 304         {
 305                 .start = IRQ_UART1_RX,
 306                 .end   = IRQ_UART1_RX+1,
 307                 .flags = IORESOURCE_IRQ,
 308         },
 309         {
 310                 .start = IRQ_UART1_ERROR,
 311                 .end   = IRQ_UART1_ERROR,
 312                 .flags = IORESOURCE_IRQ,
 313         },
 314         {
 315                 .start = CH_UART1_TX,
 316                 .end   = CH_UART1_TX,
 317                 .flags = IORESOURCE_DMA,
 318         },
 319         {
 320                 .start = CH_UART1_RX,
 321                 .end   = CH_UART1_RX,
 322                 .flags = IORESOURCE_DMA,
 323         },
 324 };
 325
 326 static unsigned short bfin_uart1_peripherals[] = {
 327         P_UART1_TX, P_UART1_RX, 0
 328 };
 329
 330 static struct platform_device bfin_uart1_device = {
 331         .name          = "bfin-uart",
 332         .id            = 1,
 333         .num_resources = ARRAY_SIZE(bfin_uart1_resources),
 334         .resource      = bfin_uart1_resources,
 335         .dev = {
 336                 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
 337         },
 338 };
 339 #endif
 340 #endif
 341
 342 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
 343 static struct resource bfin_twi0_resource[] = {
 344         [0] = {
 345                 .start = TWI0_REGBASE,
 346                 .end   = TWI0_REGBASE + 0xff,
 347                 .flags = IORESOURCE_MEM,
 348         },
 349         [1] = {
 350                 .start = IRQ_TWI,
 351                 .end   = IRQ_TWI,
 352                 .flags = IORESOURCE_IRQ,
 353         },
 354 };
 355
 356 static struct platform_device i2c_bfin_twi_device = {
 357         .name          = "i2c-bfin-twi",
 358         .id            = 0,
 359         .num_resources = ARRAY_SIZE(bfin_twi0_resource),
 360         .resource      = bfin_twi0_resource,
 361 };
 362 #endif
 363
 364 static struct platform_device *dnp5370_devices[] __initdata = {
 365
 366 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
 367 #ifdef CONFIG_SERIAL_BFIN_UART0
 368         &bfin_uart0_device,
 369 #endif
 370 #ifdef CONFIG_SERIAL_BFIN_UART1
 371         &bfin_uart1_device,
 372 #endif
 373 #endif
 374
 375 #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
 376         &asmb_flash_device,
 377 #endif
 378
 379 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
 380         &bfin_mii_bus,
 381         &bfin_mac_device,
 382 #endif
 383
 384 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
 385         &spi_bfin_master_device,
 386 #endif
 387
 388 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
 389         &i2c_bfin_twi_device,
 390 #endif
 391
 392 #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
 393         &rtc_device,
 394 #endif
 395
 396 };
 397
 398 static int __init dnp5370_init(void)
 399 {
 400         printk(KERN_INFO "DNP/5370: registering device resources\n");
 401         platform_add_devices(dnp5370_devices, ARRAY_SIZE(dnp5370_devices));
 402         printk(KERN_INFO "DNP/5370: registering %zu SPI slave devices\n",
 403                ARRAY_SIZE(bfin_spi_board_info));
 404         spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
 405         printk(KERN_INFO "DNP/5370: MAC %pM\n", (void *)FLASH_MAC);
 406         return 0;
 407 }
 408 arch_initcall(dnp5370_init);
 409
 410 /*
 411  * Currently the MAC address is saved in Flash by U-Boot
 412  */
 413 void bfin_get_ether_addr(char *addr)
 414 {
 415         *(u32 *)(&(addr[0])) = bfin_read32(FLASH_MAC);
 416         *(u16 *)(&(addr[4])) = bfin_read16(FLASH_MAC + 4);
 417 }
 418 EXPORT_SYMBOL(bfin_get_ether_addr);