arch/blackfin/mach-bf527/boards/ezbrd.c

   1 /*
   2  * Copyright 2004-2009 Analog Devices Inc.
   3  *                2005 National ICT Australia (NICTA)
   4  *                      Aidan Williams <aidan@nicta.com.au>
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 #include <linux/device.h>
  10 #include <linux/platform_device.h>
  11 #include <linux/mtd/mtd.h>
  12 #include <linux/mtd/partitions.h>
  13 #include <linux/mtd/physmap.h>
  14 #include <linux/spi/spi.h>
  15 #include <linux/spi/flash.h>
  16
  17 #include <linux/i2c.h>
  18 #include <linux/irq.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/usb/musb.h>
  21 #include <asm/dma.h>
  22 #include <asm/bfin5xx_spi.h>
  23 #include <asm/reboot.h>
  24 #include <asm/nand.h>
  25 #include <asm/portmux.h>
  26 #include <asm/dpmc.h>
  27 #include <linux/spi/ad7877.h>
  28
  29 /*
  30  * Name the Board for the /proc/cpuinfo
  31  */
  32 const char bfin_board_name[] = "ADI BF526-EZBRD";
  33
  34 /*
  35  *  Driver needs to know address, irq and flag pin.
  36  */
  37
  38 #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
  39 static struct resource musb_resources[] = {
  40         [0] = {
  41                 .start  = 0xffc03800,
  42                 .end    = 0xffc03cff,
  43                 .flags  = IORESOURCE_MEM,
  44         },
  45         [1] = { /* general IRQ */
  46                 .start  = IRQ_USB_INT0,
  47                 .end    = IRQ_USB_INT0,
  48                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  49         },
  50         [2] = { /* DMA IRQ */
  51                 .start  = IRQ_USB_DMA,
  52                 .end    = IRQ_USB_DMA,
  53                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  54         },
  55 };
  56
  57 static struct musb_hdrc_config musb_config = {
  58         .multipoint     = 0,
  59         .dyn_fifo       = 0,
  60         .soft_con       = 1,
  61         .dma            = 1,
  62         .num_eps        = 8,
  63         .dma_channels   = 8,
  64         .gpio_vrsel     = GPIO_PG13,
  65         /* Some custom boards need to be active low, just set it to "0"
  66          * if it is the case.
  67          */
  68         .gpio_vrsel_active      = 1,
  69 };
  70
  71 static struct musb_hdrc_platform_data musb_plat = {
  72 #if defined(CONFIG_USB_MUSB_OTG)
  73         .mode           = MUSB_OTG,
  74 #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
  75         .mode           = MUSB_HOST,
  76 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
  77         .mode           = MUSB_PERIPHERAL,
  78 #endif
  79         .config         = &musb_config,
  80 };
  81
  82 static u64 musb_dmamask = ~(u32)0;
  83
  84 static struct platform_device musb_device = {
  85         .name           = "musb_hdrc",
  86         .id             = 0,
  87         .dev = {
  88                 .dma_mask               = &musb_dmamask,
  89                 .coherent_dma_mask      = 0xffffffff,
  90                 .platform_data          = &musb_plat,
  91         },
  92         .num_resources  = ARRAY_SIZE(musb_resources),
  93         .resource       = musb_resources,
  94 };
  95 #endif
  96
  97 #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
  98 static struct mtd_partition ezbrd_partitions[] = {
  99         {
 100                 .name       = "bootloader(nor)",
 101                 .size       = 0x40000,
 102                 .offset     = 0,
 103         }, {
 104                 .name       = "linux kernel(nor)",
 105                 .size       = 0x1C0000,
 106                 .offset     = MTDPART_OFS_APPEND,
 107         }, {
 108                 .name       = "file system(nor)",
 109                 .size       = MTDPART_SIZ_FULL,
 110                 .offset     = MTDPART_OFS_APPEND,
 111         }
 112 };
 113
 114 static struct physmap_flash_data ezbrd_flash_data = {
 115         .width      = 2,
 116         .parts      = ezbrd_partitions,
 117         .nr_parts   = ARRAY_SIZE(ezbrd_partitions),
 118 };
 119
 120 static struct resource ezbrd_flash_resource = {
 121         .start = 0x20000000,
 122         .end   = 0x203fffff,
 123         .flags = IORESOURCE_MEM,
 124 };
 125
 126 static struct platform_device ezbrd_flash_device = {
 127         .name          = "physmap-flash",
 128         .id            = 0,
 129         .dev = {
 130                 .platform_data = &ezbrd_flash_data,
 131         },
 132         .num_resources = 1,
 133         .resource      = &ezbrd_flash_resource,
 134 };
 135 #endif
 136
 137 #if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
 138 static struct mtd_partition partition_info[] = {
 139         {
 140                 .name = "linux kernel(nand)",
 141                 .offset = 0,
 142                 .size = 4 * 1024 * 1024,
 143         },
 144         {
 145                 .name = "file system(nand)",
 146                 .offset = MTDPART_OFS_APPEND,
 147                 .size = MTDPART_SIZ_FULL,
 148         },
 149 };
 150
 151 static struct bf5xx_nand_platform bf5xx_nand_platform = {
 152         .page_size = NFC_PG_SIZE_256,
 153         .data_width = NFC_NWIDTH_8,
 154         .partitions = partition_info,
 155         .nr_partitions = ARRAY_SIZE(partition_info),
 156         .rd_dly = 3,
 157         .wr_dly = 3,
 158 };
 159
 160 static struct resource bf5xx_nand_resources[] = {
 161         {
 162                 .start = NFC_CTL,
 163                 .end = NFC_DATA_RD + 2,
 164                 .flags = IORESOURCE_MEM,
 165         },
 166         {
 167                 .start = CH_NFC,
 168                 .end = CH_NFC,
 169                 .flags = IORESOURCE_IRQ,
 170         },
 171 };
 172
 173 static struct platform_device bf5xx_nand_device = {
 174         .name = "bf5xx-nand",
 175         .id = 0,
 176         .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
 177         .resource = bf5xx_nand_resources,
 178         .dev = {
 179                 .platform_data = &bf5xx_nand_platform,
 180         },
 181 };
 182 #endif
 183
 184 #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
 185 static struct platform_device rtc_device = {
 186         .name = "rtc-bfin",
 187         .id   = -1,
 188 };
 189 #endif
 190
 191
 192 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
 193 static struct platform_device bfin_mii_bus = {
 194         .name = "bfin_mii_bus",
 195 };
 196
 197 static struct platform_device bfin_mac_device = {
 198         .name = "bfin_mac",
 199         .dev.platform_data = &bfin_mii_bus,
 200 };
 201 #endif
 202
 203 #if defined(CONFIG_MTD_M25P80) \
 204         || defined(CONFIG_MTD_M25P80_MODULE)
 205 static struct mtd_partition bfin_spi_flash_partitions[] = {
 206         {
 207                 .name = "bootloader(spi)",
 208                 .size = 0x00040000,
 209                 .offset = 0,
 210                 .mask_flags = MTD_CAP_ROM
 211         }, {
 212                 .name = "linux kernel(spi)",
 213                 .size = MTDPART_SIZ_FULL,
 214                 .offset = MTDPART_OFS_APPEND,
 215         }
 216 };
 217
 218 static struct flash_platform_data bfin_spi_flash_data = {
 219         .name = "m25p80",
 220         .parts = bfin_spi_flash_partitions,
 221         .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
 222         .type = "sst25wf040",
 223 };
 224
 225 /* SPI flash chip (sst25wf040) */
 226 static struct bfin5xx_spi_chip spi_flash_chip_info = {
 227         .enable_dma = 0,         /* use dma transfer with this chip*/
 228         .bits_per_word = 8,
 229 };
 230 #endif
 231
 232 #if defined(CONFIG_BFIN_SPI_ADC) \
 233         || defined(CONFIG_BFIN_SPI_ADC_MODULE)
 234 /* SPI ADC chip */
 235 static struct bfin5xx_spi_chip spi_adc_chip_info = {
 236         .enable_dma = 1,         /* use dma transfer with this chip*/
 237         .bits_per_word = 16,
 238 };
 239 #endif
 240
 241 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
 242 static struct bfin5xx_spi_chip mmc_spi_chip_info = {
 243         .enable_dma = 0,
 244         .bits_per_word = 8,
 245 };
 246 #endif
 247
 248 #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
 249 static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
 250         .enable_dma = 0,
 251         .bits_per_word = 16,
 252 };
 253
 254 static const struct ad7877_platform_data bfin_ad7877_ts_info = {
 255         .model                  = 7877,
 256         .vref_delay_usecs       = 50,   /* internal, no capacitor */
 257         .x_plate_ohms           = 419,
 258         .y_plate_ohms           = 486,
 259         .pressure_max           = 1000,
 260         .pressure_min           = 0,
 261         .stopacq_polarity       = 1,
 262         .first_conversion_delay = 3,
 263         .acquisition_time       = 1,
 264         .averaging              = 1,
 265         .pen_down_acc_interval  = 1,
 266 };
 267 #endif
 268
 269 #if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
 270 #include <linux/spi/ad7879.h>
 271 static const struct ad7879_platform_data bfin_ad7879_ts_info = {
 272         .model                  = 7879, /* Model = AD7879 */
 273         .x_plate_ohms           = 620,  /* 620 Ohm from the touch datasheet */
 274         .pressure_max           = 10000,
 275         .pressure_min           = 0,
 276         .first_conversion_delay = 3,    /* wait 512us before do a first conversion */
 277         .acquisition_time       = 1,    /* 4us acquisition time per sample */
 278         .median                 = 2,    /* do 8 measurements */
 279         .averaging              = 1,    /* take the average of 4 middle samples */
 280         .pen_down_acc_interval  = 255,  /* 9.4 ms */
 281         .gpio_export            = 1,    /* Export GPIO to gpiolib */
 282         .gpio_base              = -1,   /* Dynamic allocation */
 283 };
 284 #endif
 285
 286 #if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
 287 static struct bfin5xx_spi_chip spi_ad7879_chip_info = {
 288         .enable_dma = 0,
 289         .bits_per_word = 16,
 290 };
 291 #endif
 292
 293 #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
 294          && defined(CONFIG_SND_SOC_WM8731_SPI)
 295 static struct bfin5xx_spi_chip spi_wm8731_chip_info = {
 296         .enable_dma = 0,
 297         .bits_per_word = 16,
 298 };
 299 #endif
 300
 301 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
 302 static struct bfin5xx_spi_chip spidev_chip_info = {
 303         .enable_dma = 0,
 304         .bits_per_word = 8,
 305 };
 306 #endif
 307
 308 #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
 309 static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
 310         .enable_dma = 0,
 311         .bits_per_word = 8,
 312 };
 313 #endif
 314
 315 static struct spi_board_info bfin_spi_board_info[] __initdata = {
 316 #if defined(CONFIG_MTD_M25P80) \
 317         || defined(CONFIG_MTD_M25P80_MODULE)
 318         {
 319                 /* the modalias must be the same as spi device driver name */
 320                 .modalias = "m25p80", /* Name of spi_driver for this device */
 321                 .max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
 322                 .bus_num = 0, /* Framework bus number */
 323                 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
 324                 .platform_data = &bfin_spi_flash_data,
 325                 .controller_data = &spi_flash_chip_info,
 326                 .mode = SPI_MODE_3,
 327         },
 328 #endif
 329
 330 #if defined(CONFIG_BFIN_SPI_ADC) \
 331         || defined(CONFIG_BFIN_SPI_ADC_MODULE)
 332         {
 333                 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
 334                 .max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
 335                 .bus_num = 0, /* Framework bus number */
 336                 .chip_select = 1, /* Framework chip select. */
 337                 .platform_data = NULL, /* No spi_driver specific config */
 338                 .controller_data = &spi_adc_chip_info,
 339         },
 340 #endif
 341
 342 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
 343         {
 344                 .modalias = "mmc_spi",
 345                 .max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
 346                 .bus_num = 0,
 347                 .chip_select = 5,
 348                 .controller_data = &mmc_spi_chip_info,
 349                 .mode = SPI_MODE_3,
 350         },
 351 #endif
 352 #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
 353         {
 354                 .modalias               = "ad7877",
 355                 .platform_data          = &bfin_ad7877_ts_info,
 356                 .irq                    = IRQ_PF8,
 357                 .max_speed_hz   = 12500000,     /* max spi clock (SCK) speed in HZ */
 358                 .bus_num        = 0,
 359                 .chip_select  = 2,
 360                 .controller_data = &spi_ad7877_chip_info,
 361         },
 362 #endif
 363 #if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
 364         {
 365                 .modalias = "ad7879",
 366                 .platform_data = &bfin_ad7879_ts_info,
 367                 .irq = IRQ_PG0,
 368                 .max_speed_hz = 5000000,     /* max spi clock (SCK) speed in HZ */
 369                 .bus_num = 0,
 370                 .chip_select = 5,
 371                 .controller_data = &spi_ad7879_chip_info,
 372                 .mode = SPI_CPHA | SPI_CPOL,
 373         },
 374 #endif
 375 #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
 376          && defined(CONFIG_SND_SOC_WM8731_SPI)
 377         {
 378                 .modalias       = "wm8731",
 379                 .max_speed_hz   = 3125000,     /* max spi clock (SCK) speed in HZ */
 380                 .bus_num        = 0,
 381                 .chip_select    = 5,
 382                 .controller_data = &spi_wm8731_chip_info,
 383                 .mode = SPI_MODE_0,
 384         },
 385 #endif
 386 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
 387         {
 388                 .modalias = "spidev",
 389                 .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
 390                 .bus_num = 0,
 391                 .chip_select = 1,
 392                 .controller_data = &spidev_chip_info,
 393         },
 394 #endif
 395 #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
 396         {
 397                 .modalias = "bfin-lq035q1-spi",
 398                 .max_speed_hz = 20000000,     /* max spi clock (SCK) speed in HZ */
 399                 .bus_num = 0,
 400                 .chip_select = 1,
 401                 .controller_data = &lq035q1_spi_chip_info,
 402                 .mode = SPI_CPHA | SPI_CPOL,
 403         },
 404 #endif
 405 };
 406
 407 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
 408 /* SPI controller data */
 409 static struct bfin5xx_spi_master bfin_spi0_info = {
 410         .num_chipselect = 8,
 411         .enable_dma = 1,  /* master has the ability to do dma transfer */
 412         .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
 413 };
 414
 415 /* SPI (0) */
 416 static struct resource bfin_spi0_resource[] = {
 417         [0] = {
 418                 .start = SPI0_REGBASE,
 419                 .end   = SPI0_REGBASE + 0xFF,
 420                 .flags = IORESOURCE_MEM,
 421                 },
 422         [1] = {
 423                 .start = CH_SPI,
 424                 .end   = CH_SPI,
 425                 .flags = IORESOURCE_DMA,
 426         },
 427         [2] = {
 428                 .start = IRQ_SPI,
 429                 .end   = IRQ_SPI,
 430                 .flags = IORESOURCE_IRQ,
 431         },
 432 };
 433
 434 static struct platform_device bfin_spi0_device = {
 435         .name = "bfin-spi",
 436         .id = 0, /* Bus number */
 437         .num_resources = ARRAY_SIZE(bfin_spi0_resource),
 438         .resource = bfin_spi0_resource,
 439         .dev = {
 440                 .platform_data = &bfin_spi0_info, /* Passed to driver */
 441         },
 442 };
 443 #endif  /* spi master and devices */
 444
 445 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
 446 #ifdef CONFIG_SERIAL_BFIN_UART0
 447 static struct resource bfin_uart0_resources[] = {
 448         {
 449                 .start = UART0_THR,
 450                 .end = UART0_GCTL+2,
 451                 .flags = IORESOURCE_MEM,
 452         },
 453         {
 454                 .start = IRQ_UART0_RX,
 455                 .end = IRQ_UART0_RX+1,
 456                 .flags = IORESOURCE_IRQ,
 457         },
 458         {
 459                 .start = IRQ_UART0_ERROR,
 460                 .end = IRQ_UART0_ERROR,
 461                 .flags = IORESOURCE_IRQ,
 462         },
 463         {
 464                 .start = CH_UART0_TX,
 465                 .end = CH_UART0_TX,
 466                 .flags = IORESOURCE_DMA,
 467         },
 468         {
 469                 .start = CH_UART0_RX,
 470                 .end = CH_UART0_RX,
 471                 .flags = IORESOURCE_DMA,
 472         },
 473 };
 474
 475 unsigned short bfin_uart0_peripherals[] = {
 476         P_UART0_TX, P_UART0_RX, 0
 477 };
 478
 479 static struct platform_device bfin_uart0_device = {
 480         .name = "bfin-uart",
 481         .id = 0,
 482         .num_resources = ARRAY_SIZE(bfin_uart0_resources),
 483         .resource = bfin_uart0_resources,
 484         .dev = {
 485                 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
 486         },
 487 };
 488 #endif
 489 #ifdef CONFIG_SERIAL_BFIN_UART1
 490 static struct resource bfin_uart1_resources[] = {
 491         {
 492                 .start = UART1_THR,
 493                 .end = UART1_GCTL+2,
 494                 .flags = IORESOURCE_MEM,
 495         },
 496         {
 497                 .start = IRQ_UART1_RX,
 498                 .end = IRQ_UART1_RX+1,
 499                 .flags = IORESOURCE_IRQ,
 500         },
 501         {
 502                 .start = IRQ_UART1_ERROR,
 503                 .end = IRQ_UART1_ERROR,
 504                 .flags = IORESOURCE_IRQ,
 505         },
 506         {
 507                 .start = CH_UART1_TX,
 508                 .end = CH_UART1_TX,
 509                 .flags = IORESOURCE_DMA,
 510         },
 511         {
 512                 .start = CH_UART1_RX,
 513                 .end = CH_UART1_RX,
 514                 .flags = IORESOURCE_DMA,
 515         },
 516 #ifdef CONFIG_BFIN_UART1_CTSRTS
 517         {       /* CTS pin */
 518                 .start = GPIO_PG0,
 519                 .end = GPIO_PG0,
 520                 .flags = IORESOURCE_IO,
 521         },
 522         {       /* RTS pin */
 523                 .start = GPIO_PF10,
 524                 .end = GPIO_PF10,
 525                 .flags = IORESOURCE_IO,
 526         },
 527 #endif
 528 };
 529
 530 unsigned short bfin_uart1_peripherals[] = {
 531         P_UART1_TX, P_UART1_RX, 0
 532 };
 533
 534 static struct platform_device bfin_uart1_device = {
 535         .name = "bfin-uart",
 536         .id = 1,
 537         .num_resources = ARRAY_SIZE(bfin_uart1_resources),
 538         .resource = bfin_uart1_resources,
 539         .dev = {
 540                 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
 541         },
 542 };
 543 #endif
 544 #endif
 545
 546 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
 547 #ifdef CONFIG_BFIN_SIR0
 548 static struct resource bfin_sir0_resources[] = {
 549         {
 550                 .start = 0xFFC00400,
 551                 .end = 0xFFC004FF,
 552                 .flags = IORESOURCE_MEM,
 553         },
 554         {
 555                 .start = IRQ_UART0_RX,
 556                 .end = IRQ_UART0_RX+1,
 557                 .flags = IORESOURCE_IRQ,
 558         },
 559         {
 560                 .start = CH_UART0_RX,
 561                 .end = CH_UART0_RX+1,
 562                 .flags = IORESOURCE_DMA,
 563         },
 564 };
 565
 566 static struct platform_device bfin_sir0_device = {
 567         .name = "bfin_sir",
 568         .id = 0,
 569         .num_resources = ARRAY_SIZE(bfin_sir0_resources),
 570         .resource = bfin_sir0_resources,
 571 };
 572 #endif
 573 #ifdef CONFIG_BFIN_SIR1
 574 static struct resource bfin_sir1_resources[] = {
 575         {
 576                 .start = 0xFFC02000,
 577                 .end = 0xFFC020FF,
 578                 .flags = IORESOURCE_MEM,
 579         },
 580         {
 581                 .start = IRQ_UART1_RX,
 582                 .end = IRQ_UART1_RX+1,
 583                 .flags = IORESOURCE_IRQ,
 584         },
 585         {
 586                 .start = CH_UART1_RX,
 587                 .end = CH_UART1_RX+1,
 588                 .flags = IORESOURCE_DMA,
 589         },
 590 };
 591
 592 static struct platform_device bfin_sir1_device = {
 593         .name = "bfin_sir",
 594         .id = 1,
 595         .num_resources = ARRAY_SIZE(bfin_sir1_resources),
 596         .resource = bfin_sir1_resources,
 597 };
 598 #endif
 599 #endif
 600
 601 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
 602 static struct resource bfin_twi0_resource[] = {
 603         [0] = {
 604                 .start = TWI0_REGBASE,
 605                 .end   = TWI0_REGBASE,
 606                 .flags = IORESOURCE_MEM,
 607         },
 608         [1] = {
 609                 .start = IRQ_TWI,
 610                 .end   = IRQ_TWI,
 611                 .flags = IORESOURCE_IRQ,
 612         },
 613 };
 614
 615 static struct platform_device i2c_bfin_twi_device = {
 616         .name = "i2c-bfin-twi",
 617         .id = 0,
 618         .num_resources = ARRAY_SIZE(bfin_twi0_resource),
 619         .resource = bfin_twi0_resource,
 620 };
 621 #endif
 622
 623 static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
 624 #if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
 625         {
 626                 I2C_BOARD_INFO("pcf8574_lcd", 0x22),
 627         },
 628 #endif
 629 #if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE)
 630         {
 631                 I2C_BOARD_INFO("pcf8574_keypad", 0x27),
 632                 .irq = IRQ_PF8,
 633         },
 634 #endif
 635 };
 636
 637 #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
 638 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
 639 static struct resource bfin_sport0_uart_resources[] = {
 640         {
 641                 .start = SPORT0_TCR1,
 642                 .end = SPORT0_MRCS3+4,
 643                 .flags = IORESOURCE_MEM,
 644         },
 645         {
 646                 .start = IRQ_SPORT0_RX,
 647                 .end = IRQ_SPORT0_RX+1,
 648                 .flags = IORESOURCE_IRQ,
 649         },
 650         {
 651                 .start = IRQ_SPORT0_ERROR,
 652                 .end = IRQ_SPORT0_ERROR,
 653                 .flags = IORESOURCE_IRQ,
 654         },
 655 };
 656
 657 unsigned short bfin_sport0_peripherals[] = {
 658         P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
 659         P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
 660 };
 661
 662 static struct platform_device bfin_sport0_uart_device = {
 663         .name = "bfin-sport-uart",
 664         .id = 0,
 665         .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
 666         .resource = bfin_sport0_uart_resources,
 667         .dev = {
 668                 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
 669         },
 670 };
 671 #endif
 672 #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
 673 static struct resource bfin_sport1_uart_resources[] = {
 674         {
 675                 .start = SPORT1_TCR1,
 676                 .end = SPORT1_MRCS3+4,
 677                 .flags = IORESOURCE_MEM,
 678         },
 679         {
 680                 .start = IRQ_SPORT1_RX,
 681                 .end = IRQ_SPORT1_RX+1,
 682                 .flags = IORESOURCE_IRQ,
 683         },
 684         {
 685                 .start = IRQ_SPORT1_ERROR,
 686                 .end = IRQ_SPORT1_ERROR,
 687                 .flags = IORESOURCE_IRQ,
 688         },
 689 };
 690
 691 unsigned short bfin_sport1_peripherals[] = {
 692         P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
 693         P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
 694 };
 695
 696 static struct platform_device bfin_sport1_uart_device = {
 697         .name = "bfin-sport-uart",
 698         .id = 1,
 699         .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
 700         .resource = bfin_sport1_uart_resources,
 701         .dev = {
 702                 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
 703         },
 704 };
 705 #endif
 706 #endif
 707
 708 #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
 709 #include <linux/input.h>
 710 #include <linux/gpio_keys.h>
 711
 712 static struct gpio_keys_button bfin_gpio_keys_table[] = {
 713         {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
 714         {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
 715 };
 716
 717 static struct gpio_keys_platform_data bfin_gpio_keys_data = {
 718         .buttons        = bfin_gpio_keys_table,
 719         .nbuttons       = ARRAY_SIZE(bfin_gpio_keys_table),
 720 };
 721
 722 static struct platform_device bfin_device_gpiokeys = {
 723         .name      = "gpio-keys",
 724         .dev = {
 725                 .platform_data = &bfin_gpio_keys_data,
 726         },
 727 };
 728 #endif
 729
 730 static const unsigned int cclk_vlev_datasheet[] =
 731 {
 732         VRPAIR(VLEV_100, 400000000),
 733         VRPAIR(VLEV_105, 426000000),
 734         VRPAIR(VLEV_110, 500000000),
 735         VRPAIR(VLEV_115, 533000000),
 736         VRPAIR(VLEV_120, 600000000),
 737 };
 738
 739 static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
 740         .tuple_tab = cclk_vlev_datasheet,
 741         .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
 742         .vr_settling_time = 25 /* us */,
 743 };
 744
 745 static struct platform_device bfin_dpmc = {
 746         .name = "bfin dpmc",
 747         .dev = {
 748                 .platform_data = &bfin_dmpc_vreg_data,
 749         },
 750 };
 751
 752 #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
 753 #include <asm/bfin-lq035q1.h>
 754
 755 static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
 756         .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
 757         .ppi_mode = USE_RGB565_16_BIT_PPI,
 758         .use_bl = 1,
 759         .gpio_bl = GPIO_PG12,
 760 };
 761
 762 static struct resource bfin_lq035q1_resources[] = {
 763         {
 764                 .start = IRQ_PPI_ERROR,
 765                 .end = IRQ_PPI_ERROR,
 766                 .flags = IORESOURCE_IRQ,
 767         },
 768 };
 769
 770 static struct platform_device bfin_lq035q1_device = {
 771         .name           = "bfin-lq035q1",
 772         .id             = -1,
 773         .num_resources  = ARRAY_SIZE(bfin_lq035q1_resources),
 774         .resource       = bfin_lq035q1_resources,
 775         .dev            = {
 776                 .platform_data = &bfin_lq035q1_data,
 777         },
 778 };
 779 #endif
 780
 781 static struct platform_device *stamp_devices[] __initdata = {
 782
 783         &bfin_dpmc,
 784
 785 #if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
 786         &bf5xx_nand_device,
 787 #endif
 788
 789 #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
 790         &rtc_device,
 791 #endif
 792
 793 #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
 794         &musb_device,
 795 #endif
 796
 797 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
 798         &bfin_mii_bus,
 799         &bfin_mac_device,
 800 #endif
 801
 802 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
 803         &bfin_spi0_device,
 804 #endif
 805
 806 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
 807 #ifdef CONFIG_SERIAL_BFIN_UART0
 808         &bfin_uart0_device,
 809 #endif
 810 #ifdef CONFIG_SERIAL_BFIN_UART1
 811         &bfin_uart1_device,
 812 #endif
 813 #endif
 814
 815 #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
 816         &bfin_lq035q1_device,
 817 #endif
 818
 819 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
 820 #ifdef CONFIG_BFIN_SIR0
 821         &bfin_sir0_device,
 822 #endif
 823 #ifdef CONFIG_BFIN_SIR1
 824         &bfin_sir1_device,
 825 #endif
 826 #endif
 827
 828 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
 829         &i2c_bfin_twi_device,
 830 #endif
 831
 832 #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
 833 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
 834         &bfin_sport0_uart_device,
 835 #endif
 836 #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
 837         &bfin_sport1_uart_device,
 838 #endif
 839 #endif
 840
 841 #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
 842         &bfin_device_gpiokeys,
 843 #endif
 844
 845 #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
 846         &ezbrd_flash_device,
 847 #endif
 848 };
 849
 850 static int __init ezbrd_init(void)
 851 {
 852         printk(KERN_INFO "%s(): registering device resources\n", __func__);
 853         i2c_register_board_info(0, bfin_i2c_board_info,
 854                                 ARRAY_SIZE(bfin_i2c_board_info));
 855         platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
 856         spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
 857         return 0;
 858 }
 859
 860 arch_initcall(ezbrd_init);
 861
 862 static struct platform_device *ezbrd_early_devices[] __initdata = {
 863 #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
 864 #ifdef CONFIG_SERIAL_BFIN_UART0
 865         &bfin_uart0_device,
 866 #endif
 867 #ifdef CONFIG_SERIAL_BFIN_UART1
 868         &bfin_uart1_device,
 869 #endif
 870 #endif
 871
 872 #if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
 873 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
 874         &bfin_sport0_uart_device,
 875 #endif
 876 #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
 877         &bfin_sport1_uart_device,
 878 #endif
 879 #endif
 880 };
 881
 882 void __init native_machine_early_platform_add_devices(void)
 883 {
 884         printk(KERN_INFO "register early platform devices\n");
 885         early_platform_add_devices(ezbrd_early_devices,
 886                 ARRAY_SIZE(ezbrd_early_devices));
 887 }
 888
 889 void native_machine_restart(char *cmd)
 890 {
 891         /* workaround reboot hang when booting from SPI */
 892         if ((bfin_read_SYSCR() & 0x7) == 0x3)
 893                 bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
 894 }
 895
 896 void bfin_get_ether_addr(char *addr)
 897 {
 898         /* the MAC is stored in OTP memory page 0xDF */
 899         u32 ret;
 900         u64 otp_mac;
 901         u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
 902
 903         ret = otp_read(0xDF, 0x00, &otp_mac);
 904         if (!(ret & 0x1)) {
 905                 char *otp_mac_p = (char *)&otp_mac;
 906                 for (ret = 0; ret < 6; ++ret)
 907                         addr[ret] = otp_mac_p[5 - ret];
 908         }
 909 }
 910 EXPORT_SYMBOL(bfin_get_ether_addr);