arch/blackfin/kernel/time-ts.c

   1 /*
   2  * Based on arm clockevents implementation and old bfin time tick.
   3  *
   4  * Copyright 2008-2009 Analog Devics Inc.
   5  *                2008 GeoTechnologies
   6  *                     Vitja Makarov
   7  *
   8  * Licensed under the GPL-2
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/profile.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/time.h>
  15 #include <linux/timex.h>
  16 #include <linux/irq.h>
  17 #include <linux/clocksource.h>
  18 #include <linux/clockchips.h>
  19 #include <linux/cpufreq.h>
  20
  21 #include <asm/blackfin.h>
  22 #include <asm/time.h>
  23 #include <asm/gptimers.h>
  24 #include <asm/nmi.h>
  25
  26
  27 #if defined(CONFIG_CYCLES_CLOCKSOURCE)
  28
  29 static notrace cycle_t bfin_read_cycles(struct clocksource *cs)
  30 {
  31 #ifdef CONFIG_CPU_FREQ
  32         return __bfin_cycles_off + (get_cycles() << __bfin_cycles_mod);
  33 #else
  34         return get_cycles();
  35 #endif
  36 }
  37
  38 static struct clocksource bfin_cs_cycles = {
  39         .name           = "bfin_cs_cycles",
  40         .rating         = 400,
  41         .read           = bfin_read_cycles,
  42         .mask           = CLOCKSOURCE_MASK(64),
  43         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
  44 };
  45
  46 static inline unsigned long long bfin_cs_cycles_sched_clock(void)
  47 {
  48         return clocksource_cyc2ns(bfin_read_cycles(&bfin_cs_cycles),
  49                 bfin_cs_cycles.mult, bfin_cs_cycles.shift);
  50 }
  51
  52 static int __init bfin_cs_cycles_init(void)
  53 {
  54         if (clocksource_register_hz(&bfin_cs_cycles, get_cclk()))
  55                 panic("failed to register clocksource");
  56
  57         return 0;
  58 }
  59 #else
  60 # define bfin_cs_cycles_init()
  61 #endif
  62
  63 #ifdef CONFIG_GPTMR0_CLOCKSOURCE
  64
  65 void __init setup_gptimer0(void)
  66 {
  67         disable_gptimers(TIMER0bit);
  68
  69         set_gptimer_config(TIMER0_id, \
  70                 TIMER_OUT_DIS | TIMER_PERIOD_CNT | TIMER_MODE_PWM);
  71         set_gptimer_period(TIMER0_id, -1);
  72         set_gptimer_pwidth(TIMER0_id, -2);
  73         SSYNC();
  74         enable_gptimers(TIMER0bit);
  75 }
  76
  77 static cycle_t bfin_read_gptimer0(struct clocksource *cs)
  78 {
  79         return bfin_read_TIMER0_COUNTER();
  80 }
  81
  82 static struct clocksource bfin_cs_gptimer0 = {
  83         .name           = "bfin_cs_gptimer0",
  84         .rating         = 350,
  85         .read           = bfin_read_gptimer0,
  86         .mask           = CLOCKSOURCE_MASK(32),
  87         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
  88 };
  89
  90 static inline unsigned long long bfin_cs_gptimer0_sched_clock(void)
  91 {
  92         return clocksource_cyc2ns(bfin_read_TIMER0_COUNTER(),
  93                 bfin_cs_gptimer0.mult, bfin_cs_gptimer0.shift);
  94 }
  95
  96 static int __init bfin_cs_gptimer0_init(void)
  97 {
  98         setup_gptimer0();
  99
 100         if (clocksource_register_hz(&bfin_cs_gptimer0, get_sclk()))
 101                 panic("failed to register clocksource");
 102
 103         return 0;
 104 }
 105 #else
 106 # define bfin_cs_gptimer0_init()
 107 #endif
 108
 109 #if defined(CONFIG_GPTMR0_CLOCKSOURCE) || defined(CONFIG_CYCLES_CLOCKSOURCE)
 110 /* prefer to use cycles since it has higher rating */
 111 notrace unsigned long long sched_clock(void)
 112 {
 113 #if defined(CONFIG_CYCLES_CLOCKSOURCE)
 114         return bfin_cs_cycles_sched_clock();
 115 #else
 116         return bfin_cs_gptimer0_sched_clock();
 117 #endif
 118 }
 119 #endif
 120
 121 #if defined(CONFIG_TICKSOURCE_GPTMR0)
 122 static int bfin_gptmr0_set_next_event(unsigned long cycles,
 123                                      struct clock_event_device *evt)
 124 {
 125         disable_gptimers(TIMER0bit);
 126
 127         /* it starts counting three SCLK cycles after the TIMENx bit is set */
 128         set_gptimer_pwidth(TIMER0_id, cycles - 3);
 129         enable_gptimers(TIMER0bit);
 130         return 0;
 131 }
 132
 133 static void bfin_gptmr0_set_mode(enum clock_event_mode mode,
 134                                 struct clock_event_device *evt)
 135 {
 136         switch (mode) {
 137         case CLOCK_EVT_MODE_PERIODIC: {
 138                 set_gptimer_config(TIMER0_id, \
 139                         TIMER_OUT_DIS | TIMER_IRQ_ENA | \
 140                         TIMER_PERIOD_CNT | TIMER_MODE_PWM);
 141                 set_gptimer_period(TIMER0_id, get_sclk() / HZ);
 142                 set_gptimer_pwidth(TIMER0_id, get_sclk() / HZ - 1);
 143                 enable_gptimers(TIMER0bit);
 144                 break;
 145         }
 146         case CLOCK_EVT_MODE_ONESHOT:
 147                 disable_gptimers(TIMER0bit);
 148                 set_gptimer_config(TIMER0_id, \
 149                         TIMER_OUT_DIS | TIMER_IRQ_ENA | TIMER_MODE_PWM);
 150                 set_gptimer_period(TIMER0_id, 0);
 151                 break;
 152         case CLOCK_EVT_MODE_UNUSED:
 153         case CLOCK_EVT_MODE_SHUTDOWN:
 154                 disable_gptimers(TIMER0bit);
 155                 break;
 156         case CLOCK_EVT_MODE_RESUME:
 157                 break;
 158         }
 159 }
 160
 161 static void bfin_gptmr0_ack(void)
 162 {
 163         set_gptimer_status(TIMER_GROUP1, TIMER_STATUS_TIMIL0);
 164 }
 165
 166 static void __init bfin_gptmr0_init(void)
 167 {
 168         disable_gptimers(TIMER0bit);
 169 }
 170
 171 #ifdef CONFIG_CORE_TIMER_IRQ_L1
 172 __attribute__((l1_text))
 173 #endif
 174 irqreturn_t bfin_gptmr0_interrupt(int irq, void *dev_id)
 175 {
 176         struct clock_event_device *evt = dev_id;
 177         smp_mb();
 178         evt->event_handler(evt);
 179         bfin_gptmr0_ack();
 180         return IRQ_HANDLED;
 181 }
 182
 183 static struct irqaction gptmr0_irq = {
 184         .name           = "Blackfin GPTimer0",
 185         .flags          = IRQF_DISABLED | IRQF_TIMER | \
 186                           IRQF_IRQPOLL | IRQF_PERCPU,
 187         .handler        = bfin_gptmr0_interrupt,
 188 };
 189
 190 static struct clock_event_device clockevent_gptmr0 = {
 191         .name           = "bfin_gptimer0",
 192         .rating         = 300,
 193         .irq            = IRQ_TIMER0,
 194         .shift          = 32,
 195         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 196         .set_next_event = bfin_gptmr0_set_next_event,
 197         .set_mode       = bfin_gptmr0_set_mode,
 198 };
 199
 200 static void __init bfin_gptmr0_clockevent_init(struct clock_event_device *evt)
 201 {
 202         unsigned long clock_tick;
 203
 204         clock_tick = get_sclk();
 205         evt->mult = div_sc(clock_tick, NSEC_PER_SEC, evt->shift);
 206         evt->max_delta_ns = clockevent_delta2ns(-1, evt);
 207         evt->min_delta_ns = clockevent_delta2ns(100, evt);
 208
 209         evt->cpumask = cpumask_of(0);
 210
 211         clockevents_register_device(evt);
 212 }
 213 #endif /* CONFIG_TICKSOURCE_GPTMR0 */
 214
 215 #if defined(CONFIG_TICKSOURCE_CORETMR)
 216 /* per-cpu local core timer */
 217 static DEFINE_PER_CPU(struct clock_event_device, coretmr_events);
 218
 219 static int bfin_coretmr_set_next_event(unsigned long cycles,
 220                                 struct clock_event_device *evt)
 221 {
 222         bfin_write_TCNTL(TMPWR);
 223         CSYNC();
 224         bfin_write_TCOUNT(cycles);
 225         CSYNC();
 226         bfin_write_TCNTL(TMPWR | TMREN);
 227         return 0;
 228 }
 229
 230 static void bfin_coretmr_set_mode(enum clock_event_mode mode,
 231                                 struct clock_event_device *evt)
 232 {
 233         switch (mode) {
 234         case CLOCK_EVT_MODE_PERIODIC: {
 235                 unsigned long tcount = ((get_cclk() / (HZ * TIME_SCALE)) - 1);
 236                 bfin_write_TCNTL(TMPWR);
 237                 CSYNC();
 238                 bfin_write_TSCALE(TIME_SCALE - 1);
 239                 bfin_write_TPERIOD(tcount);
 240                 bfin_write_TCOUNT(tcount);
 241                 CSYNC();
 242                 bfin_write_TCNTL(TMPWR | TMREN | TAUTORLD);
 243                 break;
 244         }
 245         case CLOCK_EVT_MODE_ONESHOT:
 246                 bfin_write_TCNTL(TMPWR);
 247                 CSYNC();
 248                 bfin_write_TSCALE(TIME_SCALE - 1);
 249                 bfin_write_TPERIOD(0);
 250                 bfin_write_TCOUNT(0);
 251                 break;
 252         case CLOCK_EVT_MODE_UNUSED:
 253         case CLOCK_EVT_MODE_SHUTDOWN:
 254                 bfin_write_TCNTL(0);
 255                 CSYNC();
 256                 break;
 257         case CLOCK_EVT_MODE_RESUME:
 258                 break;
 259         }
 260 }
 261
 262 void bfin_coretmr_init(void)
 263 {
 264         /* power up the timer, but don't enable it just yet */
 265         bfin_write_TCNTL(TMPWR);
 266         CSYNC();
 267
 268         /* the TSCALE prescaler counter. */
 269         bfin_write_TSCALE(TIME_SCALE - 1);
 270         bfin_write_TPERIOD(0);
 271         bfin_write_TCOUNT(0);
 272
 273         CSYNC();
 274 }
 275
 276 #ifdef CONFIG_CORE_TIMER_IRQ_L1
 277 __attribute__((l1_text))
 278 #endif
 279 irqreturn_t bfin_coretmr_interrupt(int irq, void *dev_id)
 280 {
 281         int cpu = smp_processor_id();
 282         struct clock_event_device *evt = &per_cpu(coretmr_events, cpu);
 283
 284         smp_mb();
 285         evt->event_handler(evt);
 286
 287         touch_nmi_watchdog();
 288
 289         return IRQ_HANDLED;
 290 }
 291
 292 static struct irqaction coretmr_irq = {
 293         .name           = "Blackfin CoreTimer",
 294         .flags          = IRQF_DISABLED | IRQF_TIMER | \
 295                           IRQF_IRQPOLL | IRQF_PERCPU,
 296         .handler        = bfin_coretmr_interrupt,
 297 };
 298
 299 void bfin_coretmr_clockevent_init(void)
 300 {
 301         unsigned long clock_tick;
 302         unsigned int cpu = smp_processor_id();
 303         struct clock_event_device *evt = &per_cpu(coretmr_events, cpu);
 304
 305         evt->name = "bfin_core_timer";
 306         evt->rating = 350;
 307         evt->irq = -1;
 308         evt->shift = 32;
 309         evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
 310         evt->set_next_event = bfin_coretmr_set_next_event;
 311         evt->set_mode = bfin_coretmr_set_mode;
 312
 313         clock_tick = get_cclk() / TIME_SCALE;
 314         evt->mult = div_sc(clock_tick, NSEC_PER_SEC, evt->shift);
 315         evt->max_delta_ns = clockevent_delta2ns(-1, evt);
 316         evt->min_delta_ns = clockevent_delta2ns(100, evt);
 317
 318         evt->cpumask = cpumask_of(cpu);
 319
 320         clockevents_register_device(evt);
 321 }
 322 #endif /* CONFIG_TICKSOURCE_CORETMR */
 323
 324
 325 void read_persistent_clock(struct timespec *ts)
 326 {
 327         time_t secs_since_1970 = (365 * 37 + 9) * 24 * 60 * 60; /* 1 Jan 2007 */
 328         ts->tv_sec = secs_since_1970;
 329         ts->tv_nsec = 0;
 330 }
 331
 332 void __init time_init(void)
 333 {
 334
 335 #ifdef CONFIG_RTC_DRV_BFIN
 336         /* [#2663] hack to filter junk RTC values that would cause
 337          * userspace to have to deal with time values greater than
 338          * 2^31 seconds (which uClibc cannot cope with yet)
 339          */
 340         if ((bfin_read_RTC_STAT() & 0xC0000000) == 0xC0000000) {
 341                 printk(KERN_NOTICE "bfin-rtc: invalid date; resetting\n");
 342                 bfin_write_RTC_STAT(0);
 343         }
 344 #endif
 345
 346         bfin_cs_cycles_init();
 347         bfin_cs_gptimer0_init();
 348
 349 #if defined(CONFIG_TICKSOURCE_CORETMR)
 350         bfin_coretmr_init();
 351         setup_irq(IRQ_CORETMR, &coretmr_irq);
 352         bfin_coretmr_clockevent_init();
 353 #endif
 354
 355 #if defined(CONFIG_TICKSOURCE_GPTMR0)
 356         bfin_gptmr0_init();
 357         setup_irq(IRQ_TIMER0, &gptmr0_irq);
 358         gptmr0_irq.dev_id = &clockevent_gptmr0;
 359         bfin_gptmr0_clockevent_init(&clockevent_gptmr0);
 360 #endif
 361
 362 #if !defined(CONFIG_TICKSOURCE_CORETMR) && !defined(CONFIG_TICKSOURCE_GPTMR0)
 363 # error at least one clock event device is required
 364 #endif
 365 }