arch/blackfin/kernel/cplb-nompu/cplbinit.c

   1 /*
   2  * Blackfin CPLB initialization
   3  *
   4  *               Copyright 2004-2007 Analog Devices Inc.
   5  *
   6  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, see the file COPYING, or write
  20  * to the Free Software Foundation, Inc.,
  21  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  22  */
  23 #include <linux/module.h>
  24
  25 #include <asm/blackfin.h>
  26 #include <asm/cplb.h>
  27 #include <asm/cplbinit.h>
  28
  29 #ifdef CONFIG_MAX_MEM_SIZE
  30 # define CPLB_MEM CONFIG_MAX_MEM_SIZE
  31 #else
  32 # define CPLB_MEM CONFIG_MEM_SIZE
  33 #endif
  34
  35 /*
  36 * Number of required data CPLB switchtable entries
  37 * MEMSIZE / 4 (we mostly install 4M page size CPLBs
  38 * approx 16 for smaller 1MB page size CPLBs for allignment purposes
  39 * 1 for L1 Data Memory
  40 * possibly 1 for L2 Data Memory
  41 * 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
  42 * 1 for ASYNC Memory
  43 */
  44 #define MAX_SWITCH_D_CPLBS (((CPLB_MEM / 4) + 16 + 1 + 1 + 1 \
  45                                  + ASYNC_MEMORY_CPLB_COVERAGE) * 2)
  46
  47 /*
  48 * Number of required instruction CPLB switchtable entries
  49 * MEMSIZE / 4 (we mostly install 4M page size CPLBs
  50 * approx 12 for smaller 1MB page size CPLBs for allignment purposes
  51 * 1 for L1 Instruction Memory
  52 * possibly 1 for L2 Instruction Memory
  53 * 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
  54 */
  55 #define MAX_SWITCH_I_CPLBS (((CPLB_MEM / 4) + 12 + 1 + 1 + 1) * 2)
  56
  57
  58 u_long icplb_table[MAX_CPLBS + 1];
  59 u_long dcplb_table[MAX_CPLBS + 1];
  60
  61 #ifdef CONFIG_CPLB_SWITCH_TAB_L1
  62 # define PDT_ATTR __attribute__((l1_data))
  63 #else
  64 # define PDT_ATTR
  65 #endif
  66
  67 u_long ipdt_table[MAX_SWITCH_I_CPLBS + 1] PDT_ATTR;
  68 u_long dpdt_table[MAX_SWITCH_D_CPLBS + 1] PDT_ATTR;
  69
  70 #ifdef CONFIG_CPLB_INFO
  71 u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS] PDT_ATTR;
  72 u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS] PDT_ATTR;
  73 #endif
  74
  75 struct s_cplb {
  76         struct cplb_tab init_i;
  77         struct cplb_tab init_d;
  78         struct cplb_tab switch_i;
  79         struct cplb_tab switch_d;
  80 };
  81
  82 #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
  83 static struct cplb_desc cplb_data[] = {
  84         {
  85                 .start = 0,
  86                 .end = SIZE_1K,
  87                 .psize = SIZE_1K,
  88                 .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
  89                 .i_conf = SDRAM_OOPS,
  90                 .d_conf = SDRAM_OOPS,
  91 #if defined(CONFIG_DEBUG_HUNT_FOR_ZERO)
  92                 .valid = 1,
  93 #else
  94                 .valid = 0,
  95 #endif
  96                 .name = "Zero Pointer Guard Page",
  97         },
  98         {
  99                 .start = L1_CODE_START,
 100                 .end = L1_CODE_START + L1_CODE_LENGTH,
 101                 .psize = SIZE_4M,
 102                 .attr = INITIAL_T | SWITCH_T | I_CPLB,
 103                 .i_conf = L1_IMEMORY,
 104                 .d_conf = 0,
 105                 .valid = 1,
 106                 .name = "L1 I-Memory",
 107         },
 108         {
 109                 .start = L1_DATA_A_START,
 110                 .end = L1_DATA_B_START + L1_DATA_B_LENGTH,
 111                 .psize = SIZE_4M,
 112                 .attr = INITIAL_T | SWITCH_T | D_CPLB,
 113                 .i_conf = 0,
 114                 .d_conf = L1_DMEMORY,
 115 #if ((L1_DATA_A_LENGTH > 0) || (L1_DATA_B_LENGTH > 0))
 116                 .valid = 1,
 117 #else
 118                 .valid = 0,
 119 #endif
 120                 .name = "L1 D-Memory",
 121         },
 122         {
 123                 .start = 0,
 124                 .end = 0,  /* dynamic */
 125                 .psize = 0,
 126                 .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
 127                 .i_conf = SDRAM_IGENERIC,
 128                 .d_conf = SDRAM_DGENERIC,
 129                 .valid = 1,
 130                 .name = "Kernel Memory",
 131         },
 132         {
 133                 .start = 0, /* dynamic */
 134                 .end = 0, /* dynamic */
 135                 .psize = 0,
 136                 .attr = INITIAL_T | SWITCH_T | D_CPLB,
 137                 .i_conf = SDRAM_IGENERIC,
 138                 .d_conf = SDRAM_DNON_CHBL,
 139                 .valid = 1,
 140                 .name = "uClinux MTD Memory",
 141         },
 142         {
 143                 .start = 0, /* dynamic */
 144                 .end = 0,   /* dynamic */
 145                 .psize = SIZE_1M,
 146                 .attr = INITIAL_T | SWITCH_T | D_CPLB,
 147                 .d_conf = SDRAM_DNON_CHBL,
 148                 .valid = 1,
 149                 .name = "Uncached DMA Zone",
 150         },
 151         {
 152                 .start = 0, /* dynamic */
 153                 .end = 0, /* dynamic */
 154                 .psize = 0,
 155                 .attr = SWITCH_T | D_CPLB,
 156                 .i_conf = 0, /* dynamic */
 157                 .d_conf = 0, /* dynamic */
 158                 .valid = 1,
 159                 .name = "Reserved Memory",
 160         },
 161         {
 162                 .start = ASYNC_BANK0_BASE,
 163                 .end = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE,
 164                 .psize = 0,
 165                 .attr = SWITCH_T | D_CPLB,
 166                 .d_conf = SDRAM_EBIU,
 167                 .valid = 1,
 168                 .name = "Asynchronous Memory Banks",
 169         },
 170         {
 171 #ifdef L2_START
 172                 .start = L2_START,
 173                 .end = L2_START + L2_LENGTH,
 174                 .psize = SIZE_1M,
 175                 .attr = SWITCH_T | I_CPLB | D_CPLB,
 176                 .i_conf = L2_MEMORY,
 177                 .d_conf = L2_MEMORY,
 178                 .valid = 1,
 179 #else
 180                 .valid = 0,
 181 #endif
 182                 .name = "L2 Memory",
 183         },
 184         {
 185                 .start = BOOT_ROM_START,
 186                 .end = BOOT_ROM_START + BOOT_ROM_LENGTH,
 187                 .psize = SIZE_1M,
 188                 .attr = SWITCH_T | I_CPLB | D_CPLB,
 189                 .i_conf = SDRAM_IGENERIC,
 190                 .d_conf = SDRAM_DGENERIC,
 191                 .valid = 1,
 192                 .name = "On-Chip BootROM",
 193         },
 194 };
 195
 196 static u16 __init lock_kernel_check(u32 start, u32 end)
 197 {
 198         if ((end   <= (u32) _end && end   >= (u32)_stext) ||
 199             (start <= (u32) _end && start >= (u32)_stext))
 200                 return IN_KERNEL;
 201         return 0;
 202 }
 203
 204 static unsigned short __init
 205 fill_cplbtab(struct cplb_tab *table,
 206              unsigned long start, unsigned long end,
 207              unsigned long block_size, unsigned long cplb_data)
 208 {
 209         int i;
 210
 211         switch (block_size) {
 212         case SIZE_4M:
 213                 i = 3;
 214                 break;
 215         case SIZE_1M:
 216                 i = 2;
 217                 break;
 218         case SIZE_4K:
 219                 i = 1;
 220                 break;
 221         case SIZE_1K:
 222         default:
 223                 i = 0;
 224                 break;
 225         }
 226
 227         cplb_data = (cplb_data & ~(3 << 16)) | (i << 16);
 228
 229         while ((start < end) && (table->pos < table->size)) {
 230
 231                 table->tab[table->pos++] = start;
 232
 233                 if (lock_kernel_check(start, start + block_size) == IN_KERNEL)
 234                         table->tab[table->pos++] =
 235                             cplb_data | CPLB_LOCK | CPLB_DIRTY;
 236                 else
 237                         table->tab[table->pos++] = cplb_data;
 238
 239                 start += block_size;
 240         }
 241         return 0;
 242 }
 243
 244 static unsigned short __init
 245 close_cplbtab(struct cplb_tab *table)
 246 {
 247
 248         while (table->pos < table->size) {
 249
 250                 table->tab[table->pos++] = 0;
 251                 table->tab[table->pos++] = 0; /* !CPLB_VALID */
 252         }
 253         return 0;
 254 }
 255
 256 /* helper function */
 257 static void __init
 258 __fill_code_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
 259 {
 260         if (cplb_data[i].psize) {
 261                 fill_cplbtab(t,
 262                                 cplb_data[i].start,
 263                                 cplb_data[i].end,
 264                                 cplb_data[i].psize,
 265                                 cplb_data[i].i_conf);
 266         } else {
 267 #if defined(CONFIG_BFIN_ICACHE)
 268                 if (ANOMALY_05000263 && i == SDRAM_KERN) {
 269                         fill_cplbtab(t,
 270                                         cplb_data[i].start,
 271                                         cplb_data[i].end,
 272                                         SIZE_4M,
 273                                         cplb_data[i].i_conf);
 274                 } else
 275 #endif
 276                 {
 277                         fill_cplbtab(t,
 278                                         cplb_data[i].start,
 279                                         a_start,
 280                                         SIZE_1M,
 281                                         cplb_data[i].i_conf);
 282                         fill_cplbtab(t,
 283                                         a_start,
 284                                         a_end,
 285                                         SIZE_4M,
 286                                         cplb_data[i].i_conf);
 287                         fill_cplbtab(t, a_end,
 288                                         cplb_data[i].end,
 289                                         SIZE_1M,
 290                                         cplb_data[i].i_conf);
 291                 }
 292         }
 293 }
 294
 295 static void __init
 296 __fill_data_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
 297 {
 298         if (cplb_data[i].psize) {
 299                 fill_cplbtab(t,
 300                                 cplb_data[i].start,
 301                                 cplb_data[i].end,
 302                                 cplb_data[i].psize,
 303                                 cplb_data[i].d_conf);
 304         } else {
 305                 fill_cplbtab(t,
 306                                 cplb_data[i].start,
 307                                 a_start, SIZE_1M,
 308                                 cplb_data[i].d_conf);
 309                 fill_cplbtab(t, a_start,
 310                                 a_end, SIZE_4M,
 311                                 cplb_data[i].d_conf);
 312                 fill_cplbtab(t, a_end,
 313                                 cplb_data[i].end,
 314                                 SIZE_1M,
 315                                 cplb_data[i].d_conf);
 316         }
 317 }
 318
 319 void __init generate_cpl_tables(void)
 320 {
 321
 322         u16 i, j, process;
 323         u32 a_start, a_end, as, ae, as_1m;
 324
 325         struct cplb_tab *t_i = NULL;
 326         struct cplb_tab *t_d = NULL;
 327         struct s_cplb cplb;
 328
 329         printk(KERN_INFO "NOMPU: setting up cplb tables for global access\n");
 330
 331         cplb.init_i.size = MAX_CPLBS;
 332         cplb.init_d.size = MAX_CPLBS;
 333         cplb.switch_i.size = MAX_SWITCH_I_CPLBS;
 334         cplb.switch_d.size = MAX_SWITCH_D_CPLBS;
 335
 336         cplb.init_i.pos = 0;
 337         cplb.init_d.pos = 0;
 338         cplb.switch_i.pos = 0;
 339         cplb.switch_d.pos = 0;
 340
 341         cplb.init_i.tab = icplb_table;
 342         cplb.init_d.tab = dcplb_table;
 343         cplb.switch_i.tab = ipdt_table;
 344         cplb.switch_d.tab = dpdt_table;
 345
 346         cplb_data[SDRAM_KERN].end = memory_end;
 347
 348 #ifdef CONFIG_MTD_UCLINUX
 349         cplb_data[SDRAM_RAM_MTD].start = memory_mtd_start;
 350         cplb_data[SDRAM_RAM_MTD].end = memory_mtd_start + mtd_size;
 351         cplb_data[SDRAM_RAM_MTD].valid = mtd_size > 0;
 352 # if defined(CONFIG_ROMFS_FS)
 353         cplb_data[SDRAM_RAM_MTD].attr |= I_CPLB;
 354
 355         /*
 356          * The ROMFS_FS size is often not multiple of 1MB.
 357          * This can cause multiple CPLB sets covering the same memory area.
 358          * This will then cause multiple CPLB hit exceptions.
 359          * Workaround: We ensure a contiguous memory area by extending the kernel
 360          * memory section over the mtd section.
 361          * For ROMFS_FS memory must be covered with ICPLBs anyways.
 362          * So there is no difference between kernel and mtd memory setup.
 363          */
 364
 365         cplb_data[SDRAM_KERN].end = memory_mtd_start + mtd_size;;
 366         cplb_data[SDRAM_RAM_MTD].valid = 0;
 367
 368 # endif
 369 #else
 370         cplb_data[SDRAM_RAM_MTD].valid = 0;
 371 #endif
 372
 373         cplb_data[SDRAM_DMAZ].start = _ramend - DMA_UNCACHED_REGION;
 374         cplb_data[SDRAM_DMAZ].end = _ramend;
 375
 376         cplb_data[RES_MEM].start = _ramend;
 377         cplb_data[RES_MEM].end = physical_mem_end;
 378
 379         if (reserved_mem_dcache_on)
 380                 cplb_data[RES_MEM].d_conf = SDRAM_DGENERIC;
 381         else
 382                 cplb_data[RES_MEM].d_conf = SDRAM_DNON_CHBL;
 383
 384         if (reserved_mem_icache_on)
 385                 cplb_data[RES_MEM].i_conf = SDRAM_IGENERIC;
 386         else
 387                 cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL;
 388
 389         for (i = ZERO_P; i < ARRAY_SIZE(cplb_data); ++i) {
 390                 if (!cplb_data[i].valid)
 391                         continue;
 392
 393                 as_1m = cplb_data[i].start % SIZE_1M;
 394
 395                 /* We need to make sure all sections are properly 1M aligned
 396                  * However between Kernel Memory and the Kernel mtd section, depending on the
 397                  * rootfs size, there can be overlapping memory areas.
 398                  */
 399
 400                 if (as_1m && i != L1I_MEM && i != L1D_MEM) {
 401 #ifdef CONFIG_MTD_UCLINUX
 402                         if (i == SDRAM_RAM_MTD) {
 403                                 if ((cplb_data[SDRAM_KERN].end + 1) > cplb_data[SDRAM_RAM_MTD].start)
 404                                         cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M)) + SIZE_1M;
 405                                 else
 406                                         cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M));
 407                         } else
 408 #endif
 409                                 printk(KERN_WARNING "Unaligned Start of %s at 0x%X\n",
 410                                        cplb_data[i].name, cplb_data[i].start);
 411                 }
 412
 413                 as = cplb_data[i].start % SIZE_4M;
 414                 ae = cplb_data[i].end % SIZE_4M;
 415
 416                 if (as)
 417                         a_start = cplb_data[i].start + (SIZE_4M - (as));
 418                 else
 419                         a_start = cplb_data[i].start;
 420
 421                 a_end = cplb_data[i].end - ae;
 422
 423                 for (j = INITIAL_T; j <= SWITCH_T; j++) {
 424
 425                         switch (j) {
 426                         case INITIAL_T:
 427                                 if (cplb_data[i].attr & INITIAL_T) {
 428                                         t_i = &cplb.init_i;
 429                                         t_d = &cplb.init_d;
 430                                         process = 1;
 431                                 } else
 432                                         process = 0;
 433                                 break;
 434                         case SWITCH_T:
 435                                 if (cplb_data[i].attr & SWITCH_T) {
 436                                         t_i = &cplb.switch_i;
 437                                         t_d = &cplb.switch_d;
 438                                         process = 1;
 439                                 } else
 440                                         process = 0;
 441                                 break;
 442                         default:
 443                                         process = 0;
 444                                 break;
 445                         }
 446
 447                         if (!process)
 448                                 continue;
 449                         if (cplb_data[i].attr & I_CPLB)
 450                                 __fill_code_cplbtab(t_i, i, a_start, a_end);
 451
 452                         if (cplb_data[i].attr & D_CPLB)
 453                                 __fill_data_cplbtab(t_d, i, a_start, a_end);
 454                 }
 455         }
 456
 457 /* close tables */
 458
 459         close_cplbtab(&cplb.init_i);
 460         close_cplbtab(&cplb.init_d);
 461
 462         cplb.init_i.tab[cplb.init_i.pos] = -1;
 463         cplb.init_d.tab[cplb.init_d.pos] = -1;
 464         cplb.switch_i.tab[cplb.switch_i.pos] = -1;
 465         cplb.switch_d.tab[cplb.switch_d.pos] = -1;
 466
 467 }
 468
 469 #endif
 470