arch/blackfin/kernel/cplb-nompu/cplbinit.c

   1 /*
   2  * Blackfin CPLB initialization
   3  *
   4  *               Copyright 2004-2007 Analog Devices Inc.
   5  *
   6  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, see the file COPYING, or write
  20  * to the Free Software Foundation, Inc.,
  21  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  22  */
  23 #include <linux/module.h>
  24
  25 #include <asm/blackfin.h>
  26 #include <asm/cplb.h>
  27 #include <asm/cplbinit.h>
  28
  29 u_long icplb_table[MAX_CPLBS + 1];
  30 u_long dcplb_table[MAX_CPLBS + 1];
  31
  32 #ifdef CONFIG_CPLB_SWITCH_TAB_L1
  33 # define PDT_ATTR __attribute__((l1_data))
  34 #else
  35 # define PDT_ATTR
  36 #endif
  37
  38 u_long ipdt_table[MAX_SWITCH_I_CPLBS + 1] PDT_ATTR;
  39 u_long dpdt_table[MAX_SWITCH_D_CPLBS + 1] PDT_ATTR;
  40
  41 #ifdef CONFIG_CPLB_INFO
  42 u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS] PDT_ATTR;
  43 u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS] PDT_ATTR;
  44 #endif
  45
  46 struct s_cplb {
  47         struct cplb_tab init_i;
  48         struct cplb_tab init_d;
  49         struct cplb_tab switch_i;
  50         struct cplb_tab switch_d;
  51 };
  52
  53 #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
  54 static struct cplb_desc cplb_data[] = {
  55         {
  56                 .start = 0,
  57                 .end = SIZE_1K,
  58                 .psize = SIZE_1K,
  59                 .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
  60                 .i_conf = SDRAM_OOPS,
  61                 .d_conf = SDRAM_OOPS,
  62 #if defined(CONFIG_DEBUG_HUNT_FOR_ZERO)
  63                 .valid = 1,
  64 #else
  65                 .valid = 0,
  66 #endif
  67                 .name = "Zero Pointer Guard Page",
  68         },
  69         {
  70                 .start = L1_CODE_START,
  71                 .end = L1_CODE_START + L1_CODE_LENGTH,
  72                 .psize = SIZE_4M,
  73                 .attr = INITIAL_T | SWITCH_T | I_CPLB,
  74                 .i_conf = L1_IMEMORY,
  75                 .d_conf = 0,
  76                 .valid = 1,
  77                 .name = "L1 I-Memory",
  78         },
  79         {
  80                 .start = L1_DATA_A_START,
  81                 .end = L1_DATA_B_START + L1_DATA_B_LENGTH,
  82                 .psize = SIZE_4M,
  83                 .attr = INITIAL_T | SWITCH_T | D_CPLB,
  84                 .i_conf = 0,
  85                 .d_conf = L1_DMEMORY,
  86 #if ((L1_DATA_A_LENGTH > 0) || (L1_DATA_B_LENGTH > 0))
  87                 .valid = 1,
  88 #else
  89                 .valid = 0,
  90 #endif
  91                 .name = "L1 D-Memory",
  92         },
  93         {
  94                 .start = 0,
  95                 .end = 0,  /* dynamic */
  96                 .psize = 0,
  97                 .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
  98                 .i_conf = SDRAM_IGENERIC,
  99                 .d_conf = SDRAM_DGENERIC,
 100                 .valid = 1,
 101                 .name = "Kernel Memory",
 102         },
 103         {
 104                 .start = 0, /* dynamic */
 105                 .end = 0, /* dynamic */
 106                 .psize = 0,
 107                 .attr = INITIAL_T | SWITCH_T | D_CPLB,
 108                 .i_conf = SDRAM_IGENERIC,
 109                 .d_conf = SDRAM_DNON_CHBL,
 110                 .valid = 1,
 111                 .name = "uClinux MTD Memory",
 112         },
 113         {
 114                 .start = 0, /* dynamic */
 115                 .end = 0,   /* dynamic */
 116                 .psize = SIZE_1M,
 117                 .attr = INITIAL_T | SWITCH_T | D_CPLB,
 118                 .d_conf = SDRAM_DNON_CHBL,
 119                 .valid = 1,
 120                 .name = "Uncached DMA Zone",
 121         },
 122         {
 123                 .start = 0, /* dynamic */
 124                 .end = 0, /* dynamic */
 125                 .psize = 0,
 126                 .attr = SWITCH_T | D_CPLB,
 127                 .i_conf = 0, /* dynamic */
 128                 .d_conf = 0, /* dynamic */
 129                 .valid = 1,
 130                 .name = "Reserved Memory",
 131         },
 132         {
 133                 .start = ASYNC_BANK0_BASE,
 134                 .end = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE,
 135                 .psize = 0,
 136                 .attr = SWITCH_T | D_CPLB,
 137                 .d_conf = SDRAM_EBIU,
 138                 .valid = 1,
 139                 .name = "Asynchronous Memory Banks",
 140         },
 141         {
 142 #ifdef L2_START
 143                 .start = L2_START,
 144                 .end = L2_START + L2_LENGTH,
 145                 .psize = SIZE_1M,
 146                 .attr = SWITCH_T | I_CPLB | D_CPLB,
 147                 .i_conf = L2_MEMORY,
 148                 .d_conf = L2_MEMORY,
 149                 .valid = 1,
 150 #else
 151                 .valid = 0,
 152 #endif
 153                 .name = "L2 Memory",
 154         },
 155         {
 156                 .start = BOOT_ROM_START,
 157                 .end = BOOT_ROM_START + BOOT_ROM_LENGTH,
 158                 .psize = SIZE_1M,
 159                 .attr = SWITCH_T | I_CPLB | D_CPLB,
 160                 .i_conf = SDRAM_IGENERIC,
 161                 .d_conf = SDRAM_DGENERIC,
 162                 .valid = 1,
 163                 .name = "On-Chip BootROM",
 164         },
 165 };
 166
 167 static u16 __init lock_kernel_check(u32 start, u32 end)
 168 {
 169         if ((end   <= (u32) _end && end   >= (u32)_stext) ||
 170             (start <= (u32) _end && start >= (u32)_stext))
 171                 return IN_KERNEL;
 172         return 0;
 173 }
 174
 175 static unsigned short __init
 176 fill_cplbtab(struct cplb_tab *table,
 177              unsigned long start, unsigned long end,
 178              unsigned long block_size, unsigned long cplb_data)
 179 {
 180         int i;
 181
 182         switch (block_size) {
 183         case SIZE_4M:
 184                 i = 3;
 185                 break;
 186         case SIZE_1M:
 187                 i = 2;
 188                 break;
 189         case SIZE_4K:
 190                 i = 1;
 191                 break;
 192         case SIZE_1K:
 193         default:
 194                 i = 0;
 195                 break;
 196         }
 197
 198         cplb_data = (cplb_data & ~(3 << 16)) | (i << 16);
 199
 200         while ((start < end) && (table->pos < table->size)) {
 201
 202                 table->tab[table->pos++] = start;
 203
 204                 if (lock_kernel_check(start, start + block_size) == IN_KERNEL)
 205                         table->tab[table->pos++] =
 206                             cplb_data | CPLB_LOCK | CPLB_DIRTY;
 207                 else
 208                         table->tab[table->pos++] = cplb_data;
 209
 210                 start += block_size;
 211         }
 212         return 0;
 213 }
 214
 215 static unsigned short __init
 216 close_cplbtab(struct cplb_tab *table)
 217 {
 218
 219         while (table->pos < table->size) {
 220
 221                 table->tab[table->pos++] = 0;
 222                 table->tab[table->pos++] = 0; /* !CPLB_VALID */
 223         }
 224         return 0;
 225 }
 226
 227 /* helper function */
 228 static void __fill_code_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
 229 {
 230         if (cplb_data[i].psize) {
 231                 fill_cplbtab(t,
 232                                 cplb_data[i].start,
 233                                 cplb_data[i].end,
 234                                 cplb_data[i].psize,
 235                                 cplb_data[i].i_conf);
 236         } else {
 237 #if defined(CONFIG_BFIN_ICACHE)
 238                 if (ANOMALY_05000263 && i == SDRAM_KERN) {
 239                         fill_cplbtab(t,
 240                                         cplb_data[i].start,
 241                                         cplb_data[i].end,
 242                                         SIZE_4M,
 243                                         cplb_data[i].i_conf);
 244                 } else
 245 #endif
 246                 {
 247                         fill_cplbtab(t,
 248                                         cplb_data[i].start,
 249                                         a_start,
 250                                         SIZE_1M,
 251                                         cplb_data[i].i_conf);
 252                         fill_cplbtab(t,
 253                                         a_start,
 254                                         a_end,
 255                                         SIZE_4M,
 256                                         cplb_data[i].i_conf);
 257                         fill_cplbtab(t, a_end,
 258                                         cplb_data[i].end,
 259                                         SIZE_1M,
 260                                         cplb_data[i].i_conf);
 261                 }
 262         }
 263 }
 264
 265 static void __fill_data_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
 266 {
 267         if (cplb_data[i].psize) {
 268                 fill_cplbtab(t,
 269                                 cplb_data[i].start,
 270                                 cplb_data[i].end,
 271                                 cplb_data[i].psize,
 272                                 cplb_data[i].d_conf);
 273         } else {
 274                 fill_cplbtab(t,
 275                                 cplb_data[i].start,
 276                                 a_start, SIZE_1M,
 277                                 cplb_data[i].d_conf);
 278                 fill_cplbtab(t, a_start,
 279                                 a_end, SIZE_4M,
 280                                 cplb_data[i].d_conf);
 281                 fill_cplbtab(t, a_end,
 282                                 cplb_data[i].end,
 283                                 SIZE_1M,
 284                                 cplb_data[i].d_conf);
 285         }
 286 }
 287
 288 void __init generate_cpl_tables(void)
 289 {
 290
 291         u16 i, j, process;
 292         u32 a_start, a_end, as, ae, as_1m;
 293
 294         struct cplb_tab *t_i = NULL;
 295         struct cplb_tab *t_d = NULL;
 296         struct s_cplb cplb;
 297
 298         cplb.init_i.size = MAX_CPLBS;
 299         cplb.init_d.size = MAX_CPLBS;
 300         cplb.switch_i.size = MAX_SWITCH_I_CPLBS;
 301         cplb.switch_d.size = MAX_SWITCH_D_CPLBS;
 302
 303         cplb.init_i.pos = 0;
 304         cplb.init_d.pos = 0;
 305         cplb.switch_i.pos = 0;
 306         cplb.switch_d.pos = 0;
 307
 308         cplb.init_i.tab = icplb_table;
 309         cplb.init_d.tab = dcplb_table;
 310         cplb.switch_i.tab = ipdt_table;
 311         cplb.switch_d.tab = dpdt_table;
 312
 313         cplb_data[SDRAM_KERN].end = memory_end;
 314
 315 #ifdef CONFIG_MTD_UCLINUX
 316         cplb_data[SDRAM_RAM_MTD].start = memory_mtd_start;
 317         cplb_data[SDRAM_RAM_MTD].end = memory_mtd_start + mtd_size;
 318         cplb_data[SDRAM_RAM_MTD].valid = mtd_size > 0;
 319 # if defined(CONFIG_ROMFS_FS)
 320         cplb_data[SDRAM_RAM_MTD].attr |= I_CPLB;
 321
 322         /*
 323          * The ROMFS_FS size is often not multiple of 1MB.
 324          * This can cause multiple CPLB sets covering the same memory area.
 325          * This will then cause multiple CPLB hit exceptions.
 326          * Workaround: We ensure a contiguous memory area by extending the kernel
 327          * memory section over the mtd section.
 328          * For ROMFS_FS memory must be covered with ICPLBs anyways.
 329          * So there is no difference between kernel and mtd memory setup.
 330          */
 331
 332         cplb_data[SDRAM_KERN].end = memory_mtd_start + mtd_size;;
 333         cplb_data[SDRAM_RAM_MTD].valid = 0;
 334
 335 # endif
 336 #else
 337         cplb_data[SDRAM_RAM_MTD].valid = 0;
 338 #endif
 339
 340         cplb_data[SDRAM_DMAZ].start = _ramend - DMA_UNCACHED_REGION;
 341         cplb_data[SDRAM_DMAZ].end = _ramend;
 342
 343         cplb_data[RES_MEM].start = _ramend;
 344         cplb_data[RES_MEM].end = physical_mem_end;
 345
 346         if (reserved_mem_dcache_on)
 347                 cplb_data[RES_MEM].d_conf = SDRAM_DGENERIC;
 348         else
 349                 cplb_data[RES_MEM].d_conf = SDRAM_DNON_CHBL;
 350
 351         if (reserved_mem_icache_on)
 352                 cplb_data[RES_MEM].i_conf = SDRAM_IGENERIC;
 353         else
 354                 cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL;
 355
 356         for (i = ZERO_P; i < ARRAY_SIZE(cplb_data); ++i) {
 357                 if (!cplb_data[i].valid)
 358                         continue;
 359
 360                 as_1m = cplb_data[i].start % SIZE_1M;
 361
 362                 /* We need to make sure all sections are properly 1M aligned
 363                  * However between Kernel Memory and the Kernel mtd section, depending on the
 364                  * rootfs size, there can be overlapping memory areas.
 365                  */
 366
 367                 if (as_1m && i != L1I_MEM && i != L1D_MEM) {
 368 #ifdef CONFIG_MTD_UCLINUX
 369                         if (i == SDRAM_RAM_MTD) {
 370                                 if ((cplb_data[SDRAM_KERN].end + 1) > cplb_data[SDRAM_RAM_MTD].start)
 371                                         cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M)) + SIZE_1M;
 372                                 else
 373                                         cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M));
 374                         } else
 375 #endif
 376                                 printk(KERN_WARNING "Unaligned Start of %s at 0x%X\n",
 377                                        cplb_data[i].name, cplb_data[i].start);
 378                 }
 379
 380                 as = cplb_data[i].start % SIZE_4M;
 381                 ae = cplb_data[i].end % SIZE_4M;
 382
 383                 if (as)
 384                         a_start = cplb_data[i].start + (SIZE_4M - (as));
 385                 else
 386                         a_start = cplb_data[i].start;
 387
 388                 a_end = cplb_data[i].end - ae;
 389
 390                 for (j = INITIAL_T; j <= SWITCH_T; j++) {
 391
 392                         switch (j) {
 393                         case INITIAL_T:
 394                                 if (cplb_data[i].attr & INITIAL_T) {
 395                                         t_i = &cplb.init_i;
 396                                         t_d = &cplb.init_d;
 397                                         process = 1;
 398                                 } else
 399                                         process = 0;
 400                                 break;
 401                         case SWITCH_T:
 402                                 if (cplb_data[i].attr & SWITCH_T) {
 403                                         t_i = &cplb.switch_i;
 404                                         t_d = &cplb.switch_d;
 405                                         process = 1;
 406                                 } else
 407                                         process = 0;
 408                                 break;
 409                         default:
 410                                         process = 0;
 411                                 break;
 412                         }
 413
 414                         if (!process)
 415                                 continue;
 416                         if (cplb_data[i].attr & I_CPLB)
 417                                 __fill_code_cplbtab(t_i, i, a_start, a_end);
 418
 419                         if (cplb_data[i].attr & D_CPLB)
 420                                 __fill_data_cplbtab(t_d, i, a_start, a_end);
 421                 }
 422         }
 423
 424 /* close tables */
 425
 426         close_cplbtab(&cplb.init_i);
 427         close_cplbtab(&cplb.init_d);
 428
 429         cplb.init_i.tab[cplb.init_i.pos] = -1;
 430         cplb.init_d.tab[cplb.init_d.pos] = -1;
 431         cplb.switch_i.tab[cplb.switch_i.pos] = -1;
 432         cplb.switch_d.tab[cplb.switch_d.pos] = -1;
 433
 434 }
 435
 436 #endif
 437