2 * Blackfin CPLB initialization
4 * Copyright 2007-2009 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
9 #include <linux/module.h>
11 #include <asm/blackfin.h>
12 #include <asm/cacheflush.h>
14 #include <asm/cplbinit.h>
15 #include <asm/mem_map.h>
17 struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS] PDT_ATTR;
18 struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS] PDT_ATTR;
20 int first_switched_icplb PDT_ATTR;
21 int first_switched_dcplb PDT_ATTR;
23 struct cplb_boundary dcplb_bounds[9] PDT_ATTR;
24 struct cplb_boundary icplb_bounds[9] PDT_ATTR;
26 int icplb_nr_bounds PDT_ATTR;
27 int dcplb_nr_bounds PDT_ATTR;
29 void __init generate_cplb_tables_cpu(unsigned int cpu)
34 struct cplb_entry *d_tbl = dcplb_tbl[cpu];
35 struct cplb_entry *i_tbl = icplb_tbl[cpu];
37 printk(KERN_INFO "NOMPU: setting up cplb tables\n");
41 #ifdef CONFIG_DEBUG_HUNT_FOR_ZERO
42 /* Set up the zero page. */
44 d_tbl[i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
46 i_tbl[i_i++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
49 /* Cover kernel memory with 4M pages. */
52 for (; addr < memory_start; addr += 4 * 1024 * 1024) {
53 d_tbl[i_d].addr = addr;
54 d_tbl[i_d++].data = SDRAM_DGENERIC | PAGE_SIZE_4MB;
55 i_tbl[i_i].addr = addr;
56 i_tbl[i_i++].data = SDRAM_IGENERIC | PAGE_SIZE_4MB;
59 /* Cover L1 memory. One 4M area for code and data each is enough. */
61 if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) {
62 d_tbl[i_d].addr = L1_DATA_A_START;
63 d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
65 i_tbl[i_i].addr = L1_CODE_START;
66 i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
70 if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) {
71 d_tbl[i_d].addr = COREB_L1_DATA_A_START;
72 d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
74 i_tbl[i_i].addr = COREB_L1_CODE_START;
75 i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
78 first_switched_dcplb = i_d;
79 first_switched_icplb = i_i;
81 BUG_ON(first_switched_dcplb > MAX_CPLBS);
82 BUG_ON(first_switched_icplb > MAX_CPLBS);
84 while (i_d < MAX_CPLBS)
85 d_tbl[i_d++].data = 0;
86 while (i_i < MAX_CPLBS)
87 i_tbl[i_i++].data = 0;
90 void __init generate_cplb_tables_all(void)
92 unsigned long uncached_end;
96 /* Normal RAM, including MTD FS. */
97 #ifdef CONFIG_MTD_UCLINUX
98 uncached_end = memory_mtd_start + mtd_size;
100 uncached_end = memory_end;
103 * if DMA uncached is less than 1MB, mark the 1MB chunk as uncached
104 * so that we don't have to use 4kB pages and cause CPLB thrashing
106 if ((DMA_UNCACHED_REGION >= 1 * 1024 * 1024) || !DMA_UNCACHED_REGION ||
107 ((_ramend - uncached_end) >= 1 * 1024 * 1024))
108 dcplb_bounds[i_d].eaddr = uncached_end;
110 dcplb_bounds[i_d].eaddr = uncached_end & ~(1 * 1024 * 1024);
111 dcplb_bounds[i_d++].data = SDRAM_DGENERIC;
112 /* DMA uncached region. */
113 if (DMA_UNCACHED_REGION) {
114 dcplb_bounds[i_d].eaddr = _ramend;
115 dcplb_bounds[i_d++].data = SDRAM_DNON_CHBL;
117 if (_ramend != physical_mem_end) {
118 /* Reserved memory. */
119 dcplb_bounds[i_d].eaddr = physical_mem_end;
120 dcplb_bounds[i_d++].data = (reserved_mem_dcache_on ?
121 SDRAM_DGENERIC : SDRAM_DNON_CHBL);
123 /* Addressing hole up to the async bank. */
124 dcplb_bounds[i_d].eaddr = ASYNC_BANK0_BASE;
125 dcplb_bounds[i_d++].data = 0;
127 dcplb_bounds[i_d].eaddr = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE;
128 dcplb_bounds[i_d++].data = SDRAM_EBIU;
129 /* Addressing hole up to BootROM. */
130 dcplb_bounds[i_d].eaddr = BOOT_ROM_START;
131 dcplb_bounds[i_d++].data = 0;
132 /* BootROM -- largest one should be less than 1 meg. */
133 dcplb_bounds[i_d].eaddr = BOOT_ROM_START + (1 * 1024 * 1024);
134 dcplb_bounds[i_d++].data = SDRAM_DGENERIC;
136 /* Addressing hole up to L2 SRAM. */
137 dcplb_bounds[i_d].eaddr = L2_START;
138 dcplb_bounds[i_d++].data = 0;
140 dcplb_bounds[i_d].eaddr = L2_START + L2_LENGTH;
141 dcplb_bounds[i_d++].data = L2_DMEMORY;
143 dcplb_nr_bounds = i_d;
144 BUG_ON(dcplb_nr_bounds > ARRAY_SIZE(dcplb_bounds));
147 /* Normal RAM, including MTD FS. */
148 icplb_bounds[i_i].eaddr = uncached_end;
149 icplb_bounds[i_i++].data = SDRAM_IGENERIC;
150 if (_ramend != physical_mem_end) {
151 /* DMA uncached region. */
152 if (DMA_UNCACHED_REGION) {
153 /* Normally this hole is caught by the async below. */
154 icplb_bounds[i_i].eaddr = _ramend;
155 icplb_bounds[i_i++].data = 0;
157 /* Reserved memory. */
158 icplb_bounds[i_i].eaddr = physical_mem_end;
159 icplb_bounds[i_i++].data = (reserved_mem_icache_on ?
160 SDRAM_IGENERIC : SDRAM_INON_CHBL);
162 /* Addressing hole up to the async bank. */
163 icplb_bounds[i_i].eaddr = ASYNC_BANK0_BASE;
164 icplb_bounds[i_i++].data = 0;
166 icplb_bounds[i_i].eaddr = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE;
167 icplb_bounds[i_i++].data = SDRAM_EBIU;
168 /* Addressing hole up to BootROM. */
169 icplb_bounds[i_i].eaddr = BOOT_ROM_START;
170 icplb_bounds[i_i++].data = 0;
171 /* BootROM -- largest one should be less than 1 meg. */
172 icplb_bounds[i_i].eaddr = BOOT_ROM_START + (1 * 1024 * 1024);
173 icplb_bounds[i_i++].data = SDRAM_IGENERIC;
176 /* Addressing hole up to L2 SRAM. */
177 icplb_bounds[i_i].eaddr = L2_START;
178 icplb_bounds[i_i++].data = 0;
180 icplb_bounds[i_i].eaddr = L2_START + L2_LENGTH;
181 icplb_bounds[i_i++].data = L2_IMEMORY;
183 icplb_nr_bounds = i_i;
184 BUG_ON(icplb_nr_bounds > ARRAY_SIZE(icplb_bounds));