arch/blackfin/kernel/cplb-nompu/cplbinit.c

   1 /*
   2  * Blackfin CPLB initialization
   3  *
   4  *               Copyright 2004-2007 Analog Devices Inc.
   5  *
   6  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, see the file COPYING, or write
  20  * to the Free Software Foundation, Inc.,
  21  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  22  */
  23 #include <linux/module.h>
  24
  25 #include <asm/blackfin.h>
  26 #include <asm/cplb.h>
  27 #include <asm/cplbinit.h>
  28
  29 #define CPLB_MEM CONFIG_MAX_MEM_SIZE
  30
  31 /*
  32 * Number of required data CPLB switchtable entries
  33 * MEMSIZE / 4 (we mostly install 4M page size CPLBs
  34 * approx 16 for smaller 1MB page size CPLBs for allignment purposes
  35 * 1 for L1 Data Memory
  36 * possibly 1 for L2 Data Memory
  37 * 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
  38 * 1 for ASYNC Memory
  39 */
  40 #define MAX_SWITCH_D_CPLBS (((CPLB_MEM / 4) + 16 + 1 + 1 + 1 \
  41                                  + ASYNC_MEMORY_CPLB_COVERAGE) * 2)
  42
  43 /*
  44 * Number of required instruction CPLB switchtable entries
  45 * MEMSIZE / 4 (we mostly install 4M page size CPLBs
  46 * approx 12 for smaller 1MB page size CPLBs for allignment purposes
  47 * 1 for L1 Instruction Memory
  48 * possibly 1 for L2 Instruction Memory
  49 * 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
  50 */
  51 #define MAX_SWITCH_I_CPLBS (((CPLB_MEM / 4) + 12 + 1 + 1 + 1) * 2)
  52
  53
  54 u_long icplb_table[MAX_CPLBS + 1];
  55 u_long dcplb_table[MAX_CPLBS + 1];
  56
  57 #ifdef CONFIG_CPLB_SWITCH_TAB_L1
  58 # define PDT_ATTR __attribute__((l1_data))
  59 #else
  60 # define PDT_ATTR
  61 #endif
  62
  63 u_long ipdt_table[MAX_SWITCH_I_CPLBS + 1] PDT_ATTR;
  64 u_long dpdt_table[MAX_SWITCH_D_CPLBS + 1] PDT_ATTR;
  65
  66 #ifdef CONFIG_CPLB_INFO
  67 u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS] PDT_ATTR;
  68 u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS] PDT_ATTR;
  69 #endif
  70
  71 struct s_cplb {
  72         struct cplb_tab init_i;
  73         struct cplb_tab init_d;
  74         struct cplb_tab switch_i;
  75         struct cplb_tab switch_d;
  76 };
  77
  78 #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
  79 static struct cplb_desc cplb_data[] = {
  80         {
  81                 .start = 0,
  82                 .end = SIZE_1K,
  83                 .psize = SIZE_1K,
  84                 .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
  85                 .i_conf = SDRAM_OOPS,
  86                 .d_conf = SDRAM_OOPS,
  87 #if defined(CONFIG_DEBUG_HUNT_FOR_ZERO)
  88                 .valid = 1,
  89 #else
  90                 .valid = 0,
  91 #endif
  92                 .name = "Zero Pointer Guard Page",
  93         },
  94         {
  95                 .start = L1_CODE_START,
  96                 .end = L1_CODE_START + L1_CODE_LENGTH,
  97                 .psize = SIZE_4M,
  98                 .attr = INITIAL_T | SWITCH_T | I_CPLB,
  99                 .i_conf = L1_IMEMORY,
 100                 .d_conf = 0,
 101                 .valid = 1,
 102                 .name = "L1 I-Memory",
 103         },
 104         {
 105                 .start = L1_DATA_A_START,
 106                 .end = L1_DATA_B_START + L1_DATA_B_LENGTH,
 107                 .psize = SIZE_4M,
 108                 .attr = INITIAL_T | SWITCH_T | D_CPLB,
 109                 .i_conf = 0,
 110                 .d_conf = L1_DMEMORY,
 111 #if ((L1_DATA_A_LENGTH > 0) || (L1_DATA_B_LENGTH > 0))
 112                 .valid = 1,
 113 #else
 114                 .valid = 0,
 115 #endif
 116                 .name = "L1 D-Memory",
 117         },
 118         {
 119                 .start = 0,
 120                 .end = 0,  /* dynamic */
 121                 .psize = 0,
 122                 .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
 123                 .i_conf = SDRAM_IGENERIC,
 124                 .d_conf = SDRAM_DGENERIC,
 125                 .valid = 1,
 126                 .name = "Kernel Memory",
 127         },
 128         {
 129                 .start = 0, /* dynamic */
 130                 .end = 0, /* dynamic */
 131                 .psize = 0,
 132                 .attr = INITIAL_T | SWITCH_T | D_CPLB,
 133                 .i_conf = SDRAM_IGENERIC,
 134                 .d_conf = SDRAM_DNON_CHBL,
 135                 .valid = 1,
 136                 .name = "uClinux MTD Memory",
 137         },
 138         {
 139                 .start = 0, /* dynamic */
 140                 .end = 0,   /* dynamic */
 141                 .psize = SIZE_1M,
 142                 .attr = INITIAL_T | SWITCH_T | D_CPLB,
 143                 .d_conf = SDRAM_DNON_CHBL,
 144                 .valid = 1,
 145                 .name = "Uncached DMA Zone",
 146         },
 147         {
 148                 .start = 0, /* dynamic */
 149                 .end = 0, /* dynamic */
 150                 .psize = 0,
 151                 .attr = SWITCH_T | D_CPLB,
 152                 .i_conf = 0, /* dynamic */
 153                 .d_conf = 0, /* dynamic */
 154                 .valid = 1,
 155                 .name = "Reserved Memory",
 156         },
 157         {
 158                 .start = ASYNC_BANK0_BASE,
 159                 .end = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE,
 160                 .psize = 0,
 161                 .attr = SWITCH_T | D_CPLB,
 162                 .d_conf = SDRAM_EBIU,
 163                 .valid = 1,
 164                 .name = "Asynchronous Memory Banks",
 165         },
 166         {
 167 #ifdef L2_START
 168                 .start = L2_START,
 169                 .end = L2_START + L2_LENGTH,
 170                 .psize = SIZE_1M,
 171                 .attr = SWITCH_T | I_CPLB | D_CPLB,
 172                 .i_conf = L2_MEMORY,
 173                 .d_conf = L2_MEMORY,
 174                 .valid = 1,
 175 #else
 176                 .valid = 0,
 177 #endif
 178                 .name = "L2 Memory",
 179         },
 180         {
 181                 .start = BOOT_ROM_START,
 182                 .end = BOOT_ROM_START + BOOT_ROM_LENGTH,
 183                 .psize = SIZE_1M,
 184                 .attr = SWITCH_T | I_CPLB | D_CPLB,
 185                 .i_conf = SDRAM_IGENERIC,
 186                 .d_conf = SDRAM_DGENERIC,
 187                 .valid = 1,
 188                 .name = "On-Chip BootROM",
 189         },
 190 };
 191
 192 static u16 __init lock_kernel_check(u32 start, u32 end)
 193 {
 194         if ((end   <= (u32) _end && end   >= (u32)_stext) ||
 195             (start <= (u32) _end && start >= (u32)_stext))
 196                 return IN_KERNEL;
 197         return 0;
 198 }
 199
 200 static unsigned short __init
 201 fill_cplbtab(struct cplb_tab *table,
 202              unsigned long start, unsigned long end,
 203              unsigned long block_size, unsigned long cplb_data)
 204 {
 205         int i;
 206
 207         switch (block_size) {
 208         case SIZE_4M:
 209                 i = 3;
 210                 break;
 211         case SIZE_1M:
 212                 i = 2;
 213                 break;
 214         case SIZE_4K:
 215                 i = 1;
 216                 break;
 217         case SIZE_1K:
 218         default:
 219                 i = 0;
 220                 break;
 221         }
 222
 223         cplb_data = (cplb_data & ~(3 << 16)) | (i << 16);
 224
 225         while ((start < end) && (table->pos < table->size)) {
 226
 227                 table->tab[table->pos++] = start;
 228
 229                 if (lock_kernel_check(start, start + block_size) == IN_KERNEL)
 230                         table->tab[table->pos++] =
 231                             cplb_data | CPLB_LOCK | CPLB_DIRTY;
 232                 else
 233                         table->tab[table->pos++] = cplb_data;
 234
 235                 start += block_size;
 236         }
 237         return 0;
 238 }
 239
 240 static unsigned short __init
 241 close_cplbtab(struct cplb_tab *table)
 242 {
 243
 244         while (table->pos < table->size) {
 245
 246                 table->tab[table->pos++] = 0;
 247                 table->tab[table->pos++] = 0; /* !CPLB_VALID */
 248         }
 249         return 0;
 250 }
 251
 252 /* helper function */
 253 static void __init
 254 __fill_code_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
 255 {
 256         if (cplb_data[i].psize) {
 257                 fill_cplbtab(t,
 258                                 cplb_data[i].start,
 259                                 cplb_data[i].end,
 260                                 cplb_data[i].psize,
 261                                 cplb_data[i].i_conf);
 262         } else {
 263 #if defined(CONFIG_BFIN_ICACHE)
 264                 if (ANOMALY_05000263 && i == SDRAM_KERN) {
 265                         fill_cplbtab(t,
 266                                         cplb_data[i].start,
 267                                         cplb_data[i].end,
 268                                         SIZE_4M,
 269                                         cplb_data[i].i_conf);
 270                 } else
 271 #endif
 272                 {
 273                         fill_cplbtab(t,
 274                                         cplb_data[i].start,
 275                                         a_start,
 276                                         SIZE_1M,
 277                                         cplb_data[i].i_conf);
 278                         fill_cplbtab(t,
 279                                         a_start,
 280                                         a_end,
 281                                         SIZE_4M,
 282                                         cplb_data[i].i_conf);
 283                         fill_cplbtab(t, a_end,
 284                                         cplb_data[i].end,
 285                                         SIZE_1M,
 286                                         cplb_data[i].i_conf);
 287                 }
 288         }
 289 }
 290
 291 static void __init
 292 __fill_data_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
 293 {
 294         if (cplb_data[i].psize) {
 295                 fill_cplbtab(t,
 296                                 cplb_data[i].start,
 297                                 cplb_data[i].end,
 298                                 cplb_data[i].psize,
 299                                 cplb_data[i].d_conf);
 300         } else {
 301                 fill_cplbtab(t,
 302                                 cplb_data[i].start,
 303                                 a_start, SIZE_1M,
 304                                 cplb_data[i].d_conf);
 305                 fill_cplbtab(t, a_start,
 306                                 a_end, SIZE_4M,
 307                                 cplb_data[i].d_conf);
 308                 fill_cplbtab(t, a_end,
 309                                 cplb_data[i].end,
 310                                 SIZE_1M,
 311                                 cplb_data[i].d_conf);
 312         }
 313 }
 314
 315 void __init generate_cpl_tables(void)
 316 {
 317
 318         u16 i, j, process;
 319         u32 a_start, a_end, as, ae, as_1m;
 320
 321         struct cplb_tab *t_i = NULL;
 322         struct cplb_tab *t_d = NULL;
 323         struct s_cplb cplb;
 324
 325         printk(KERN_INFO "NOMPU: setting up cplb tables for global access\n");
 326
 327         cplb.init_i.size = MAX_CPLBS;
 328         cplb.init_d.size = MAX_CPLBS;
 329         cplb.switch_i.size = MAX_SWITCH_I_CPLBS;
 330         cplb.switch_d.size = MAX_SWITCH_D_CPLBS;
 331
 332         cplb.init_i.pos = 0;
 333         cplb.init_d.pos = 0;
 334         cplb.switch_i.pos = 0;
 335         cplb.switch_d.pos = 0;
 336
 337         cplb.init_i.tab = icplb_table;
 338         cplb.init_d.tab = dcplb_table;
 339         cplb.switch_i.tab = ipdt_table;
 340         cplb.switch_d.tab = dpdt_table;
 341
 342         cplb_data[SDRAM_KERN].end = memory_end;
 343
 344 #ifdef CONFIG_MTD_UCLINUX
 345         cplb_data[SDRAM_RAM_MTD].start = memory_mtd_start;
 346         cplb_data[SDRAM_RAM_MTD].end = memory_mtd_start + mtd_size;
 347         cplb_data[SDRAM_RAM_MTD].valid = mtd_size > 0;
 348 # if defined(CONFIG_ROMFS_FS)
 349         cplb_data[SDRAM_RAM_MTD].attr |= I_CPLB;
 350
 351         /*
 352          * The ROMFS_FS size is often not multiple of 1MB.
 353          * This can cause multiple CPLB sets covering the same memory area.
 354          * This will then cause multiple CPLB hit exceptions.
 355          * Workaround: We ensure a contiguous memory area by extending the kernel
 356          * memory section over the mtd section.
 357          * For ROMFS_FS memory must be covered with ICPLBs anyways.
 358          * So there is no difference between kernel and mtd memory setup.
 359          */
 360
 361         cplb_data[SDRAM_KERN].end = memory_mtd_start + mtd_size;;
 362         cplb_data[SDRAM_RAM_MTD].valid = 0;
 363
 364 # endif
 365 #else
 366         cplb_data[SDRAM_RAM_MTD].valid = 0;
 367 #endif
 368
 369         cplb_data[SDRAM_DMAZ].start = _ramend - DMA_UNCACHED_REGION;
 370         cplb_data[SDRAM_DMAZ].end = _ramend;
 371
 372         cplb_data[RES_MEM].start = _ramend;
 373         cplb_data[RES_MEM].end = physical_mem_end;
 374
 375         if (reserved_mem_dcache_on)
 376                 cplb_data[RES_MEM].d_conf = SDRAM_DGENERIC;
 377         else
 378                 cplb_data[RES_MEM].d_conf = SDRAM_DNON_CHBL;
 379
 380         if (reserved_mem_icache_on)
 381                 cplb_data[RES_MEM].i_conf = SDRAM_IGENERIC;
 382         else
 383                 cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL;
 384
 385         for (i = ZERO_P; i < ARRAY_SIZE(cplb_data); ++i) {
 386                 if (!cplb_data[i].valid)
 387                         continue;
 388
 389                 as_1m = cplb_data[i].start % SIZE_1M;
 390
 391                 /* We need to make sure all sections are properly 1M aligned
 392                  * However between Kernel Memory and the Kernel mtd section, depending on the
 393                  * rootfs size, there can be overlapping memory areas.
 394                  */
 395
 396                 if (as_1m && i != L1I_MEM && i != L1D_MEM) {
 397 #ifdef CONFIG_MTD_UCLINUX
 398                         if (i == SDRAM_RAM_MTD) {
 399                                 if ((cplb_data[SDRAM_KERN].end + 1) > cplb_data[SDRAM_RAM_MTD].start)
 400                                         cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M)) + SIZE_1M;
 401                                 else
 402                                         cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M));
 403                         } else
 404 #endif
 405                                 printk(KERN_WARNING "Unaligned Start of %s at 0x%X\n",
 406                                        cplb_data[i].name, cplb_data[i].start);
 407                 }
 408
 409                 as = cplb_data[i].start % SIZE_4M;
 410                 ae = cplb_data[i].end % SIZE_4M;
 411
 412                 if (as)
 413                         a_start = cplb_data[i].start + (SIZE_4M - (as));
 414                 else
 415                         a_start = cplb_data[i].start;
 416
 417                 a_end = cplb_data[i].end - ae;
 418
 419                 for (j = INITIAL_T; j <= SWITCH_T; j++) {
 420
 421                         switch (j) {
 422                         case INITIAL_T:
 423                                 if (cplb_data[i].attr & INITIAL_T) {
 424                                         t_i = &cplb.init_i;
 425                                         t_d = &cplb.init_d;
 426                                         process = 1;
 427                                 } else
 428                                         process = 0;
 429                                 break;
 430                         case SWITCH_T:
 431                                 if (cplb_data[i].attr & SWITCH_T) {
 432                                         t_i = &cplb.switch_i;
 433                                         t_d = &cplb.switch_d;
 434                                         process = 1;
 435                                 } else
 436                                         process = 0;
 437                                 break;
 438                         default:
 439                                         process = 0;
 440                                 break;
 441                         }
 442
 443                         if (!process)
 444                                 continue;
 445                         if (cplb_data[i].attr & I_CPLB)
 446                                 __fill_code_cplbtab(t_i, i, a_start, a_end);
 447
 448                         if (cplb_data[i].attr & D_CPLB)
 449                                 __fill_data_cplbtab(t_d, i, a_start, a_end);
 450                 }
 451         }
 452
 453 /* close tables */
 454
 455         close_cplbtab(&cplb.init_i);
 456         close_cplbtab(&cplb.init_d);
 457
 458         cplb.init_i.tab[cplb.init_i.pos] = -1;
 459         cplb.init_d.tab[cplb.init_d.pos] = -1;
 460         cplb.switch_i.tab[cplb.switch_i.pos] = -1;
 461         cplb.switch_d.tab[cplb.switch_d.pos] = -1;
 462
 463 }
 464
 465 #endif
 466