arch/blackfin/include/mach-common/pll.h

   1 /*
   2  * Copyright 2005-2010 Analog Devices Inc.
   3  *
   4  * Licensed under the GPL-2 or later.
   5  */
   6
   7 #ifndef _MACH_COMMON_PLL_H
   8 #define _MACH_COMMON_PLL_H
   9
  10 #ifndef __ASSEMBLY__
  11
  12 #include <asm/blackfin.h>
  13 #include <asm/irqflags.h>
  14
  15 #ifndef bfin_iwr_restore
  16 static inline void
  17 bfin_iwr_restore(unsigned long iwr0, unsigned long iwr1, unsigned long iwr2)
  18 {
  19 #ifdef SIC_IWR
  20         bfin_write_SIC_IWR(iwr0);
  21 #else
  22         bfin_write_SIC_IWR0(iwr0);
  23 # ifdef SIC_IWR1
  24         bfin_write_SIC_IWR1(iwr1);
  25 # endif
  26 # ifdef SIC_IWR2
  27         bfin_write_SIC_IWR2(iwr2);
  28 # endif
  29 #endif
  30 }
  31 #endif
  32
  33 #ifndef bfin_iwr_save
  34 static inline void
  35 bfin_iwr_save(unsigned long niwr0, unsigned long niwr1, unsigned long niwr2,
  36               unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2)
  37 {
  38 #ifdef SIC_IWR
  39         *iwr0 = bfin_read_SIC_IWR();
  40 #else
  41         *iwr0 = bfin_read_SIC_IWR0();
  42 # ifdef SIC_IWR1
  43         *iwr1 = bfin_read_SIC_IWR1();
  44 # endif
  45 # ifdef SIC_IWR2
  46         *iwr2 = bfin_read_SIC_IWR2();
  47 # endif
  48 #endif
  49         bfin_iwr_restore(niwr0, niwr1, niwr2);
  50 }
  51 #endif
  52
  53 static inline void _bfin_write_pll_relock(u32 addr, unsigned int val)
  54 {
  55         unsigned long flags, iwr0, iwr1, iwr2;
  56
  57         if (val == bfin_read_PLL_CTL())
  58                 return;
  59
  60         flags = hard_local_irq_save();
  61         /* Enable the PLL Wakeup bit in SIC IWR */
  62         bfin_iwr_save(IWR_ENABLE(0), 0, 0, &iwr0, &iwr1, &iwr2);
  63
  64         bfin_write16(addr, val);
  65         SSYNC();
  66         asm("IDLE;");
  67
  68         bfin_iwr_restore(iwr0, iwr1, iwr2);
  69         hard_local_irq_restore(flags);
  70 }
  71
  72 /* Writing to PLL_CTL initiates a PLL relock sequence */
  73 static inline void bfin_write_PLL_CTL(unsigned int val)
  74 {
  75         _bfin_write_pll_relock(PLL_CTL, val);
  76 }
  77
  78 /* Writing to VR_CTL initiates a PLL relock sequence */
  79 static inline void bfin_write_VR_CTL(unsigned int val)
  80 {
  81         _bfin_write_pll_relock(VR_CTL, val);
  82 }
  83
  84 #endif
  85
  86 #endif