arch/blackfin/include/asm/cplb.h

   1 /*
   2  * File:         include/asm-blackfin/cplb.h
   3  * Based on:     include/asm-blackfin/mach-bf537/bf537.h
   4  * Author:       Robin Getz <rgetz@blackfin.uclinux.org>
   5  *
   6  * Created:      2000
   7  * Description:  Common CPLB definitions for CPLB init
   8  *
   9  * Modified:
  10  *               Copyright 2004-2007 Analog Devices Inc.
  11  *
  12  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License as published by
  16  * the Free Software Foundation; either version 2 of the License, or
  17  * (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, see the file COPYING, or write
  26  * to the Free Software Foundation, Inc.,
  27  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  28  */
  29
  30 #ifndef _CPLB_H
  31 #define _CPLB_H
  32
  33 #include <asm/blackfin.h>
  34 #include <mach/anomaly.h>
  35
  36 #define SDRAM_IGENERIC    (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
  37 #define SDRAM_IKERNEL     (SDRAM_IGENERIC | CPLB_LOCK)
  38 #define L1_IMEMORY        (               CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
  39 #define SDRAM_INON_CHBL   (               CPLB_USER_RD | CPLB_VALID)
  40
  41 /*Use the menuconfig cache policy here - CONFIG_BFIN_WT/CONFIG_BFIN_WB*/
  42
  43 #if ANOMALY_05000158
  44 #define ANOMALY_05000158_WORKAROUND             0x200
  45 #else
  46 #define ANOMALY_05000158_WORKAROUND             0x0
  47 #endif
  48
  49 #define CPLB_COMMON     (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
  50
  51 #ifdef CONFIG_BFIN_WB         /*Write Back Policy */
  52 #define SDRAM_DGENERIC   (CPLB_L1_CHBL | CPLB_COMMON)
  53 #else                           /*Write Through */
  54 #define SDRAM_DGENERIC   (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW  | CPLB_COMMON)
  55 #endif
  56
  57 #define L1_DMEMORY       (CPLB_LOCK | CPLB_COMMON)
  58 #ifdef CONFIG_BFIN_L2_CACHEABLE
  59 #define L2_IMEMORY        (SDRAM_IGENERIC)
  60 #define L2_DMEMORY        (SDRAM_DGENERIC)
  61 #else
  62 #define L2_IMEMORY        (CPLB_COMMON)
  63 #define L2_DMEMORY        (CPLB_COMMON)
  64 #endif
  65 #define SDRAM_DNON_CHBL  (CPLB_COMMON)
  66 #define SDRAM_EBIU       (CPLB_COMMON)
  67 #define SDRAM_OOPS       (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
  68
  69 #define SIZE_1K 0x00000400      /* 1K */
  70 #define SIZE_4K 0x00001000      /* 4K */
  71 #define SIZE_1M 0x00100000      /* 1M */
  72 #define SIZE_4M 0x00400000      /* 4M */
  73
  74 #ifdef CONFIG_MPU
  75 #define MAX_CPLBS 16
  76 #else
  77 #define MAX_CPLBS (16 * 2)
  78 #endif
  79
  80 #define ASYNC_MEMORY_CPLB_COVERAGE      ((ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \
  81                                  ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) / SIZE_4M)
  82
  83 #define CPLB_ENABLE_ICACHE_P    0
  84 #define CPLB_ENABLE_DCACHE_P    1
  85 #define CPLB_ENABLE_DCACHE2_P   2
  86 #define CPLB_ENABLE_CPLBS_P     3       /* Deprecated! */
  87 #define CPLB_ENABLE_ICPLBS_P    4
  88 #define CPLB_ENABLE_DCPLBS_P    5
  89
  90 #define CPLB_ENABLE_ICACHE      (1<<CPLB_ENABLE_ICACHE_P)
  91 #define CPLB_ENABLE_DCACHE      (1<<CPLB_ENABLE_DCACHE_P)
  92 #define CPLB_ENABLE_DCACHE2     (1<<CPLB_ENABLE_DCACHE2_P)
  93 #define CPLB_ENABLE_CPLBS       (1<<CPLB_ENABLE_CPLBS_P)
  94 #define CPLB_ENABLE_ICPLBS      (1<<CPLB_ENABLE_ICPLBS_P)
  95 #define CPLB_ENABLE_DCPLBS      (1<<CPLB_ENABLE_DCPLBS_P)
  96 #define CPLB_ENABLE_ANY_CPLBS   CPLB_ENABLE_CPLBS | \
  97                                 CPLB_ENABLE_ICPLBS | \
  98                                 CPLB_ENABLE_DCPLBS
  99
 100 #define CPLB_RELOADED           0x0000
 101 #define CPLB_NO_UNLOCKED        0x0001
 102 #define CPLB_NO_ADDR_MATCH      0x0002
 103 #define CPLB_PROT_VIOL          0x0003
 104 #define CPLB_UNKNOWN_ERR        0x0004
 105
 106 #define CPLB_DEF_CACHE          CPLB_L1_CHBL | CPLB_WT
 107 #define CPLB_CACHE_ENABLED      CPLB_L1_CHBL | CPLB_DIRTY
 108
 109 #define CPLB_I_PAGE_MGMT        CPLB_LOCK | CPLB_VALID
 110 #define CPLB_D_PAGE_MGMT        CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
 111 #define CPLB_DNOCACHE           CPLB_ALL_ACCESS | CPLB_VALID
 112 #define CPLB_DDOCACHE           CPLB_DNOCACHE | CPLB_DEF_CACHE
 113 #define CPLB_INOCACHE           CPLB_USER_RD | CPLB_VALID
 114 #define CPLB_IDOCACHE           CPLB_INOCACHE | CPLB_L1_CHBL
 115
 116 #endif                          /* _CPLB_H */