arch/avr32/mach-at32ap/at32ap700x.c

   1 /*
   2  * Copyright (C) 2005-2006 Atmel Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 #include <linux/clk.h>
   9 #include <linux/delay.h>
  10 #include <linux/fb.h>
  11 #include <linux/init.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/spi/spi.h>
  15 #include <linux/usb/atmel_usba_udc.h>
  16
  17 #include <asm/io.h>
  18 #include <asm/irq.h>
  19
  20 #include <asm/arch/at32ap700x.h>
  21 #include <asm/arch/board.h>
  22 #include <asm/arch/portmux.h>
  23
  24 #include <video/atmel_lcdc.h>
  25
  26 #include "clock.h"
  27 #include "hmatrix.h"
  28 #include "pio.h"
  29 #include "pm.h"
  30
  31
  32 #define PBMEM(base)                                     \
  33         {                                               \
  34                 .start          = base,                 \
  35                 .end            = base + 0x3ff,         \
  36                 .flags          = IORESOURCE_MEM,       \
  37         }
  38 #define IRQ(num)                                        \
  39         {                                               \
  40                 .start          = num,                  \
  41                 .end            = num,                  \
  42                 .flags          = IORESOURCE_IRQ,       \
  43         }
  44 #define NAMED_IRQ(num, _name)                           \
  45         {                                               \
  46                 .start          = num,                  \
  47                 .end            = num,                  \
  48                 .name           = _name,                \
  49                 .flags          = IORESOURCE_IRQ,       \
  50         }
  51
  52 /* REVISIT these assume *every* device supports DMA, but several
  53  * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
  54  */
  55 #define DEFINE_DEV(_name, _id)                                  \
  56 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK;              \
  57 static struct platform_device _name##_id##_device = {           \
  58         .name           = #_name,                               \
  59         .id             = _id,                                  \
  60         .dev            = {                                     \
  61                 .dma_mask = &_name##_id##_dma_mask,             \
  62                 .coherent_dma_mask = DMA_32BIT_MASK,            \
  63         },                                                      \
  64         .resource       = _name##_id##_resource,                \
  65         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
  66 }
  67 #define DEFINE_DEV_DATA(_name, _id)                             \
  68 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK;              \
  69 static struct platform_device _name##_id##_device = {           \
  70         .name           = #_name,                               \
  71         .id             = _id,                                  \
  72         .dev            = {                                     \
  73                 .dma_mask = &_name##_id##_dma_mask,             \
  74                 .platform_data  = &_name##_id##_data,           \
  75                 .coherent_dma_mask = DMA_32BIT_MASK,            \
  76         },                                                      \
  77         .resource       = _name##_id##_resource,                \
  78         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
  79 }
  80
  81 #define select_peripheral(pin, periph, flags)                   \
  82         at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags)
  83
  84 #define DEV_CLK(_name, devname, bus, _index)                    \
  85 static struct clk devname##_##_name = {                         \
  86         .name           = #_name,                               \
  87         .dev            = &devname##_device.dev,                \
  88         .parent         = &bus##_clk,                           \
  89         .mode           = bus##_clk_mode,                       \
  90         .get_rate       = bus##_clk_get_rate,                   \
  91         .index          = _index,                               \
  92 }
  93
  94 static DEFINE_SPINLOCK(pm_lock);
  95
  96 unsigned long at32ap7000_osc_rates[3] = {
  97         [0] = 32768,
  98         /* FIXME: these are ATSTK1002-specific */
  99         [1] = 20000000,
 100         [2] = 12000000,
 101 };
 102
 103 static struct clk osc0;
 104 static struct clk osc1;
 105
 106 static unsigned long osc_get_rate(struct clk *clk)
 107 {
 108         return at32ap7000_osc_rates[clk->index];
 109 }
 110
 111 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
 112 {
 113         unsigned long div, mul, rate;
 114
 115         div = PM_BFEXT(PLLDIV, control) + 1;
 116         mul = PM_BFEXT(PLLMUL, control) + 1;
 117
 118         rate = clk->parent->get_rate(clk->parent);
 119         rate = (rate + div / 2) / div;
 120         rate *= mul;
 121
 122         return rate;
 123 }
 124
 125 static long pll_set_rate(struct clk *clk, unsigned long rate,
 126                          u32 *pll_ctrl)
 127 {
 128         unsigned long mul;
 129         unsigned long mul_best_fit = 0;
 130         unsigned long div;
 131         unsigned long div_min;
 132         unsigned long div_max;
 133         unsigned long div_best_fit = 0;
 134         unsigned long base;
 135         unsigned long pll_in;
 136         unsigned long actual = 0;
 137         unsigned long rate_error;
 138         unsigned long rate_error_prev = ~0UL;
 139         u32 ctrl;
 140
 141         /* Rate must be between 80 MHz and 200 Mhz. */
 142         if (rate < 80000000UL || rate > 200000000UL)
 143                 return -EINVAL;
 144
 145         ctrl = PM_BF(PLLOPT, 4);
 146         base = clk->parent->get_rate(clk->parent);
 147
 148         /* PLL input frequency must be between 6 MHz and 32 MHz. */
 149         div_min = DIV_ROUND_UP(base, 32000000UL);
 150         div_max = base / 6000000UL;
 151
 152         if (div_max < div_min)
 153                 return -EINVAL;
 154
 155         for (div = div_min; div <= div_max; div++) {
 156                 pll_in = (base + div / 2) / div;
 157                 mul = (rate + pll_in / 2) / pll_in;
 158
 159                 if (mul == 0)
 160                         continue;
 161
 162                 actual = pll_in * mul;
 163                 rate_error = abs(actual - rate);
 164
 165                 if (rate_error < rate_error_prev) {
 166                         mul_best_fit = mul;
 167                         div_best_fit = div;
 168                         rate_error_prev = rate_error;
 169                 }
 170
 171                 if (rate_error == 0)
 172                         break;
 173         }
 174
 175         if (div_best_fit == 0)
 176                 return -EINVAL;
 177
 178         ctrl |= PM_BF(PLLMUL, mul_best_fit - 1);
 179         ctrl |= PM_BF(PLLDIV, div_best_fit - 1);
 180         ctrl |= PM_BF(PLLCOUNT, 16);
 181
 182         if (clk->parent == &osc1)
 183                 ctrl |= PM_BIT(PLLOSC);
 184
 185         *pll_ctrl = ctrl;
 186
 187         return actual;
 188 }
 189
 190 static unsigned long pll0_get_rate(struct clk *clk)
 191 {
 192         u32 control;
 193
 194         control = pm_readl(PLL0);
 195
 196         return pll_get_rate(clk, control);
 197 }
 198
 199 static void pll1_mode(struct clk *clk, int enabled)
 200 {
 201         unsigned long timeout;
 202         u32 status;
 203         u32 ctrl;
 204
 205         ctrl = pm_readl(PLL1);
 206
 207         if (enabled) {
 208                 if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) {
 209                         pr_debug("clk %s: failed to enable, rate not set\n",
 210                                         clk->name);
 211                         return;
 212                 }
 213
 214                 ctrl |= PM_BIT(PLLEN);
 215                 pm_writel(PLL1, ctrl);
 216
 217                 /* Wait for PLL lock. */
 218                 for (timeout = 10000; timeout; timeout--) {
 219                         status = pm_readl(ISR);
 220                         if (status & PM_BIT(LOCK1))
 221                                 break;
 222                         udelay(10);
 223                 }
 224
 225                 if (!(status & PM_BIT(LOCK1)))
 226                         printk(KERN_ERR "clk %s: timeout waiting for lock\n",
 227                                         clk->name);
 228         } else {
 229                 ctrl &= ~PM_BIT(PLLEN);
 230                 pm_writel(PLL1, ctrl);
 231         }
 232 }
 233
 234 static unsigned long pll1_get_rate(struct clk *clk)
 235 {
 236         u32 control;
 237
 238         control = pm_readl(PLL1);
 239
 240         return pll_get_rate(clk, control);
 241 }
 242
 243 static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply)
 244 {
 245         u32 ctrl = 0;
 246         unsigned long actual_rate;
 247
 248         actual_rate = pll_set_rate(clk, rate, &ctrl);
 249
 250         if (apply) {
 251                 if (actual_rate != rate)
 252                         return -EINVAL;
 253                 if (clk->users > 0)
 254                         return -EBUSY;
 255                 pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
 256                                 clk->name, rate, actual_rate);
 257                 pm_writel(PLL1, ctrl);
 258         }
 259
 260         return actual_rate;
 261 }
 262
 263 static int pll1_set_parent(struct clk *clk, struct clk *parent)
 264 {
 265         u32 ctrl;
 266
 267         if (clk->users > 0)
 268                 return -EBUSY;
 269
 270         ctrl = pm_readl(PLL1);
 271         WARN_ON(ctrl & PM_BIT(PLLEN));
 272
 273         if (parent == &osc0)
 274                 ctrl &= ~PM_BIT(PLLOSC);
 275         else if (parent == &osc1)
 276                 ctrl |= PM_BIT(PLLOSC);
 277         else
 278                 return -EINVAL;
 279
 280         pm_writel(PLL1, ctrl);
 281         clk->parent = parent;
 282
 283         return 0;
 284 }
 285
 286 /*
 287  * The AT32AP7000 has five primary clock sources: One 32kHz
 288  * oscillator, two crystal oscillators and two PLLs.
 289  */
 290 static struct clk osc32k = {
 291         .name           = "osc32k",
 292         .get_rate       = osc_get_rate,
 293         .users          = 1,
 294         .index          = 0,
 295 };
 296 static struct clk osc0 = {
 297         .name           = "osc0",
 298         .get_rate       = osc_get_rate,
 299         .users          = 1,
 300         .index          = 1,
 301 };
 302 static struct clk osc1 = {
 303         .name           = "osc1",
 304         .get_rate       = osc_get_rate,
 305         .index          = 2,
 306 };
 307 static struct clk pll0 = {
 308         .name           = "pll0",
 309         .get_rate       = pll0_get_rate,
 310         .parent         = &osc0,
 311 };
 312 static struct clk pll1 = {
 313         .name           = "pll1",
 314         .mode           = pll1_mode,
 315         .get_rate       = pll1_get_rate,
 316         .set_rate       = pll1_set_rate,
 317         .set_parent     = pll1_set_parent,
 318         .parent         = &osc0,
 319 };
 320
 321 /*
 322  * The main clock can be either osc0 or pll0.  The boot loader may
 323  * have chosen one for us, so we don't really know which one until we
 324  * have a look at the SM.
 325  */
 326 static struct clk *main_clock;
 327
 328 /*
 329  * Synchronous clocks are generated from the main clock. The clocks
 330  * must satisfy the constraint
 331  *   fCPU >= fHSB >= fPB
 332  * i.e. each clock must not be faster than its parent.
 333  */
 334 static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
 335 {
 336         return main_clock->get_rate(main_clock) >> shift;
 337 };
 338
 339 static void cpu_clk_mode(struct clk *clk, int enabled)
 340 {
 341         unsigned long flags;
 342         u32 mask;
 343
 344         spin_lock_irqsave(&pm_lock, flags);
 345         mask = pm_readl(CPU_MASK);
 346         if (enabled)
 347                 mask |= 1 << clk->index;
 348         else
 349                 mask &= ~(1 << clk->index);
 350         pm_writel(CPU_MASK, mask);
 351         spin_unlock_irqrestore(&pm_lock, flags);
 352 }
 353
 354 static unsigned long cpu_clk_get_rate(struct clk *clk)
 355 {
 356         unsigned long cksel, shift = 0;
 357
 358         cksel = pm_readl(CKSEL);
 359         if (cksel & PM_BIT(CPUDIV))
 360                 shift = PM_BFEXT(CPUSEL, cksel) + 1;
 361
 362         return bus_clk_get_rate(clk, shift);
 363 }
 364
 365 static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
 366 {
 367         u32 control;
 368         unsigned long parent_rate, child_div, actual_rate, div;
 369
 370         parent_rate = clk->parent->get_rate(clk->parent);
 371         control = pm_readl(CKSEL);
 372
 373         if (control & PM_BIT(HSBDIV))
 374                 child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
 375         else
 376                 child_div = 1;
 377
 378         if (rate > 3 * (parent_rate / 4) || child_div == 1) {
 379                 actual_rate = parent_rate;
 380                 control &= ~PM_BIT(CPUDIV);
 381         } else {
 382                 unsigned int cpusel;
 383                 div = (parent_rate + rate / 2) / rate;
 384                 if (div > child_div)
 385                         div = child_div;
 386                 cpusel = (div > 1) ? (fls(div) - 2) : 0;
 387                 control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
 388                 actual_rate = parent_rate / (1 << (cpusel + 1));
 389         }
 390
 391         pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
 392                         clk->name, rate, actual_rate);
 393
 394         if (apply)
 395                 pm_writel(CKSEL, control);
 396
 397         return actual_rate;
 398 }
 399
 400 static void hsb_clk_mode(struct clk *clk, int enabled)
 401 {
 402         unsigned long flags;
 403         u32 mask;
 404
 405         spin_lock_irqsave(&pm_lock, flags);
 406         mask = pm_readl(HSB_MASK);
 407         if (enabled)
 408                 mask |= 1 << clk->index;
 409         else
 410                 mask &= ~(1 << clk->index);
 411         pm_writel(HSB_MASK, mask);
 412         spin_unlock_irqrestore(&pm_lock, flags);
 413 }
 414
 415 static unsigned long hsb_clk_get_rate(struct clk *clk)
 416 {
 417         unsigned long cksel, shift = 0;
 418
 419         cksel = pm_readl(CKSEL);
 420         if (cksel & PM_BIT(HSBDIV))
 421                 shift = PM_BFEXT(HSBSEL, cksel) + 1;
 422
 423         return bus_clk_get_rate(clk, shift);
 424 }
 425
 426 static void pba_clk_mode(struct clk *clk, int enabled)
 427 {
 428         unsigned long flags;
 429         u32 mask;
 430
 431         spin_lock_irqsave(&pm_lock, flags);
 432         mask = pm_readl(PBA_MASK);
 433         if (enabled)
 434                 mask |= 1 << clk->index;
 435         else
 436                 mask &= ~(1 << clk->index);
 437         pm_writel(PBA_MASK, mask);
 438         spin_unlock_irqrestore(&pm_lock, flags);
 439 }
 440
 441 static unsigned long pba_clk_get_rate(struct clk *clk)
 442 {
 443         unsigned long cksel, shift = 0;
 444
 445         cksel = pm_readl(CKSEL);
 446         if (cksel & PM_BIT(PBADIV))
 447                 shift = PM_BFEXT(PBASEL, cksel) + 1;
 448
 449         return bus_clk_get_rate(clk, shift);
 450 }
 451
 452 static void pbb_clk_mode(struct clk *clk, int enabled)
 453 {
 454         unsigned long flags;
 455         u32 mask;
 456
 457         spin_lock_irqsave(&pm_lock, flags);
 458         mask = pm_readl(PBB_MASK);
 459         if (enabled)
 460                 mask |= 1 << clk->index;
 461         else
 462                 mask &= ~(1 << clk->index);
 463         pm_writel(PBB_MASK, mask);
 464         spin_unlock_irqrestore(&pm_lock, flags);
 465 }
 466
 467 static unsigned long pbb_clk_get_rate(struct clk *clk)
 468 {
 469         unsigned long cksel, shift = 0;
 470
 471         cksel = pm_readl(CKSEL);
 472         if (cksel & PM_BIT(PBBDIV))
 473                 shift = PM_BFEXT(PBBSEL, cksel) + 1;
 474
 475         return bus_clk_get_rate(clk, shift);
 476 }
 477
 478 static struct clk cpu_clk = {
 479         .name           = "cpu",
 480         .get_rate       = cpu_clk_get_rate,
 481         .set_rate       = cpu_clk_set_rate,
 482         .users          = 1,
 483 };
 484 static struct clk hsb_clk = {
 485         .name           = "hsb",
 486         .parent         = &cpu_clk,
 487         .get_rate       = hsb_clk_get_rate,
 488 };
 489 static struct clk pba_clk = {
 490         .name           = "pba",
 491         .parent         = &hsb_clk,
 492         .mode           = hsb_clk_mode,
 493         .get_rate       = pba_clk_get_rate,
 494         .index          = 1,
 495 };
 496 static struct clk pbb_clk = {
 497         .name           = "pbb",
 498         .parent         = &hsb_clk,
 499         .mode           = hsb_clk_mode,
 500         .get_rate       = pbb_clk_get_rate,
 501         .users          = 1,
 502         .index          = 2,
 503 };
 504
 505 /* --------------------------------------------------------------------
 506  *  Generic Clock operations
 507  * -------------------------------------------------------------------- */
 508
 509 static void genclk_mode(struct clk *clk, int enabled)
 510 {
 511         u32 control;
 512
 513         control = pm_readl(GCCTRL(clk->index));
 514         if (enabled)
 515                 control |= PM_BIT(CEN);
 516         else
 517                 control &= ~PM_BIT(CEN);
 518         pm_writel(GCCTRL(clk->index), control);
 519 }
 520
 521 static unsigned long genclk_get_rate(struct clk *clk)
 522 {
 523         u32 control;
 524         unsigned long div = 1;
 525
 526         control = pm_readl(GCCTRL(clk->index));
 527         if (control & PM_BIT(DIVEN))
 528                 div = 2 * (PM_BFEXT(DIV, control) + 1);
 529
 530         return clk->parent->get_rate(clk->parent) / div;
 531 }
 532
 533 static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
 534 {
 535         u32 control;
 536         unsigned long parent_rate, actual_rate, div;
 537
 538         parent_rate = clk->parent->get_rate(clk->parent);
 539         control = pm_readl(GCCTRL(clk->index));
 540
 541         if (rate > 3 * parent_rate / 4) {
 542                 actual_rate = parent_rate;
 543                 control &= ~PM_BIT(DIVEN);
 544         } else {
 545                 div = (parent_rate + rate) / (2 * rate) - 1;
 546                 control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
 547                 actual_rate = parent_rate / (2 * (div + 1));
 548         }
 549
 550         dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
 551                 clk->name, rate, actual_rate);
 552
 553         if (apply)
 554                 pm_writel(GCCTRL(clk->index), control);
 555
 556         return actual_rate;
 557 }
 558
 559 int genclk_set_parent(struct clk *clk, struct clk *parent)
 560 {
 561         u32 control;
 562
 563         dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
 564                 clk->name, parent->name, clk->parent->name);
 565
 566         control = pm_readl(GCCTRL(clk->index));
 567
 568         if (parent == &osc1 || parent == &pll1)
 569                 control |= PM_BIT(OSCSEL);
 570         else if (parent == &osc0 || parent == &pll0)
 571                 control &= ~PM_BIT(OSCSEL);
 572         else
 573                 return -EINVAL;
 574
 575         if (parent == &pll0 || parent == &pll1)
 576                 control |= PM_BIT(PLLSEL);
 577         else
 578                 control &= ~PM_BIT(PLLSEL);
 579
 580         pm_writel(GCCTRL(clk->index), control);
 581         clk->parent = parent;
 582
 583         return 0;
 584 }
 585
 586 static void __init genclk_init_parent(struct clk *clk)
 587 {
 588         u32 control;
 589         struct clk *parent;
 590
 591         BUG_ON(clk->index > 7);
 592
 593         control = pm_readl(GCCTRL(clk->index));
 594         if (control & PM_BIT(OSCSEL))
 595                 parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
 596         else
 597                 parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
 598
 599         clk->parent = parent;
 600 }
 601
 602 /* --------------------------------------------------------------------
 603  *  System peripherals
 604  * -------------------------------------------------------------------- */
 605 static struct resource at32_pm0_resource[] = {
 606         {
 607                 .start  = 0xfff00000,
 608                 .end    = 0xfff0007f,
 609                 .flags  = IORESOURCE_MEM,
 610         },
 611         IRQ(20),
 612 };
 613
 614 static struct resource at32ap700x_rtc0_resource[] = {
 615         {
 616                 .start  = 0xfff00080,
 617                 .end    = 0xfff000af,
 618                 .flags  = IORESOURCE_MEM,
 619         },
 620         IRQ(21),
 621 };
 622
 623 static struct resource at32_wdt0_resource[] = {
 624         {
 625                 .start  = 0xfff000b0,
 626                 .end    = 0xfff000cf,
 627                 .flags  = IORESOURCE_MEM,
 628         },
 629 };
 630
 631 static struct resource at32_eic0_resource[] = {
 632         {
 633                 .start  = 0xfff00100,
 634                 .end    = 0xfff0013f,
 635                 .flags  = IORESOURCE_MEM,
 636         },
 637         IRQ(19),
 638 };
 639
 640 DEFINE_DEV(at32_pm, 0);
 641 DEFINE_DEV(at32ap700x_rtc, 0);
 642 DEFINE_DEV(at32_wdt, 0);
 643 DEFINE_DEV(at32_eic, 0);
 644
 645 /*
 646  * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
 647  * is always running.
 648  */
 649 static struct clk at32_pm_pclk = {
 650         .name           = "pclk",
 651         .dev            = &at32_pm0_device.dev,
 652         .parent         = &pbb_clk,
 653         .mode           = pbb_clk_mode,
 654         .get_rate       = pbb_clk_get_rate,
 655         .users          = 1,
 656         .index          = 0,
 657 };
 658
 659 static struct resource intc0_resource[] = {
 660         PBMEM(0xfff00400),
 661 };
 662 struct platform_device at32_intc0_device = {
 663         .name           = "intc",
 664         .id             = 0,
 665         .resource       = intc0_resource,
 666         .num_resources  = ARRAY_SIZE(intc0_resource),
 667 };
 668 DEV_CLK(pclk, at32_intc0, pbb, 1);
 669
 670 static struct clk ebi_clk = {
 671         .name           = "ebi",
 672         .parent         = &hsb_clk,
 673         .mode           = hsb_clk_mode,
 674         .get_rate       = hsb_clk_get_rate,
 675         .users          = 1,
 676 };
 677 static struct clk hramc_clk = {
 678         .name           = "hramc",
 679         .parent         = &hsb_clk,
 680         .mode           = hsb_clk_mode,
 681         .get_rate       = hsb_clk_get_rate,
 682         .users          = 1,
 683         .index          = 3,
 684 };
 685
 686 static struct resource smc0_resource[] = {
 687         PBMEM(0xfff03400),
 688 };
 689 DEFINE_DEV(smc, 0);
 690 DEV_CLK(pclk, smc0, pbb, 13);
 691 DEV_CLK(mck, smc0, hsb, 0);
 692
 693 static struct platform_device pdc_device = {
 694         .name           = "pdc",
 695         .id             = 0,
 696 };
 697 DEV_CLK(hclk, pdc, hsb, 4);
 698 DEV_CLK(pclk, pdc, pba, 16);
 699
 700 static struct clk pico_clk = {
 701         .name           = "pico",
 702         .parent         = &cpu_clk,
 703         .mode           = cpu_clk_mode,
 704         .get_rate       = cpu_clk_get_rate,
 705         .users          = 1,
 706 };
 707
 708 static struct resource dmaca0_resource[] = {
 709         {
 710                 .start  = 0xff200000,
 711                 .end    = 0xff20ffff,
 712                 .flags  = IORESOURCE_MEM,
 713         },
 714         IRQ(2),
 715 };
 716 DEFINE_DEV(dmaca, 0);
 717 DEV_CLK(hclk, dmaca0, hsb, 10);
 718
 719 /* --------------------------------------------------------------------
 720  * HMATRIX
 721  * -------------------------------------------------------------------- */
 722
 723 static struct clk hmatrix_clk = {
 724         .name           = "hmatrix_clk",
 725         .parent         = &pbb_clk,
 726         .mode           = pbb_clk_mode,
 727         .get_rate       = pbb_clk_get_rate,
 728         .index          = 2,
 729         .users          = 1,
 730 };
 731 #define HMATRIX_BASE    ((void __iomem *)0xfff00800)
 732
 733 #define hmatrix_readl(reg)                                      \
 734         __raw_readl((HMATRIX_BASE) + HMATRIX_##reg)
 735 #define hmatrix_writel(reg,value)                               \
 736         __raw_writel((value), (HMATRIX_BASE) + HMATRIX_##reg)
 737
 738 /*
 739  * Set bits in the HMATRIX Special Function Register (SFR) used by the
 740  * External Bus Interface (EBI). This can be used to enable special
 741  * features like CompactFlash support, NAND Flash support, etc. on
 742  * certain chipselects.
 743  */
 744 static inline void set_ebi_sfr_bits(u32 mask)
 745 {
 746         u32 sfr;
 747
 748         clk_enable(&hmatrix_clk);
 749         sfr = hmatrix_readl(SFR4);
 750         sfr |= mask;
 751         hmatrix_writel(SFR4, sfr);
 752         clk_disable(&hmatrix_clk);
 753 }
 754
 755 /* --------------------------------------------------------------------
 756  *  Timer/Counter (TC)
 757  * -------------------------------------------------------------------- */
 758
 759 static struct resource at32_tcb0_resource[] = {
 760         PBMEM(0xfff00c00),
 761         IRQ(22),
 762 };
 763 static struct platform_device at32_tcb0_device = {
 764         .name           = "atmel_tcb",
 765         .id             = 0,
 766         .resource       = at32_tcb0_resource,
 767         .num_resources  = ARRAY_SIZE(at32_tcb0_resource),
 768 };
 769 DEV_CLK(t0_clk, at32_tcb0, pbb, 3);
 770
 771 static struct resource at32_tcb1_resource[] = {
 772         PBMEM(0xfff01000),
 773         IRQ(23),
 774 };
 775 static struct platform_device at32_tcb1_device = {
 776         .name           = "atmel_tcb",
 777         .id             = 1,
 778         .resource       = at32_tcb1_resource,
 779         .num_resources  = ARRAY_SIZE(at32_tcb1_resource),
 780 };
 781 DEV_CLK(t0_clk, at32_tcb1, pbb, 4);
 782
 783 /* --------------------------------------------------------------------
 784  *  PIO
 785  * -------------------------------------------------------------------- */
 786
 787 static struct resource pio0_resource[] = {
 788         PBMEM(0xffe02800),
 789         IRQ(13),
 790 };
 791 DEFINE_DEV(pio, 0);
 792 DEV_CLK(mck, pio0, pba, 10);
 793
 794 static struct resource pio1_resource[] = {
 795         PBMEM(0xffe02c00),
 796         IRQ(14),
 797 };
 798 DEFINE_DEV(pio, 1);
 799 DEV_CLK(mck, pio1, pba, 11);
 800
 801 static struct resource pio2_resource[] = {
 802         PBMEM(0xffe03000),
 803         IRQ(15),
 804 };
 805 DEFINE_DEV(pio, 2);
 806 DEV_CLK(mck, pio2, pba, 12);
 807
 808 static struct resource pio3_resource[] = {
 809         PBMEM(0xffe03400),
 810         IRQ(16),
 811 };
 812 DEFINE_DEV(pio, 3);
 813 DEV_CLK(mck, pio3, pba, 13);
 814
 815 static struct resource pio4_resource[] = {
 816         PBMEM(0xffe03800),
 817         IRQ(17),
 818 };
 819 DEFINE_DEV(pio, 4);
 820 DEV_CLK(mck, pio4, pba, 14);
 821
 822 void __init at32_add_system_devices(void)
 823 {
 824         platform_device_register(&at32_pm0_device);
 825         platform_device_register(&at32_intc0_device);
 826         platform_device_register(&at32ap700x_rtc0_device);
 827         platform_device_register(&at32_wdt0_device);
 828         platform_device_register(&at32_eic0_device);
 829         platform_device_register(&smc0_device);
 830         platform_device_register(&pdc_device);
 831         platform_device_register(&dmaca0_device);
 832
 833         platform_device_register(&at32_tcb0_device);
 834         platform_device_register(&at32_tcb1_device);
 835
 836         platform_device_register(&pio0_device);
 837         platform_device_register(&pio1_device);
 838         platform_device_register(&pio2_device);
 839         platform_device_register(&pio3_device);
 840         platform_device_register(&pio4_device);
 841 }
 842
 843 /* --------------------------------------------------------------------
 844  *  USART
 845  * -------------------------------------------------------------------- */
 846
 847 static struct atmel_uart_data atmel_usart0_data = {
 848         .use_dma_tx     = 1,
 849         .use_dma_rx     = 1,
 850 };
 851 static struct resource atmel_usart0_resource[] = {
 852         PBMEM(0xffe00c00),
 853         IRQ(6),
 854 };
 855 DEFINE_DEV_DATA(atmel_usart, 0);
 856 DEV_CLK(usart, atmel_usart0, pba, 3);
 857
 858 static struct atmel_uart_data atmel_usart1_data = {
 859         .use_dma_tx     = 1,
 860         .use_dma_rx     = 1,
 861 };
 862 static struct resource atmel_usart1_resource[] = {
 863         PBMEM(0xffe01000),
 864         IRQ(7),
 865 };
 866 DEFINE_DEV_DATA(atmel_usart, 1);
 867 DEV_CLK(usart, atmel_usart1, pba, 4);
 868
 869 static struct atmel_uart_data atmel_usart2_data = {
 870         .use_dma_tx     = 1,
 871         .use_dma_rx     = 1,
 872 };
 873 static struct resource atmel_usart2_resource[] = {
 874         PBMEM(0xffe01400),
 875         IRQ(8),
 876 };
 877 DEFINE_DEV_DATA(atmel_usart, 2);
 878 DEV_CLK(usart, atmel_usart2, pba, 5);
 879
 880 static struct atmel_uart_data atmel_usart3_data = {
 881         .use_dma_tx     = 1,
 882         .use_dma_rx     = 1,
 883 };
 884 static struct resource atmel_usart3_resource[] = {
 885         PBMEM(0xffe01800),
 886         IRQ(9),
 887 };
 888 DEFINE_DEV_DATA(atmel_usart, 3);
 889 DEV_CLK(usart, atmel_usart3, pba, 6);
 890
 891 static inline void configure_usart0_pins(void)
 892 {
 893         select_peripheral(PA(8),  PERIPH_B, 0); /* RXD  */
 894         select_peripheral(PA(9),  PERIPH_B, 0); /* TXD  */
 895 }
 896
 897 static inline void configure_usart1_pins(void)
 898 {
 899         select_peripheral(PA(17), PERIPH_A, 0); /* RXD  */
 900         select_peripheral(PA(18), PERIPH_A, 0); /* TXD  */
 901 }
 902
 903 static inline void configure_usart2_pins(void)
 904 {
 905         select_peripheral(PB(26), PERIPH_B, 0); /* RXD  */
 906         select_peripheral(PB(27), PERIPH_B, 0); /* TXD  */
 907 }
 908
 909 static inline void configure_usart3_pins(void)
 910 {
 911         select_peripheral(PB(18), PERIPH_B, 0); /* RXD  */
 912         select_peripheral(PB(17), PERIPH_B, 0); /* TXD  */
 913 }
 914
 915 static struct platform_device *__initdata at32_usarts[4];
 916
 917 void __init at32_map_usart(unsigned int hw_id, unsigned int line)
 918 {
 919         struct platform_device *pdev;
 920
 921         switch (hw_id) {
 922         case 0:
 923                 pdev = &atmel_usart0_device;
 924                 configure_usart0_pins();
 925                 break;
 926         case 1:
 927                 pdev = &atmel_usart1_device;
 928                 configure_usart1_pins();
 929                 break;
 930         case 2:
 931                 pdev = &atmel_usart2_device;
 932                 configure_usart2_pins();
 933                 break;
 934         case 3:
 935                 pdev = &atmel_usart3_device;
 936                 configure_usart3_pins();
 937                 break;
 938         default:
 939                 return;
 940         }
 941
 942         if (PXSEG(pdev->resource[0].start) == P4SEG) {
 943                 /* Addresses in the P4 segment are permanently mapped 1:1 */
 944                 struct atmel_uart_data *data = pdev->dev.platform_data;
 945                 data->regs = (void __iomem *)pdev->resource[0].start;
 946         }
 947
 948         pdev->id = line;
 949         at32_usarts[line] = pdev;
 950 }
 951
 952 struct platform_device *__init at32_add_device_usart(unsigned int id)
 953 {
 954         platform_device_register(at32_usarts[id]);
 955         return at32_usarts[id];
 956 }
 957
 958 struct platform_device *atmel_default_console_device;
 959
 960 void __init at32_setup_serial_console(unsigned int usart_id)
 961 {
 962         atmel_default_console_device = at32_usarts[usart_id];
 963 }
 964
 965 /* --------------------------------------------------------------------
 966  *  Ethernet
 967  * -------------------------------------------------------------------- */
 968
 969 #ifdef CONFIG_CPU_AT32AP7000
 970 static struct eth_platform_data macb0_data;
 971 static struct resource macb0_resource[] = {
 972         PBMEM(0xfff01800),
 973         IRQ(25),
 974 };
 975 DEFINE_DEV_DATA(macb, 0);
 976 DEV_CLK(hclk, macb0, hsb, 8);
 977 DEV_CLK(pclk, macb0, pbb, 6);
 978
 979 static struct eth_platform_data macb1_data;
 980 static struct resource macb1_resource[] = {
 981         PBMEM(0xfff01c00),
 982         IRQ(26),
 983 };
 984 DEFINE_DEV_DATA(macb, 1);
 985 DEV_CLK(hclk, macb1, hsb, 9);
 986 DEV_CLK(pclk, macb1, pbb, 7);
 987
 988 struct platform_device *__init
 989 at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
 990 {
 991         struct platform_device *pdev;
 992
 993         switch (id) {
 994         case 0:
 995                 pdev = &macb0_device;
 996
 997                 select_peripheral(PC(3),  PERIPH_A, 0); /* TXD0 */
 998                 select_peripheral(PC(4),  PERIPH_A, 0); /* TXD1 */
 999                 select_peripheral(PC(7),  PERIPH_A, 0); /* TXEN */
1000                 select_peripheral(PC(8),  PERIPH_A, 0); /* TXCK */
1001                 select_peripheral(PC(9),  PERIPH_A, 0); /* RXD0 */
1002                 select_peripheral(PC(10), PERIPH_A, 0); /* RXD1 */
1003                 select_peripheral(PC(13), PERIPH_A, 0); /* RXER */
1004                 select_peripheral(PC(15), PERIPH_A, 0); /* RXDV */
1005                 select_peripheral(PC(16), PERIPH_A, 0); /* MDC  */
1006                 select_peripheral(PC(17), PERIPH_A, 0); /* MDIO */
1007
1008                 if (!data->is_rmii) {
1009                         select_peripheral(PC(0),  PERIPH_A, 0); /* COL  */
1010                         select_peripheral(PC(1),  PERIPH_A, 0); /* CRS  */
1011                         select_peripheral(PC(2),  PERIPH_A, 0); /* TXER */
1012                         select_peripheral(PC(5),  PERIPH_A, 0); /* TXD2 */
1013                         select_peripheral(PC(6),  PERIPH_A, 0); /* TXD3 */
1014                         select_peripheral(PC(11), PERIPH_A, 0); /* RXD2 */
1015                         select_peripheral(PC(12), PERIPH_A, 0); /* RXD3 */
1016                         select_peripheral(PC(14), PERIPH_A, 0); /* RXCK */
1017                         select_peripheral(PC(18), PERIPH_A, 0); /* SPD  */
1018                 }
1019                 break;
1020
1021         case 1:
1022                 pdev = &macb1_device;
1023
1024                 select_peripheral(PD(13), PERIPH_B, 0);         /* TXD0 */
1025                 select_peripheral(PD(14), PERIPH_B, 0);         /* TXD1 */
1026                 select_peripheral(PD(11), PERIPH_B, 0);         /* TXEN */
1027                 select_peripheral(PD(12), PERIPH_B, 0);         /* TXCK */
1028                 select_peripheral(PD(10), PERIPH_B, 0);         /* RXD0 */
1029                 select_peripheral(PD(6),  PERIPH_B, 0);         /* RXD1 */
1030                 select_peripheral(PD(5),  PERIPH_B, 0);         /* RXER */
1031                 select_peripheral(PD(4),  PERIPH_B, 0);         /* RXDV */
1032                 select_peripheral(PD(3),  PERIPH_B, 0);         /* MDC  */
1033                 select_peripheral(PD(2),  PERIPH_B, 0);         /* MDIO */
1034
1035                 if (!data->is_rmii) {
1036                         select_peripheral(PC(19), PERIPH_B, 0); /* COL  */
1037                         select_peripheral(PC(23), PERIPH_B, 0); /* CRS  */
1038                         select_peripheral(PC(26), PERIPH_B, 0); /* TXER */
1039                         select_peripheral(PC(27), PERIPH_B, 0); /* TXD2 */
1040                         select_peripheral(PC(28), PERIPH_B, 0); /* TXD3 */
1041                         select_peripheral(PC(29), PERIPH_B, 0); /* RXD2 */
1042                         select_peripheral(PC(30), PERIPH_B, 0); /* RXD3 */
1043                         select_peripheral(PC(24), PERIPH_B, 0); /* RXCK */
1044                         select_peripheral(PD(15), PERIPH_B, 0); /* SPD  */
1045                 }
1046                 break;
1047
1048         default:
1049                 return NULL;
1050         }
1051
1052         memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
1053         platform_device_register(pdev);
1054
1055         return pdev;
1056 }
1057 #endif
1058
1059 /* --------------------------------------------------------------------
1060  *  SPI
1061  * -------------------------------------------------------------------- */
1062 static struct resource atmel_spi0_resource[] = {
1063         PBMEM(0xffe00000),
1064         IRQ(3),
1065 };
1066 DEFINE_DEV(atmel_spi, 0);
1067 DEV_CLK(spi_clk, atmel_spi0, pba, 0);
1068
1069 static struct resource atmel_spi1_resource[] = {
1070         PBMEM(0xffe00400),
1071         IRQ(4),
1072 };
1073 DEFINE_DEV(atmel_spi, 1);
1074 DEV_CLK(spi_clk, atmel_spi1, pba, 1);
1075
1076 static void __init
1077 at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
1078                       unsigned int n, const u8 *pins)
1079 {
1080         unsigned int pin, mode;
1081
1082         for (; n; n--, b++) {
1083                 b->bus_num = bus_num;
1084                 if (b->chip_select >= 4)
1085                         continue;
1086                 pin = (unsigned)b->controller_data;
1087                 if (!pin) {
1088                         pin = pins[b->chip_select];
1089                         b->controller_data = (void *)pin;
1090                 }
1091                 mode = AT32_GPIOF_OUTPUT;
1092                 if (!(b->mode & SPI_CS_HIGH))
1093                         mode |= AT32_GPIOF_HIGH;
1094                 at32_select_gpio(pin, mode);
1095         }
1096 }
1097
1098 struct platform_device *__init
1099 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
1100 {
1101         /*
1102          * Manage the chipselects as GPIOs, normally using the same pins
1103          * the SPI controller expects; but boards can use other pins.
1104          */
1105         static u8 __initdata spi0_pins[] =
1106                 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
1107                   GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
1108         static u8 __initdata spi1_pins[] =
1109                 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
1110                   GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
1111         struct platform_device *pdev;
1112
1113         switch (id) {
1114         case 0:
1115                 pdev = &atmel_spi0_device;
1116                 select_peripheral(PA(0),  PERIPH_A, 0); /* MISO  */
1117                 select_peripheral(PA(1),  PERIPH_A, 0); /* MOSI  */
1118                 select_peripheral(PA(2),  PERIPH_A, 0); /* SCK   */
1119                 at32_spi_setup_slaves(0, b, n, spi0_pins);
1120                 break;
1121
1122         case 1:
1123                 pdev = &atmel_spi1_device;
1124                 select_peripheral(PB(0),  PERIPH_B, 0); /* MISO  */
1125                 select_peripheral(PB(1),  PERIPH_B, 0); /* MOSI  */
1126                 select_peripheral(PB(5),  PERIPH_B, 0); /* SCK   */
1127                 at32_spi_setup_slaves(1, b, n, spi1_pins);
1128                 break;
1129
1130         default:
1131                 return NULL;
1132         }
1133
1134         spi_register_board_info(b, n);
1135         platform_device_register(pdev);
1136         return pdev;
1137 }
1138
1139 /* --------------------------------------------------------------------
1140  *  TWI
1141  * -------------------------------------------------------------------- */
1142 static struct resource atmel_twi0_resource[] __initdata = {
1143         PBMEM(0xffe00800),
1144         IRQ(5),
1145 };
1146 static struct clk atmel_twi0_pclk = {
1147         .name           = "twi_pclk",
1148         .parent         = &pba_clk,
1149         .mode           = pba_clk_mode,
1150         .get_rate       = pba_clk_get_rate,
1151         .index          = 2,
1152 };
1153
1154 struct platform_device *__init at32_add_device_twi(unsigned int id,
1155                                                     struct i2c_board_info *b,
1156                                                     unsigned int n)
1157 {
1158         struct platform_device *pdev;
1159
1160         if (id != 0)
1161                 return NULL;
1162
1163         pdev = platform_device_alloc("atmel_twi", id);
1164         if (!pdev)
1165                 return NULL;
1166
1167         if (platform_device_add_resources(pdev, atmel_twi0_resource,
1168                                 ARRAY_SIZE(atmel_twi0_resource)))
1169                 goto err_add_resources;
1170
1171         select_peripheral(PA(6),  PERIPH_A, 0); /* SDA  */
1172         select_peripheral(PA(7),  PERIPH_A, 0); /* SDL  */
1173
1174         atmel_twi0_pclk.dev = &pdev->dev;
1175
1176         if (b)
1177                 i2c_register_board_info(id, b, n);
1178
1179         platform_device_add(pdev);
1180         return pdev;
1181
1182 err_add_resources:
1183         platform_device_put(pdev);
1184         return NULL;
1185 }
1186
1187 /* --------------------------------------------------------------------
1188  * MMC
1189  * -------------------------------------------------------------------- */
1190 static struct resource atmel_mci0_resource[] __initdata = {
1191         PBMEM(0xfff02400),
1192         IRQ(28),
1193 };
1194 static struct clk atmel_mci0_pclk = {
1195         .name           = "mci_clk",
1196         .parent         = &pbb_clk,
1197         .mode           = pbb_clk_mode,
1198         .get_rate       = pbb_clk_get_rate,
1199         .index          = 9,
1200 };
1201
1202 struct platform_device *__init at32_add_device_mci(unsigned int id)
1203 {
1204         struct platform_device *pdev;
1205
1206         if (id != 0)
1207                 return NULL;
1208
1209         pdev = platform_device_alloc("atmel_mci", id);
1210         if (!pdev)
1211                 return NULL;
1212
1213         if (platform_device_add_resources(pdev, atmel_mci0_resource,
1214                                 ARRAY_SIZE(atmel_mci0_resource)))
1215                 goto err_add_resources;
1216
1217         select_peripheral(PA(10), PERIPH_A, 0); /* CLK   */
1218         select_peripheral(PA(11), PERIPH_A, 0); /* CMD   */
1219         select_peripheral(PA(12), PERIPH_A, 0); /* DATA0 */
1220         select_peripheral(PA(13), PERIPH_A, 0); /* DATA1 */
1221         select_peripheral(PA(14), PERIPH_A, 0); /* DATA2 */
1222         select_peripheral(PA(15), PERIPH_A, 0); /* DATA3 */
1223
1224         atmel_mci0_pclk.dev = &pdev->dev;
1225
1226         platform_device_add(pdev);
1227         return pdev;
1228
1229 err_add_resources:
1230         platform_device_put(pdev);
1231         return NULL;
1232 }
1233
1234 /* --------------------------------------------------------------------
1235  *  LCDC
1236  * -------------------------------------------------------------------- */
1237 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1238 static struct atmel_lcdfb_info atmel_lcdfb0_data;
1239 static struct resource atmel_lcdfb0_resource[] = {
1240         {
1241                 .start          = 0xff000000,
1242                 .end            = 0xff000fff,
1243                 .flags          = IORESOURCE_MEM,
1244         },
1245         IRQ(1),
1246         {
1247                 /* Placeholder for pre-allocated fb memory */
1248                 .start          = 0x00000000,
1249                 .end            = 0x00000000,
1250                 .flags          = 0,
1251         },
1252 };
1253 DEFINE_DEV_DATA(atmel_lcdfb, 0);
1254 DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
1255 static struct clk atmel_lcdfb0_pixclk = {
1256         .name           = "lcdc_clk",
1257         .dev            = &atmel_lcdfb0_device.dev,
1258         .mode           = genclk_mode,
1259         .get_rate       = genclk_get_rate,
1260         .set_rate       = genclk_set_rate,
1261         .set_parent     = genclk_set_parent,
1262         .index          = 7,
1263 };
1264
1265 struct platform_device *__init
1266 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
1267                      unsigned long fbmem_start, unsigned long fbmem_len)
1268 {
1269         struct platform_device *pdev;
1270         struct atmel_lcdfb_info *info;
1271         struct fb_monspecs *monspecs;
1272         struct fb_videomode *modedb;
1273         unsigned int modedb_size;
1274
1275         /*
1276          * Do a deep copy of the fb data, monspecs and modedb. Make
1277          * sure all allocations are done before setting up the
1278          * portmux.
1279          */
1280         monspecs = kmemdup(data->default_monspecs,
1281                            sizeof(struct fb_monspecs), GFP_KERNEL);
1282         if (!monspecs)
1283                 return NULL;
1284
1285         modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
1286         modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
1287         if (!modedb)
1288                 goto err_dup_modedb;
1289         monspecs->modedb = modedb;
1290
1291         switch (id) {
1292         case 0:
1293                 pdev = &atmel_lcdfb0_device;
1294                 select_peripheral(PC(19), PERIPH_A, 0); /* CC     */
1295                 select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC  */
1296                 select_peripheral(PC(21), PERIPH_A, 0); /* PCLK   */
1297                 select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC  */
1298                 select_peripheral(PC(23), PERIPH_A, 0); /* DVAL   */
1299                 select_peripheral(PC(24), PERIPH_A, 0); /* MODE   */
1300                 select_peripheral(PC(25), PERIPH_A, 0); /* PWR    */
1301                 select_peripheral(PC(26), PERIPH_A, 0); /* DATA0  */
1302                 select_peripheral(PC(27), PERIPH_A, 0); /* DATA1  */
1303                 select_peripheral(PC(28), PERIPH_A, 0); /* DATA2  */
1304                 select_peripheral(PC(29), PERIPH_A, 0); /* DATA3  */
1305                 select_peripheral(PC(30), PERIPH_A, 0); /* DATA4  */
1306                 select_peripheral(PC(31), PERIPH_A, 0); /* DATA5  */
1307                 select_peripheral(PD(0),  PERIPH_A, 0); /* DATA6  */
1308                 select_peripheral(PD(1),  PERIPH_A, 0); /* DATA7  */
1309                 select_peripheral(PD(2),  PERIPH_A, 0); /* DATA8  */
1310                 select_peripheral(PD(3),  PERIPH_A, 0); /* DATA9  */
1311                 select_peripheral(PD(4),  PERIPH_A, 0); /* DATA10 */
1312                 select_peripheral(PD(5),  PERIPH_A, 0); /* DATA11 */
1313                 select_peripheral(PD(6),  PERIPH_A, 0); /* DATA12 */
1314                 select_peripheral(PD(7),  PERIPH_A, 0); /* DATA13 */
1315                 select_peripheral(PD(8),  PERIPH_A, 0); /* DATA14 */
1316                 select_peripheral(PD(9),  PERIPH_A, 0); /* DATA15 */
1317                 select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
1318                 select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
1319                 select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
1320                 select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
1321                 select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
1322                 select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
1323                 select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
1324                 select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
1325
1326                 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
1327                 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
1328                 break;
1329
1330         default:
1331                 goto err_invalid_id;
1332         }
1333
1334         if (fbmem_len) {
1335                 pdev->resource[2].start = fbmem_start;
1336                 pdev->resource[2].end = fbmem_start + fbmem_len - 1;
1337                 pdev->resource[2].flags = IORESOURCE_MEM;
1338         }
1339
1340         info = pdev->dev.platform_data;
1341         memcpy(info, data, sizeof(struct atmel_lcdfb_info));
1342         info->default_monspecs = monspecs;
1343
1344         platform_device_register(pdev);
1345         return pdev;
1346
1347 err_invalid_id:
1348         kfree(modedb);
1349 err_dup_modedb:
1350         kfree(monspecs);
1351         return NULL;
1352 }
1353 #endif
1354
1355 /* --------------------------------------------------------------------
1356  *  PWM
1357  * -------------------------------------------------------------------- */
1358 static struct resource atmel_pwm0_resource[] __initdata = {
1359         PBMEM(0xfff01400),
1360         IRQ(24),
1361 };
1362 static struct clk atmel_pwm0_mck = {
1363         .name           = "mck",
1364         .parent         = &pbb_clk,
1365         .mode           = pbb_clk_mode,
1366         .get_rate       = pbb_clk_get_rate,
1367         .index          = 5,
1368 };
1369
1370 struct platform_device *__init at32_add_device_pwm(u32 mask)
1371 {
1372         struct platform_device *pdev;
1373
1374         if (!mask)
1375                 return NULL;
1376
1377         pdev = platform_device_alloc("atmel_pwm", 0);
1378         if (!pdev)
1379                 return NULL;
1380
1381         if (platform_device_add_resources(pdev, atmel_pwm0_resource,
1382                                 ARRAY_SIZE(atmel_pwm0_resource)))
1383                 goto out_free_pdev;
1384
1385         if (platform_device_add_data(pdev, &mask, sizeof(mask)))
1386                 goto out_free_pdev;
1387
1388         if (mask & (1 << 0))
1389                 select_peripheral(PA(28), PERIPH_A, 0);
1390         if (mask & (1 << 1))
1391                 select_peripheral(PA(29), PERIPH_A, 0);
1392         if (mask & (1 << 2))
1393                 select_peripheral(PA(21), PERIPH_B, 0);
1394         if (mask & (1 << 3))
1395                 select_peripheral(PA(22), PERIPH_B, 0);
1396
1397         atmel_pwm0_mck.dev = &pdev->dev;
1398
1399         platform_device_add(pdev);
1400
1401         return pdev;
1402
1403 out_free_pdev:
1404         platform_device_put(pdev);
1405         return NULL;
1406 }
1407
1408 /* --------------------------------------------------------------------
1409  *  SSC
1410  * -------------------------------------------------------------------- */
1411 static struct resource ssc0_resource[] = {
1412         PBMEM(0xffe01c00),
1413         IRQ(10),
1414 };
1415 DEFINE_DEV(ssc, 0);
1416 DEV_CLK(pclk, ssc0, pba, 7);
1417
1418 static struct resource ssc1_resource[] = {
1419         PBMEM(0xffe02000),
1420         IRQ(11),
1421 };
1422 DEFINE_DEV(ssc, 1);
1423 DEV_CLK(pclk, ssc1, pba, 8);
1424
1425 static struct resource ssc2_resource[] = {
1426         PBMEM(0xffe02400),
1427         IRQ(12),
1428 };
1429 DEFINE_DEV(ssc, 2);
1430 DEV_CLK(pclk, ssc2, pba, 9);
1431
1432 struct platform_device *__init
1433 at32_add_device_ssc(unsigned int id, unsigned int flags)
1434 {
1435         struct platform_device *pdev;
1436
1437         switch (id) {
1438         case 0:
1439                 pdev = &ssc0_device;
1440                 if (flags & ATMEL_SSC_RF)
1441                         select_peripheral(PA(21), PERIPH_A, 0); /* RF */
1442                 if (flags & ATMEL_SSC_RK)
1443                         select_peripheral(PA(22), PERIPH_A, 0); /* RK */
1444                 if (flags & ATMEL_SSC_TK)
1445                         select_peripheral(PA(23), PERIPH_A, 0); /* TK */
1446                 if (flags & ATMEL_SSC_TF)
1447                         select_peripheral(PA(24), PERIPH_A, 0); /* TF */
1448                 if (flags & ATMEL_SSC_TD)
1449                         select_peripheral(PA(25), PERIPH_A, 0); /* TD */
1450                 if (flags & ATMEL_SSC_RD)
1451                         select_peripheral(PA(26), PERIPH_A, 0); /* RD */
1452                 break;
1453         case 1:
1454                 pdev = &ssc1_device;
1455                 if (flags & ATMEL_SSC_RF)
1456                         select_peripheral(PA(0), PERIPH_B, 0);  /* RF */
1457                 if (flags & ATMEL_SSC_RK)
1458                         select_peripheral(PA(1), PERIPH_B, 0);  /* RK */
1459                 if (flags & ATMEL_SSC_TK)
1460                         select_peripheral(PA(2), PERIPH_B, 0);  /* TK */
1461                 if (flags & ATMEL_SSC_TF)
1462                         select_peripheral(PA(3), PERIPH_B, 0);  /* TF */
1463                 if (flags & ATMEL_SSC_TD)
1464                         select_peripheral(PA(4), PERIPH_B, 0);  /* TD */
1465                 if (flags & ATMEL_SSC_RD)
1466                         select_peripheral(PA(5), PERIPH_B, 0);  /* RD */
1467                 break;
1468         case 2:
1469                 pdev = &ssc2_device;
1470                 if (flags & ATMEL_SSC_TD)
1471                         select_peripheral(PB(13), PERIPH_A, 0); /* TD */
1472                 if (flags & ATMEL_SSC_RD)
1473                         select_peripheral(PB(14), PERIPH_A, 0); /* RD */
1474                 if (flags & ATMEL_SSC_TK)
1475                         select_peripheral(PB(15), PERIPH_A, 0); /* TK */
1476                 if (flags & ATMEL_SSC_TF)
1477                         select_peripheral(PB(16), PERIPH_A, 0); /* TF */
1478                 if (flags & ATMEL_SSC_RF)
1479                         select_peripheral(PB(17), PERIPH_A, 0); /* RF */
1480                 if (flags & ATMEL_SSC_RK)
1481                         select_peripheral(PB(18), PERIPH_A, 0); /* RK */
1482                 break;
1483         default:
1484                 return NULL;
1485         }
1486
1487         platform_device_register(pdev);
1488         return pdev;
1489 }
1490
1491 /* --------------------------------------------------------------------
1492  *  USB Device Controller
1493  * -------------------------------------------------------------------- */
1494 static struct resource usba0_resource[] __initdata = {
1495         {
1496                 .start          = 0xff300000,
1497                 .end            = 0xff3fffff,
1498                 .flags          = IORESOURCE_MEM,
1499         }, {
1500                 .start          = 0xfff03000,
1501                 .end            = 0xfff033ff,
1502                 .flags          = IORESOURCE_MEM,
1503         },
1504         IRQ(31),
1505 };
1506 static struct clk usba0_pclk = {
1507         .name           = "pclk",
1508         .parent         = &pbb_clk,
1509         .mode           = pbb_clk_mode,
1510         .get_rate       = pbb_clk_get_rate,
1511         .index          = 12,
1512 };
1513 static struct clk usba0_hclk = {
1514         .name           = "hclk",
1515         .parent         = &hsb_clk,
1516         .mode           = hsb_clk_mode,
1517         .get_rate       = hsb_clk_get_rate,
1518         .index          = 6,
1519 };
1520
1521 #define EP(nam, idx, maxpkt, maxbk, dma, isoc)                  \
1522         [idx] = {                                               \
1523                 .name           = nam,                          \
1524                 .index          = idx,                          \
1525                 .fifo_size      = maxpkt,                       \
1526                 .nr_banks       = maxbk,                        \
1527                 .can_dma        = dma,                          \
1528                 .can_isoc       = isoc,                         \
1529         }
1530
1531 static struct usba_ep_data at32_usba_ep[] __initdata = {
1532         EP("ep0",     0,   64, 1, 0, 0),
1533         EP("ep1",     1,  512, 2, 1, 1),
1534         EP("ep2",     2,  512, 2, 1, 1),
1535         EP("ep3-int", 3,   64, 3, 1, 0),
1536         EP("ep4-int", 4,   64, 3, 1, 0),
1537         EP("ep5",     5, 1024, 3, 1, 1),
1538         EP("ep6",     6, 1024, 3, 1, 1),
1539 };
1540
1541 #undef EP
1542
1543 struct platform_device *__init
1544 at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
1545 {
1546         /*
1547          * pdata doesn't have room for any endpoints, so we need to
1548          * append room for the ones we need right after it.
1549          */
1550         struct {
1551                 struct usba_platform_data pdata;
1552                 struct usba_ep_data ep[7];
1553         } usba_data;
1554         struct platform_device *pdev;
1555
1556         if (id != 0)
1557                 return NULL;
1558
1559         pdev = platform_device_alloc("atmel_usba_udc", 0);
1560         if (!pdev)
1561                 return NULL;
1562
1563         if (platform_device_add_resources(pdev, usba0_resource,
1564                                           ARRAY_SIZE(usba0_resource)))
1565                 goto out_free_pdev;
1566
1567         if (data)
1568                 usba_data.pdata.vbus_pin = data->vbus_pin;
1569         else
1570                 usba_data.pdata.vbus_pin = -EINVAL;
1571
1572         data = &usba_data.pdata;
1573         data->num_ep = ARRAY_SIZE(at32_usba_ep);
1574         memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep));
1575
1576         if (platform_device_add_data(pdev, data, sizeof(usba_data)))
1577                 goto out_free_pdev;
1578
1579         if (data->vbus_pin >= 0)
1580                 at32_select_gpio(data->vbus_pin, 0);
1581
1582         usba0_pclk.dev = &pdev->dev;
1583         usba0_hclk.dev = &pdev->dev;
1584
1585         platform_device_add(pdev);
1586
1587         return pdev;
1588
1589 out_free_pdev:
1590         platform_device_put(pdev);
1591         return NULL;
1592 }
1593
1594 /* --------------------------------------------------------------------
1595  * IDE / CompactFlash
1596  * -------------------------------------------------------------------- */
1597 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001)
1598 static struct resource at32_smc_cs4_resource[] __initdata = {
1599         {
1600                 .start  = 0x04000000,
1601                 .end    = 0x07ffffff,
1602                 .flags  = IORESOURCE_MEM,
1603         },
1604         IRQ(~0UL), /* Magic IRQ will be overridden */
1605 };
1606 static struct resource at32_smc_cs5_resource[] __initdata = {
1607         {
1608                 .start  = 0x20000000,
1609                 .end    = 0x23ffffff,
1610                 .flags  = IORESOURCE_MEM,
1611         },
1612         IRQ(~0UL), /* Magic IRQ will be overridden */
1613 };
1614
1615 static int __init at32_init_ide_or_cf(struct platform_device *pdev,
1616                 unsigned int cs, unsigned int extint)
1617 {
1618         static unsigned int extint_pin_map[4] __initdata = {
1619                 GPIO_PIN_PB(25),
1620                 GPIO_PIN_PB(26),
1621                 GPIO_PIN_PB(27),
1622                 GPIO_PIN_PB(28),
1623         };
1624         static bool common_pins_initialized __initdata = false;
1625         unsigned int extint_pin;
1626         int ret;
1627
1628         if (extint >= ARRAY_SIZE(extint_pin_map))
1629                 return -EINVAL;
1630         extint_pin = extint_pin_map[extint];
1631
1632         switch (cs) {
1633         case 4:
1634                 ret = platform_device_add_resources(pdev,
1635                                 at32_smc_cs4_resource,
1636                                 ARRAY_SIZE(at32_smc_cs4_resource));
1637                 if (ret)
1638                         return ret;
1639
1640                 select_peripheral(PE(21), PERIPH_A, 0); /* NCS4   -> OE_N  */
1641                 set_ebi_sfr_bits(HMATRIX_BIT(CS4A));
1642                 break;
1643         case 5:
1644                 ret = platform_device_add_resources(pdev,
1645                                 at32_smc_cs5_resource,
1646                                 ARRAY_SIZE(at32_smc_cs5_resource));
1647                 if (ret)
1648                         return ret;
1649
1650                 select_peripheral(PE(22), PERIPH_A, 0); /* NCS5   -> OE_N  */
1651                 set_ebi_sfr_bits(HMATRIX_BIT(CS5A));
1652                 break;
1653         default:
1654                 return -EINVAL;
1655         }
1656
1657         if (!common_pins_initialized) {
1658                 select_peripheral(PE(19), PERIPH_A, 0); /* CFCE1  -> CS0_N */
1659                 select_peripheral(PE(20), PERIPH_A, 0); /* CFCE2  -> CS1_N */
1660                 select_peripheral(PE(23), PERIPH_A, 0); /* CFRNW  -> DIR   */
1661                 select_peripheral(PE(24), PERIPH_A, 0); /* NWAIT  <- IORDY */
1662                 common_pins_initialized = true;
1663         }
1664
1665         at32_select_periph(extint_pin, GPIO_PERIPH_A, AT32_GPIOF_DEGLITCH);
1666
1667         pdev->resource[1].start = EIM_IRQ_BASE + extint;
1668         pdev->resource[1].end = pdev->resource[1].start;
1669
1670         return 0;
1671 }
1672
1673 struct platform_device *__init
1674 at32_add_device_ide(unsigned int id, unsigned int extint,
1675                     struct ide_platform_data *data)
1676 {
1677         struct platform_device *pdev;
1678
1679         pdev = platform_device_alloc("at32_ide", id);
1680         if (!pdev)
1681                 goto fail;
1682
1683         if (platform_device_add_data(pdev, data,
1684                                 sizeof(struct ide_platform_data)))
1685                 goto fail;
1686
1687         if (at32_init_ide_or_cf(pdev, data->cs, extint))
1688                 goto fail;
1689
1690         platform_device_add(pdev);
1691         return pdev;
1692
1693 fail:
1694         platform_device_put(pdev);
1695         return NULL;
1696 }
1697
1698 struct platform_device *__init
1699 at32_add_device_cf(unsigned int id, unsigned int extint,
1700                     struct cf_platform_data *data)
1701 {
1702         struct platform_device *pdev;
1703
1704         pdev = platform_device_alloc("at32_cf", id);
1705         if (!pdev)
1706                 goto fail;
1707
1708         if (platform_device_add_data(pdev, data,
1709                                 sizeof(struct cf_platform_data)))
1710                 goto fail;
1711
1712         if (at32_init_ide_or_cf(pdev, data->cs, extint))
1713                 goto fail;
1714
1715         if (data->detect_pin != GPIO_PIN_NONE)
1716                 at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH);
1717         if (data->reset_pin != GPIO_PIN_NONE)
1718                 at32_select_gpio(data->reset_pin, 0);
1719         if (data->vcc_pin != GPIO_PIN_NONE)
1720                 at32_select_gpio(data->vcc_pin, 0);
1721         /* READY is used as extint, so we can't select it as gpio */
1722
1723         platform_device_add(pdev);
1724         return pdev;
1725
1726 fail:
1727         platform_device_put(pdev);
1728         return NULL;
1729 }
1730 #endif
1731
1732 /* --------------------------------------------------------------------
1733  * AC97C
1734  * -------------------------------------------------------------------- */
1735 static struct resource atmel_ac97c0_resource[] __initdata = {
1736         PBMEM(0xfff02800),
1737         IRQ(29),
1738 };
1739 static struct clk atmel_ac97c0_pclk = {
1740         .name           = "pclk",
1741         .parent         = &pbb_clk,
1742         .mode           = pbb_clk_mode,
1743         .get_rate       = pbb_clk_get_rate,
1744         .index          = 10,
1745 };
1746
1747 struct platform_device *__init at32_add_device_ac97c(unsigned int id)
1748 {
1749         struct platform_device *pdev;
1750
1751         if (id != 0)
1752                 return NULL;
1753
1754         pdev = platform_device_alloc("atmel_ac97c", id);
1755         if (!pdev)
1756                 return NULL;
1757
1758         if (platform_device_add_resources(pdev, atmel_ac97c0_resource,
1759                                 ARRAY_SIZE(atmel_ac97c0_resource)))
1760                 goto err_add_resources;
1761
1762         select_peripheral(PB(20), PERIPH_B, 0); /* SYNC */
1763         select_peripheral(PB(21), PERIPH_B, 0); /* SDO  */
1764         select_peripheral(PB(22), PERIPH_B, 0); /* SDI  */
1765         select_peripheral(PB(23), PERIPH_B, 0); /* SCLK */
1766
1767         atmel_ac97c0_pclk.dev = &pdev->dev;
1768
1769         platform_device_add(pdev);
1770         return pdev;
1771
1772 err_add_resources:
1773         platform_device_put(pdev);
1774         return NULL;
1775 }
1776
1777 /* --------------------------------------------------------------------
1778  * ABDAC
1779  * -------------------------------------------------------------------- */
1780 static struct resource abdac0_resource[] __initdata = {
1781         PBMEM(0xfff02000),
1782         IRQ(27),
1783 };
1784 static struct clk abdac0_pclk = {
1785         .name           = "pclk",
1786         .parent         = &pbb_clk,
1787         .mode           = pbb_clk_mode,
1788         .get_rate       = pbb_clk_get_rate,
1789         .index          = 8,
1790 };
1791 static struct clk abdac0_sample_clk = {
1792         .name           = "sample_clk",
1793         .mode           = genclk_mode,
1794         .get_rate       = genclk_get_rate,
1795         .set_rate       = genclk_set_rate,
1796         .set_parent     = genclk_set_parent,
1797         .index          = 6,
1798 };
1799
1800 struct platform_device *__init at32_add_device_abdac(unsigned int id)
1801 {
1802         struct platform_device *pdev;
1803
1804         if (id != 0)
1805                 return NULL;
1806
1807         pdev = platform_device_alloc("abdac", id);
1808         if (!pdev)
1809                 return NULL;
1810
1811         if (platform_device_add_resources(pdev, abdac0_resource,
1812                                 ARRAY_SIZE(abdac0_resource)))
1813                 goto err_add_resources;
1814
1815         select_peripheral(PB(20), PERIPH_A, 0); /* DATA1        */
1816         select_peripheral(PB(21), PERIPH_A, 0); /* DATA0        */
1817         select_peripheral(PB(22), PERIPH_A, 0); /* DATAN1       */
1818         select_peripheral(PB(23), PERIPH_A, 0); /* DATAN0       */
1819
1820         abdac0_pclk.dev = &pdev->dev;
1821         abdac0_sample_clk.dev = &pdev->dev;
1822
1823         platform_device_add(pdev);
1824         return pdev;
1825
1826 err_add_resources:
1827         platform_device_put(pdev);
1828         return NULL;
1829 }
1830
1831 /* --------------------------------------------------------------------
1832  *  GCLK
1833  * -------------------------------------------------------------------- */
1834 static struct clk gclk0 = {
1835         .name           = "gclk0",
1836         .mode           = genclk_mode,
1837         .get_rate       = genclk_get_rate,
1838         .set_rate       = genclk_set_rate,
1839         .set_parent     = genclk_set_parent,
1840         .index          = 0,
1841 };
1842 static struct clk gclk1 = {
1843         .name           = "gclk1",
1844         .mode           = genclk_mode,
1845         .get_rate       = genclk_get_rate,
1846         .set_rate       = genclk_set_rate,
1847         .set_parent     = genclk_set_parent,
1848         .index          = 1,
1849 };
1850 static struct clk gclk2 = {
1851         .name           = "gclk2",
1852         .mode           = genclk_mode,
1853         .get_rate       = genclk_get_rate,
1854         .set_rate       = genclk_set_rate,
1855         .set_parent     = genclk_set_parent,
1856         .index          = 2,
1857 };
1858 static struct clk gclk3 = {
1859         .name           = "gclk3",
1860         .mode           = genclk_mode,
1861         .get_rate       = genclk_get_rate,
1862         .set_rate       = genclk_set_rate,
1863         .set_parent     = genclk_set_parent,
1864         .index          = 3,
1865 };
1866 static struct clk gclk4 = {
1867         .name           = "gclk4",
1868         .mode           = genclk_mode,
1869         .get_rate       = genclk_get_rate,
1870         .set_rate       = genclk_set_rate,
1871         .set_parent     = genclk_set_parent,
1872         .index          = 4,
1873 };
1874
1875 struct clk *at32_clock_list[] = {
1876         &osc32k,
1877         &osc0,
1878         &osc1,
1879         &pll0,
1880         &pll1,
1881         &cpu_clk,
1882         &hsb_clk,
1883         &pba_clk,
1884         &pbb_clk,
1885         &at32_pm_pclk,
1886         &at32_intc0_pclk,
1887         &hmatrix_clk,
1888         &ebi_clk,
1889         &hramc_clk,
1890         &smc0_pclk,
1891         &smc0_mck,
1892         &pdc_hclk,
1893         &pdc_pclk,
1894         &dmaca0_hclk,
1895         &pico_clk,
1896         &pio0_mck,
1897         &pio1_mck,
1898         &pio2_mck,
1899         &pio3_mck,
1900         &pio4_mck,
1901         &at32_tcb0_t0_clk,
1902         &at32_tcb1_t0_clk,
1903         &atmel_usart0_usart,
1904         &atmel_usart1_usart,
1905         &atmel_usart2_usart,
1906         &atmel_usart3_usart,
1907         &atmel_pwm0_mck,
1908 #if defined(CONFIG_CPU_AT32AP7000)
1909         &macb0_hclk,
1910         &macb0_pclk,
1911         &macb1_hclk,
1912         &macb1_pclk,
1913 #endif
1914         &atmel_spi0_spi_clk,
1915         &atmel_spi1_spi_clk,
1916         &atmel_twi0_pclk,
1917         &atmel_mci0_pclk,
1918 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1919         &atmel_lcdfb0_hck1,
1920         &atmel_lcdfb0_pixclk,
1921 #endif
1922         &ssc0_pclk,
1923         &ssc1_pclk,
1924         &ssc2_pclk,
1925         &usba0_hclk,
1926         &usba0_pclk,
1927         &atmel_ac97c0_pclk,
1928         &abdac0_pclk,
1929         &abdac0_sample_clk,
1930         &gclk0,
1931         &gclk1,
1932         &gclk2,
1933         &gclk3,
1934         &gclk4,
1935 };
1936 unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
1937
1938 void __init at32_portmux_init(void)
1939 {
1940         at32_init_pio(&pio0_device);
1941         at32_init_pio(&pio1_device);
1942         at32_init_pio(&pio2_device);
1943         at32_init_pio(&pio3_device);
1944         at32_init_pio(&pio4_device);
1945 }
1946
1947 void __init at32_clock_init(void)
1948 {
1949         u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
1950         int i;
1951
1952         if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
1953                 main_clock = &pll0;
1954                 cpu_clk.parent = &pll0;
1955         } else {
1956                 main_clock = &osc0;
1957                 cpu_clk.parent = &osc0;
1958         }
1959
1960         if (pm_readl(PLL0) & PM_BIT(PLLOSC))
1961                 pll0.parent = &osc1;
1962         if (pm_readl(PLL1) & PM_BIT(PLLOSC))
1963                 pll1.parent = &osc1;
1964
1965         genclk_init_parent(&gclk0);
1966         genclk_init_parent(&gclk1);
1967         genclk_init_parent(&gclk2);
1968         genclk_init_parent(&gclk3);
1969         genclk_init_parent(&gclk4);
1970 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1971         genclk_init_parent(&atmel_lcdfb0_pixclk);
1972 #endif
1973         genclk_init_parent(&abdac0_sample_clk);
1974
1975         /*
1976          * Turn on all clocks that have at least one user already, and
1977          * turn off everything else. We only do this for module
1978          * clocks, and even though it isn't particularly pretty to
1979          * check the address of the mode function, it should do the
1980          * trick...
1981          */
1982         for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) {
1983                 struct clk *clk = at32_clock_list[i];
1984
1985                 if (clk->users == 0)
1986                         continue;
1987
1988                 if (clk->mode == &cpu_clk_mode)
1989                         cpu_mask |= 1 << clk->index;
1990                 else if (clk->mode == &hsb_clk_mode)
1991                         hsb_mask |= 1 << clk->index;
1992                 else if (clk->mode == &pba_clk_mode)
1993                         pba_mask |= 1 << clk->index;
1994                 else if (clk->mode == &pbb_clk_mode)
1995                         pbb_mask |= 1 << clk->index;
1996         }
1997
1998         pm_writel(CPU_MASK, cpu_mask);
1999         pm_writel(HSB_MASK, hsb_mask);
2000         pm_writel(PBA_MASK, pba_mask);
2001         pm_writel(PBB_MASK, pbb_mask);
2002 }