arch/avr32/mach-at32ap/at32ap700x.c

   1 /*
   2  * Copyright (C) 2005-2006 Atmel Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 #include <linux/clk.h>
   9 #include <linux/delay.h>
  10 #include <linux/fb.h>
  11 #include <linux/init.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/spi/spi.h>
  15 #include <linux/usb/atmel_usba_udc.h>
  16
  17 #include <asm/io.h>
  18 #include <asm/irq.h>
  19
  20 #include <asm/arch/at32ap700x.h>
  21 #include <asm/arch/board.h>
  22 #include <asm/arch/portmux.h>
  23 #include <asm/arch/sram.h>
  24
  25 #include <video/atmel_lcdc.h>
  26
  27 #include "clock.h"
  28 #include "hmatrix.h"
  29 #include "pio.h"
  30 #include "pm.h"
  31
  32
  33 #define PBMEM(base)                                     \
  34         {                                               \
  35                 .start          = base,                 \
  36                 .end            = base + 0x3ff,         \
  37                 .flags          = IORESOURCE_MEM,       \
  38         }
  39 #define IRQ(num)                                        \
  40         {                                               \
  41                 .start          = num,                  \
  42                 .end            = num,                  \
  43                 .flags          = IORESOURCE_IRQ,       \
  44         }
  45 #define NAMED_IRQ(num, _name)                           \
  46         {                                               \
  47                 .start          = num,                  \
  48                 .end            = num,                  \
  49                 .name           = _name,                \
  50                 .flags          = IORESOURCE_IRQ,       \
  51         }
  52
  53 /* REVISIT these assume *every* device supports DMA, but several
  54  * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
  55  */
  56 #define DEFINE_DEV(_name, _id)                                  \
  57 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK;              \
  58 static struct platform_device _name##_id##_device = {           \
  59         .name           = #_name,                               \
  60         .id             = _id,                                  \
  61         .dev            = {                                     \
  62                 .dma_mask = &_name##_id##_dma_mask,             \
  63                 .coherent_dma_mask = DMA_32BIT_MASK,            \
  64         },                                                      \
  65         .resource       = _name##_id##_resource,                \
  66         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
  67 }
  68 #define DEFINE_DEV_DATA(_name, _id)                             \
  69 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK;              \
  70 static struct platform_device _name##_id##_device = {           \
  71         .name           = #_name,                               \
  72         .id             = _id,                                  \
  73         .dev            = {                                     \
  74                 .dma_mask = &_name##_id##_dma_mask,             \
  75                 .platform_data  = &_name##_id##_data,           \
  76                 .coherent_dma_mask = DMA_32BIT_MASK,            \
  77         },                                                      \
  78         .resource       = _name##_id##_resource,                \
  79         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
  80 }
  81
  82 #define select_peripheral(pin, periph, flags)                   \
  83         at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags)
  84
  85 #define DEV_CLK(_name, devname, bus, _index)                    \
  86 static struct clk devname##_##_name = {                         \
  87         .name           = #_name,                               \
  88         .dev            = &devname##_device.dev,                \
  89         .parent         = &bus##_clk,                           \
  90         .mode           = bus##_clk_mode,                       \
  91         .get_rate       = bus##_clk_get_rate,                   \
  92         .index          = _index,                               \
  93 }
  94
  95 static DEFINE_SPINLOCK(pm_lock);
  96
  97 static struct clk osc0;
  98 static struct clk osc1;
  99
 100 static unsigned long osc_get_rate(struct clk *clk)
 101 {
 102         return at32_board_osc_rates[clk->index];
 103 }
 104
 105 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
 106 {
 107         unsigned long div, mul, rate;
 108
 109         div = PM_BFEXT(PLLDIV, control) + 1;
 110         mul = PM_BFEXT(PLLMUL, control) + 1;
 111
 112         rate = clk->parent->get_rate(clk->parent);
 113         rate = (rate + div / 2) / div;
 114         rate *= mul;
 115
 116         return rate;
 117 }
 118
 119 static long pll_set_rate(struct clk *clk, unsigned long rate,
 120                          u32 *pll_ctrl)
 121 {
 122         unsigned long mul;
 123         unsigned long mul_best_fit = 0;
 124         unsigned long div;
 125         unsigned long div_min;
 126         unsigned long div_max;
 127         unsigned long div_best_fit = 0;
 128         unsigned long base;
 129         unsigned long pll_in;
 130         unsigned long actual = 0;
 131         unsigned long rate_error;
 132         unsigned long rate_error_prev = ~0UL;
 133         u32 ctrl;
 134
 135         /* Rate must be between 80 MHz and 200 Mhz. */
 136         if (rate < 80000000UL || rate > 200000000UL)
 137                 return -EINVAL;
 138
 139         ctrl = PM_BF(PLLOPT, 4);
 140         base = clk->parent->get_rate(clk->parent);
 141
 142         /* PLL input frequency must be between 6 MHz and 32 MHz. */
 143         div_min = DIV_ROUND_UP(base, 32000000UL);
 144         div_max = base / 6000000UL;
 145
 146         if (div_max < div_min)
 147                 return -EINVAL;
 148
 149         for (div = div_min; div <= div_max; div++) {
 150                 pll_in = (base + div / 2) / div;
 151                 mul = (rate + pll_in / 2) / pll_in;
 152
 153                 if (mul == 0)
 154                         continue;
 155
 156                 actual = pll_in * mul;
 157                 rate_error = abs(actual - rate);
 158
 159                 if (rate_error < rate_error_prev) {
 160                         mul_best_fit = mul;
 161                         div_best_fit = div;
 162                         rate_error_prev = rate_error;
 163                 }
 164
 165                 if (rate_error == 0)
 166                         break;
 167         }
 168
 169         if (div_best_fit == 0)
 170                 return -EINVAL;
 171
 172         ctrl |= PM_BF(PLLMUL, mul_best_fit - 1);
 173         ctrl |= PM_BF(PLLDIV, div_best_fit - 1);
 174         ctrl |= PM_BF(PLLCOUNT, 16);
 175
 176         if (clk->parent == &osc1)
 177                 ctrl |= PM_BIT(PLLOSC);
 178
 179         *pll_ctrl = ctrl;
 180
 181         return actual;
 182 }
 183
 184 static unsigned long pll0_get_rate(struct clk *clk)
 185 {
 186         u32 control;
 187
 188         control = pm_readl(PLL0);
 189
 190         return pll_get_rate(clk, control);
 191 }
 192
 193 static void pll1_mode(struct clk *clk, int enabled)
 194 {
 195         unsigned long timeout;
 196         u32 status;
 197         u32 ctrl;
 198
 199         ctrl = pm_readl(PLL1);
 200
 201         if (enabled) {
 202                 if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) {
 203                         pr_debug("clk %s: failed to enable, rate not set\n",
 204                                         clk->name);
 205                         return;
 206                 }
 207
 208                 ctrl |= PM_BIT(PLLEN);
 209                 pm_writel(PLL1, ctrl);
 210
 211                 /* Wait for PLL lock. */
 212                 for (timeout = 10000; timeout; timeout--) {
 213                         status = pm_readl(ISR);
 214                         if (status & PM_BIT(LOCK1))
 215                                 break;
 216                         udelay(10);
 217                 }
 218
 219                 if (!(status & PM_BIT(LOCK1)))
 220                         printk(KERN_ERR "clk %s: timeout waiting for lock\n",
 221                                         clk->name);
 222         } else {
 223                 ctrl &= ~PM_BIT(PLLEN);
 224                 pm_writel(PLL1, ctrl);
 225         }
 226 }
 227
 228 static unsigned long pll1_get_rate(struct clk *clk)
 229 {
 230         u32 control;
 231
 232         control = pm_readl(PLL1);
 233
 234         return pll_get_rate(clk, control);
 235 }
 236
 237 static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply)
 238 {
 239         u32 ctrl = 0;
 240         unsigned long actual_rate;
 241
 242         actual_rate = pll_set_rate(clk, rate, &ctrl);
 243
 244         if (apply) {
 245                 if (actual_rate != rate)
 246                         return -EINVAL;
 247                 if (clk->users > 0)
 248                         return -EBUSY;
 249                 pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
 250                                 clk->name, rate, actual_rate);
 251                 pm_writel(PLL1, ctrl);
 252         }
 253
 254         return actual_rate;
 255 }
 256
 257 static int pll1_set_parent(struct clk *clk, struct clk *parent)
 258 {
 259         u32 ctrl;
 260
 261         if (clk->users > 0)
 262                 return -EBUSY;
 263
 264         ctrl = pm_readl(PLL1);
 265         WARN_ON(ctrl & PM_BIT(PLLEN));
 266
 267         if (parent == &osc0)
 268                 ctrl &= ~PM_BIT(PLLOSC);
 269         else if (parent == &osc1)
 270                 ctrl |= PM_BIT(PLLOSC);
 271         else
 272                 return -EINVAL;
 273
 274         pm_writel(PLL1, ctrl);
 275         clk->parent = parent;
 276
 277         return 0;
 278 }
 279
 280 /*
 281  * The AT32AP7000 has five primary clock sources: One 32kHz
 282  * oscillator, two crystal oscillators and two PLLs.
 283  */
 284 static struct clk osc32k = {
 285         .name           = "osc32k",
 286         .get_rate       = osc_get_rate,
 287         .users          = 1,
 288         .index          = 0,
 289 };
 290 static struct clk osc0 = {
 291         .name           = "osc0",
 292         .get_rate       = osc_get_rate,
 293         .users          = 1,
 294         .index          = 1,
 295 };
 296 static struct clk osc1 = {
 297         .name           = "osc1",
 298         .get_rate       = osc_get_rate,
 299         .index          = 2,
 300 };
 301 static struct clk pll0 = {
 302         .name           = "pll0",
 303         .get_rate       = pll0_get_rate,
 304         .parent         = &osc0,
 305 };
 306 static struct clk pll1 = {
 307         .name           = "pll1",
 308         .mode           = pll1_mode,
 309         .get_rate       = pll1_get_rate,
 310         .set_rate       = pll1_set_rate,
 311         .set_parent     = pll1_set_parent,
 312         .parent         = &osc0,
 313 };
 314
 315 /*
 316  * The main clock can be either osc0 or pll0.  The boot loader may
 317  * have chosen one for us, so we don't really know which one until we
 318  * have a look at the SM.
 319  */
 320 static struct clk *main_clock;
 321
 322 /*
 323  * Synchronous clocks are generated from the main clock. The clocks
 324  * must satisfy the constraint
 325  *   fCPU >= fHSB >= fPB
 326  * i.e. each clock must not be faster than its parent.
 327  */
 328 static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
 329 {
 330         return main_clock->get_rate(main_clock) >> shift;
 331 };
 332
 333 static void cpu_clk_mode(struct clk *clk, int enabled)
 334 {
 335         unsigned long flags;
 336         u32 mask;
 337
 338         spin_lock_irqsave(&pm_lock, flags);
 339         mask = pm_readl(CPU_MASK);
 340         if (enabled)
 341                 mask |= 1 << clk->index;
 342         else
 343                 mask &= ~(1 << clk->index);
 344         pm_writel(CPU_MASK, mask);
 345         spin_unlock_irqrestore(&pm_lock, flags);
 346 }
 347
 348 static unsigned long cpu_clk_get_rate(struct clk *clk)
 349 {
 350         unsigned long cksel, shift = 0;
 351
 352         cksel = pm_readl(CKSEL);
 353         if (cksel & PM_BIT(CPUDIV))
 354                 shift = PM_BFEXT(CPUSEL, cksel) + 1;
 355
 356         return bus_clk_get_rate(clk, shift);
 357 }
 358
 359 static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
 360 {
 361         u32 control;
 362         unsigned long parent_rate, child_div, actual_rate, div;
 363
 364         parent_rate = clk->parent->get_rate(clk->parent);
 365         control = pm_readl(CKSEL);
 366
 367         if (control & PM_BIT(HSBDIV))
 368                 child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
 369         else
 370                 child_div = 1;
 371
 372         if (rate > 3 * (parent_rate / 4) || child_div == 1) {
 373                 actual_rate = parent_rate;
 374                 control &= ~PM_BIT(CPUDIV);
 375         } else {
 376                 unsigned int cpusel;
 377                 div = (parent_rate + rate / 2) / rate;
 378                 if (div > child_div)
 379                         div = child_div;
 380                 cpusel = (div > 1) ? (fls(div) - 2) : 0;
 381                 control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
 382                 actual_rate = parent_rate / (1 << (cpusel + 1));
 383         }
 384
 385         pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
 386                         clk->name, rate, actual_rate);
 387
 388         if (apply)
 389                 pm_writel(CKSEL, control);
 390
 391         return actual_rate;
 392 }
 393
 394 static void hsb_clk_mode(struct clk *clk, int enabled)
 395 {
 396         unsigned long flags;
 397         u32 mask;
 398
 399         spin_lock_irqsave(&pm_lock, flags);
 400         mask = pm_readl(HSB_MASK);
 401         if (enabled)
 402                 mask |= 1 << clk->index;
 403         else
 404                 mask &= ~(1 << clk->index);
 405         pm_writel(HSB_MASK, mask);
 406         spin_unlock_irqrestore(&pm_lock, flags);
 407 }
 408
 409 static unsigned long hsb_clk_get_rate(struct clk *clk)
 410 {
 411         unsigned long cksel, shift = 0;
 412
 413         cksel = pm_readl(CKSEL);
 414         if (cksel & PM_BIT(HSBDIV))
 415                 shift = PM_BFEXT(HSBSEL, cksel) + 1;
 416
 417         return bus_clk_get_rate(clk, shift);
 418 }
 419
 420 static void pba_clk_mode(struct clk *clk, int enabled)
 421 {
 422         unsigned long flags;
 423         u32 mask;
 424
 425         spin_lock_irqsave(&pm_lock, flags);
 426         mask = pm_readl(PBA_MASK);
 427         if (enabled)
 428                 mask |= 1 << clk->index;
 429         else
 430                 mask &= ~(1 << clk->index);
 431         pm_writel(PBA_MASK, mask);
 432         spin_unlock_irqrestore(&pm_lock, flags);
 433 }
 434
 435 static unsigned long pba_clk_get_rate(struct clk *clk)
 436 {
 437         unsigned long cksel, shift = 0;
 438
 439         cksel = pm_readl(CKSEL);
 440         if (cksel & PM_BIT(PBADIV))
 441                 shift = PM_BFEXT(PBASEL, cksel) + 1;
 442
 443         return bus_clk_get_rate(clk, shift);
 444 }
 445
 446 static void pbb_clk_mode(struct clk *clk, int enabled)
 447 {
 448         unsigned long flags;
 449         u32 mask;
 450
 451         spin_lock_irqsave(&pm_lock, flags);
 452         mask = pm_readl(PBB_MASK);
 453         if (enabled)
 454                 mask |= 1 << clk->index;
 455         else
 456                 mask &= ~(1 << clk->index);
 457         pm_writel(PBB_MASK, mask);
 458         spin_unlock_irqrestore(&pm_lock, flags);
 459 }
 460
 461 static unsigned long pbb_clk_get_rate(struct clk *clk)
 462 {
 463         unsigned long cksel, shift = 0;
 464
 465         cksel = pm_readl(CKSEL);
 466         if (cksel & PM_BIT(PBBDIV))
 467                 shift = PM_BFEXT(PBBSEL, cksel) + 1;
 468
 469         return bus_clk_get_rate(clk, shift);
 470 }
 471
 472 static struct clk cpu_clk = {
 473         .name           = "cpu",
 474         .get_rate       = cpu_clk_get_rate,
 475         .set_rate       = cpu_clk_set_rate,
 476         .users          = 1,
 477 };
 478 static struct clk hsb_clk = {
 479         .name           = "hsb",
 480         .parent         = &cpu_clk,
 481         .get_rate       = hsb_clk_get_rate,
 482 };
 483 static struct clk pba_clk = {
 484         .name           = "pba",
 485         .parent         = &hsb_clk,
 486         .mode           = hsb_clk_mode,
 487         .get_rate       = pba_clk_get_rate,
 488         .index          = 1,
 489 };
 490 static struct clk pbb_clk = {
 491         .name           = "pbb",
 492         .parent         = &hsb_clk,
 493         .mode           = hsb_clk_mode,
 494         .get_rate       = pbb_clk_get_rate,
 495         .users          = 1,
 496         .index          = 2,
 497 };
 498
 499 /* --------------------------------------------------------------------
 500  *  Generic Clock operations
 501  * -------------------------------------------------------------------- */
 502
 503 static void genclk_mode(struct clk *clk, int enabled)
 504 {
 505         u32 control;
 506
 507         control = pm_readl(GCCTRL(clk->index));
 508         if (enabled)
 509                 control |= PM_BIT(CEN);
 510         else
 511                 control &= ~PM_BIT(CEN);
 512         pm_writel(GCCTRL(clk->index), control);
 513 }
 514
 515 static unsigned long genclk_get_rate(struct clk *clk)
 516 {
 517         u32 control;
 518         unsigned long div = 1;
 519
 520         control = pm_readl(GCCTRL(clk->index));
 521         if (control & PM_BIT(DIVEN))
 522                 div = 2 * (PM_BFEXT(DIV, control) + 1);
 523
 524         return clk->parent->get_rate(clk->parent) / div;
 525 }
 526
 527 static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
 528 {
 529         u32 control;
 530         unsigned long parent_rate, actual_rate, div;
 531
 532         parent_rate = clk->parent->get_rate(clk->parent);
 533         control = pm_readl(GCCTRL(clk->index));
 534
 535         if (rate > 3 * parent_rate / 4) {
 536                 actual_rate = parent_rate;
 537                 control &= ~PM_BIT(DIVEN);
 538         } else {
 539                 div = (parent_rate + rate) / (2 * rate) - 1;
 540                 control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
 541                 actual_rate = parent_rate / (2 * (div + 1));
 542         }
 543
 544         dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
 545                 clk->name, rate, actual_rate);
 546
 547         if (apply)
 548                 pm_writel(GCCTRL(clk->index), control);
 549
 550         return actual_rate;
 551 }
 552
 553 int genclk_set_parent(struct clk *clk, struct clk *parent)
 554 {
 555         u32 control;
 556
 557         dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
 558                 clk->name, parent->name, clk->parent->name);
 559
 560         control = pm_readl(GCCTRL(clk->index));
 561
 562         if (parent == &osc1 || parent == &pll1)
 563                 control |= PM_BIT(OSCSEL);
 564         else if (parent == &osc0 || parent == &pll0)
 565                 control &= ~PM_BIT(OSCSEL);
 566         else
 567                 return -EINVAL;
 568
 569         if (parent == &pll0 || parent == &pll1)
 570                 control |= PM_BIT(PLLSEL);
 571         else
 572                 control &= ~PM_BIT(PLLSEL);
 573
 574         pm_writel(GCCTRL(clk->index), control);
 575         clk->parent = parent;
 576
 577         return 0;
 578 }
 579
 580 static void __init genclk_init_parent(struct clk *clk)
 581 {
 582         u32 control;
 583         struct clk *parent;
 584
 585         BUG_ON(clk->index > 7);
 586
 587         control = pm_readl(GCCTRL(clk->index));
 588         if (control & PM_BIT(OSCSEL))
 589                 parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
 590         else
 591                 parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
 592
 593         clk->parent = parent;
 594 }
 595
 596 /* --------------------------------------------------------------------
 597  *  System peripherals
 598  * -------------------------------------------------------------------- */
 599 static struct resource at32_pm0_resource[] = {
 600         {
 601                 .start  = 0xfff00000,
 602                 .end    = 0xfff0007f,
 603                 .flags  = IORESOURCE_MEM,
 604         },
 605         IRQ(20),
 606 };
 607
 608 static struct resource at32ap700x_rtc0_resource[] = {
 609         {
 610                 .start  = 0xfff00080,
 611                 .end    = 0xfff000af,
 612                 .flags  = IORESOURCE_MEM,
 613         },
 614         IRQ(21),
 615 };
 616
 617 static struct resource at32_wdt0_resource[] = {
 618         {
 619                 .start  = 0xfff000b0,
 620                 .end    = 0xfff000cf,
 621                 .flags  = IORESOURCE_MEM,
 622         },
 623 };
 624
 625 static struct resource at32_eic0_resource[] = {
 626         {
 627                 .start  = 0xfff00100,
 628                 .end    = 0xfff0013f,
 629                 .flags  = IORESOURCE_MEM,
 630         },
 631         IRQ(19),
 632 };
 633
 634 DEFINE_DEV(at32_pm, 0);
 635 DEFINE_DEV(at32ap700x_rtc, 0);
 636 DEFINE_DEV(at32_wdt, 0);
 637 DEFINE_DEV(at32_eic, 0);
 638
 639 /*
 640  * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
 641  * is always running.
 642  */
 643 static struct clk at32_pm_pclk = {
 644         .name           = "pclk",
 645         .dev            = &at32_pm0_device.dev,
 646         .parent         = &pbb_clk,
 647         .mode           = pbb_clk_mode,
 648         .get_rate       = pbb_clk_get_rate,
 649         .users          = 1,
 650         .index          = 0,
 651 };
 652
 653 static struct resource intc0_resource[] = {
 654         PBMEM(0xfff00400),
 655 };
 656 struct platform_device at32_intc0_device = {
 657         .name           = "intc",
 658         .id             = 0,
 659         .resource       = intc0_resource,
 660         .num_resources  = ARRAY_SIZE(intc0_resource),
 661 };
 662 DEV_CLK(pclk, at32_intc0, pbb, 1);
 663
 664 static struct clk ebi_clk = {
 665         .name           = "ebi",
 666         .parent         = &hsb_clk,
 667         .mode           = hsb_clk_mode,
 668         .get_rate       = hsb_clk_get_rate,
 669         .users          = 1,
 670 };
 671 static struct clk hramc_clk = {
 672         .name           = "hramc",
 673         .parent         = &hsb_clk,
 674         .mode           = hsb_clk_mode,
 675         .get_rate       = hsb_clk_get_rate,
 676         .users          = 1,
 677         .index          = 3,
 678 };
 679 static struct clk sdramc_clk = {
 680         .name           = "sdramc_clk",
 681         .parent         = &pbb_clk,
 682         .mode           = pbb_clk_mode,
 683         .get_rate       = pbb_clk_get_rate,
 684         .users          = 1,
 685         .index          = 14,
 686 };
 687
 688 static struct resource smc0_resource[] = {
 689         PBMEM(0xfff03400),
 690 };
 691 DEFINE_DEV(smc, 0);
 692 DEV_CLK(pclk, smc0, pbb, 13);
 693 DEV_CLK(mck, smc0, hsb, 0);
 694
 695 static struct platform_device pdc_device = {
 696         .name           = "pdc",
 697         .id             = 0,
 698 };
 699 DEV_CLK(hclk, pdc, hsb, 4);
 700 DEV_CLK(pclk, pdc, pba, 16);
 701
 702 static struct clk pico_clk = {
 703         .name           = "pico",
 704         .parent         = &cpu_clk,
 705         .mode           = cpu_clk_mode,
 706         .get_rate       = cpu_clk_get_rate,
 707         .users          = 1,
 708 };
 709
 710 static struct resource dmaca0_resource[] = {
 711         {
 712                 .start  = 0xff200000,
 713                 .end    = 0xff20ffff,
 714                 .flags  = IORESOURCE_MEM,
 715         },
 716         IRQ(2),
 717 };
 718 DEFINE_DEV(dmaca, 0);
 719 DEV_CLK(hclk, dmaca0, hsb, 10);
 720
 721 /* --------------------------------------------------------------------
 722  * HMATRIX
 723  * -------------------------------------------------------------------- */
 724
 725 static struct clk hmatrix_clk = {
 726         .name           = "hmatrix_clk",
 727         .parent         = &pbb_clk,
 728         .mode           = pbb_clk_mode,
 729         .get_rate       = pbb_clk_get_rate,
 730         .index          = 2,
 731         .users          = 1,
 732 };
 733 #define HMATRIX_BASE    ((void __iomem *)0xfff00800)
 734
 735 #define hmatrix_readl(reg)                                      \
 736         __raw_readl((HMATRIX_BASE) + HMATRIX_##reg)
 737 #define hmatrix_writel(reg,value)                               \
 738         __raw_writel((value), (HMATRIX_BASE) + HMATRIX_##reg)
 739
 740 /*
 741  * Set bits in the HMATRIX Special Function Register (SFR) used by the
 742  * External Bus Interface (EBI). This can be used to enable special
 743  * features like CompactFlash support, NAND Flash support, etc. on
 744  * certain chipselects.
 745  */
 746 static inline void set_ebi_sfr_bits(u32 mask)
 747 {
 748         u32 sfr;
 749
 750         clk_enable(&hmatrix_clk);
 751         sfr = hmatrix_readl(SFR4);
 752         sfr |= mask;
 753         hmatrix_writel(SFR4, sfr);
 754         clk_disable(&hmatrix_clk);
 755 }
 756
 757 /* --------------------------------------------------------------------
 758  *  Timer/Counter (TC)
 759  * -------------------------------------------------------------------- */
 760
 761 static struct resource at32_tcb0_resource[] = {
 762         PBMEM(0xfff00c00),
 763         IRQ(22),
 764 };
 765 static struct platform_device at32_tcb0_device = {
 766         .name           = "atmel_tcb",
 767         .id             = 0,
 768         .resource       = at32_tcb0_resource,
 769         .num_resources  = ARRAY_SIZE(at32_tcb0_resource),
 770 };
 771 DEV_CLK(t0_clk, at32_tcb0, pbb, 3);
 772
 773 static struct resource at32_tcb1_resource[] = {
 774         PBMEM(0xfff01000),
 775         IRQ(23),
 776 };
 777 static struct platform_device at32_tcb1_device = {
 778         .name           = "atmel_tcb",
 779         .id             = 1,
 780         .resource       = at32_tcb1_resource,
 781         .num_resources  = ARRAY_SIZE(at32_tcb1_resource),
 782 };
 783 DEV_CLK(t0_clk, at32_tcb1, pbb, 4);
 784
 785 /* --------------------------------------------------------------------
 786  *  PIO
 787  * -------------------------------------------------------------------- */
 788
 789 static struct resource pio0_resource[] = {
 790         PBMEM(0xffe02800),
 791         IRQ(13),
 792 };
 793 DEFINE_DEV(pio, 0);
 794 DEV_CLK(mck, pio0, pba, 10);
 795
 796 static struct resource pio1_resource[] = {
 797         PBMEM(0xffe02c00),
 798         IRQ(14),
 799 };
 800 DEFINE_DEV(pio, 1);
 801 DEV_CLK(mck, pio1, pba, 11);
 802
 803 static struct resource pio2_resource[] = {
 804         PBMEM(0xffe03000),
 805         IRQ(15),
 806 };
 807 DEFINE_DEV(pio, 2);
 808 DEV_CLK(mck, pio2, pba, 12);
 809
 810 static struct resource pio3_resource[] = {
 811         PBMEM(0xffe03400),
 812         IRQ(16),
 813 };
 814 DEFINE_DEV(pio, 3);
 815 DEV_CLK(mck, pio3, pba, 13);
 816
 817 static struct resource pio4_resource[] = {
 818         PBMEM(0xffe03800),
 819         IRQ(17),
 820 };
 821 DEFINE_DEV(pio, 4);
 822 DEV_CLK(mck, pio4, pba, 14);
 823
 824 void __init at32_add_system_devices(void)
 825 {
 826         platform_device_register(&at32_pm0_device);
 827         platform_device_register(&at32_intc0_device);
 828         platform_device_register(&at32ap700x_rtc0_device);
 829         platform_device_register(&at32_wdt0_device);
 830         platform_device_register(&at32_eic0_device);
 831         platform_device_register(&smc0_device);
 832         platform_device_register(&pdc_device);
 833         platform_device_register(&dmaca0_device);
 834
 835         platform_device_register(&at32_tcb0_device);
 836         platform_device_register(&at32_tcb1_device);
 837
 838         platform_device_register(&pio0_device);
 839         platform_device_register(&pio1_device);
 840         platform_device_register(&pio2_device);
 841         platform_device_register(&pio3_device);
 842         platform_device_register(&pio4_device);
 843 }
 844
 845 /* --------------------------------------------------------------------
 846  *  PSIF
 847  * -------------------------------------------------------------------- */
 848 static struct resource atmel_psif0_resource[] __initdata = {
 849         {
 850                 .start  = 0xffe03c00,
 851                 .end    = 0xffe03cff,
 852                 .flags  = IORESOURCE_MEM,
 853         },
 854         IRQ(18),
 855 };
 856 static struct clk atmel_psif0_pclk = {
 857         .name           = "pclk",
 858         .parent         = &pba_clk,
 859         .mode           = pba_clk_mode,
 860         .get_rate       = pba_clk_get_rate,
 861         .index          = 15,
 862 };
 863
 864 static struct resource atmel_psif1_resource[] __initdata = {
 865         {
 866                 .start  = 0xffe03d00,
 867                 .end    = 0xffe03dff,
 868                 .flags  = IORESOURCE_MEM,
 869         },
 870         IRQ(18),
 871 };
 872 static struct clk atmel_psif1_pclk = {
 873         .name           = "pclk",
 874         .parent         = &pba_clk,
 875         .mode           = pba_clk_mode,
 876         .get_rate       = pba_clk_get_rate,
 877         .index          = 15,
 878 };
 879
 880 struct platform_device *__init at32_add_device_psif(unsigned int id)
 881 {
 882         struct platform_device *pdev;
 883
 884         if (!(id == 0 || id == 1))
 885                 return NULL;
 886
 887         pdev = platform_device_alloc("atmel_psif", id);
 888         if (!pdev)
 889                 return NULL;
 890
 891         switch (id) {
 892         case 0:
 893                 if (platform_device_add_resources(pdev, atmel_psif0_resource,
 894                                         ARRAY_SIZE(atmel_psif0_resource)))
 895                         goto err_add_resources;
 896                 atmel_psif0_pclk.dev = &pdev->dev;
 897                 select_peripheral(PA(8), PERIPH_A, 0); /* CLOCK */
 898                 select_peripheral(PA(9), PERIPH_A, 0); /* DATA  */
 899                 break;
 900         case 1:
 901                 if (platform_device_add_resources(pdev, atmel_psif1_resource,
 902                                         ARRAY_SIZE(atmel_psif1_resource)))
 903                         goto err_add_resources;
 904                 atmel_psif1_pclk.dev = &pdev->dev;
 905                 select_peripheral(PB(11), PERIPH_A, 0); /* CLOCK */
 906                 select_peripheral(PB(12), PERIPH_A, 0); /* DATA  */
 907                 break;
 908         default:
 909                 return NULL;
 910         }
 911
 912         platform_device_add(pdev);
 913         return pdev;
 914
 915 err_add_resources:
 916         platform_device_put(pdev);
 917         return NULL;
 918 }
 919
 920 /* --------------------------------------------------------------------
 921  *  USART
 922  * -------------------------------------------------------------------- */
 923
 924 static struct atmel_uart_data atmel_usart0_data = {
 925         .use_dma_tx     = 1,
 926         .use_dma_rx     = 1,
 927 };
 928 static struct resource atmel_usart0_resource[] = {
 929         PBMEM(0xffe00c00),
 930         IRQ(6),
 931 };
 932 DEFINE_DEV_DATA(atmel_usart, 0);
 933 DEV_CLK(usart, atmel_usart0, pba, 3);
 934
 935 static struct atmel_uart_data atmel_usart1_data = {
 936         .use_dma_tx     = 1,
 937         .use_dma_rx     = 1,
 938 };
 939 static struct resource atmel_usart1_resource[] = {
 940         PBMEM(0xffe01000),
 941         IRQ(7),
 942 };
 943 DEFINE_DEV_DATA(atmel_usart, 1);
 944 DEV_CLK(usart, atmel_usart1, pba, 4);
 945
 946 static struct atmel_uart_data atmel_usart2_data = {
 947         .use_dma_tx     = 1,
 948         .use_dma_rx     = 1,
 949 };
 950 static struct resource atmel_usart2_resource[] = {
 951         PBMEM(0xffe01400),
 952         IRQ(8),
 953 };
 954 DEFINE_DEV_DATA(atmel_usart, 2);
 955 DEV_CLK(usart, atmel_usart2, pba, 5);
 956
 957 static struct atmel_uart_data atmel_usart3_data = {
 958         .use_dma_tx     = 1,
 959         .use_dma_rx     = 1,
 960 };
 961 static struct resource atmel_usart3_resource[] = {
 962         PBMEM(0xffe01800),
 963         IRQ(9),
 964 };
 965 DEFINE_DEV_DATA(atmel_usart, 3);
 966 DEV_CLK(usart, atmel_usart3, pba, 6);
 967
 968 static inline void configure_usart0_pins(void)
 969 {
 970         select_peripheral(PA(8),  PERIPH_B, 0); /* RXD  */
 971         select_peripheral(PA(9),  PERIPH_B, 0); /* TXD  */
 972 }
 973
 974 static inline void configure_usart1_pins(void)
 975 {
 976         select_peripheral(PA(17), PERIPH_A, 0); /* RXD  */
 977         select_peripheral(PA(18), PERIPH_A, 0); /* TXD  */
 978 }
 979
 980 static inline void configure_usart2_pins(void)
 981 {
 982         select_peripheral(PB(26), PERIPH_B, 0); /* RXD  */
 983         select_peripheral(PB(27), PERIPH_B, 0); /* TXD  */
 984 }
 985
 986 static inline void configure_usart3_pins(void)
 987 {
 988         select_peripheral(PB(18), PERIPH_B, 0); /* RXD  */
 989         select_peripheral(PB(17), PERIPH_B, 0); /* TXD  */
 990 }
 991
 992 static struct platform_device *__initdata at32_usarts[4];
 993
 994 void __init at32_map_usart(unsigned int hw_id, unsigned int line)
 995 {
 996         struct platform_device *pdev;
 997
 998         switch (hw_id) {
 999         case 0:
1000                 pdev = &atmel_usart0_device;
1001                 configure_usart0_pins();
1002                 break;
1003         case 1:
1004                 pdev = &atmel_usart1_device;
1005                 configure_usart1_pins();
1006                 break;
1007         case 2:
1008                 pdev = &atmel_usart2_device;
1009                 configure_usart2_pins();
1010                 break;
1011         case 3:
1012                 pdev = &atmel_usart3_device;
1013                 configure_usart3_pins();
1014                 break;
1015         default:
1016                 return;
1017         }
1018
1019         if (PXSEG(pdev->resource[0].start) == P4SEG) {
1020                 /* Addresses in the P4 segment are permanently mapped 1:1 */
1021                 struct atmel_uart_data *data = pdev->dev.platform_data;
1022                 data->regs = (void __iomem *)pdev->resource[0].start;
1023         }
1024
1025         pdev->id = line;
1026         at32_usarts[line] = pdev;
1027 }
1028
1029 struct platform_device *__init at32_add_device_usart(unsigned int id)
1030 {
1031         platform_device_register(at32_usarts[id]);
1032         return at32_usarts[id];
1033 }
1034
1035 struct platform_device *atmel_default_console_device;
1036
1037 void __init at32_setup_serial_console(unsigned int usart_id)
1038 {
1039         atmel_default_console_device = at32_usarts[usart_id];
1040 }
1041
1042 /* --------------------------------------------------------------------
1043  *  Ethernet
1044  * -------------------------------------------------------------------- */
1045
1046 #ifdef CONFIG_CPU_AT32AP7000
1047 static struct eth_platform_data macb0_data;
1048 static struct resource macb0_resource[] = {
1049         PBMEM(0xfff01800),
1050         IRQ(25),
1051 };
1052 DEFINE_DEV_DATA(macb, 0);
1053 DEV_CLK(hclk, macb0, hsb, 8);
1054 DEV_CLK(pclk, macb0, pbb, 6);
1055
1056 static struct eth_platform_data macb1_data;
1057 static struct resource macb1_resource[] = {
1058         PBMEM(0xfff01c00),
1059         IRQ(26),
1060 };
1061 DEFINE_DEV_DATA(macb, 1);
1062 DEV_CLK(hclk, macb1, hsb, 9);
1063 DEV_CLK(pclk, macb1, pbb, 7);
1064
1065 struct platform_device *__init
1066 at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
1067 {
1068         struct platform_device *pdev;
1069
1070         switch (id) {
1071         case 0:
1072                 pdev = &macb0_device;
1073
1074                 select_peripheral(PC(3),  PERIPH_A, 0); /* TXD0 */
1075                 select_peripheral(PC(4),  PERIPH_A, 0); /* TXD1 */
1076                 select_peripheral(PC(7),  PERIPH_A, 0); /* TXEN */
1077                 select_peripheral(PC(8),  PERIPH_A, 0); /* TXCK */
1078                 select_peripheral(PC(9),  PERIPH_A, 0); /* RXD0 */
1079                 select_peripheral(PC(10), PERIPH_A, 0); /* RXD1 */
1080                 select_peripheral(PC(13), PERIPH_A, 0); /* RXER */
1081                 select_peripheral(PC(15), PERIPH_A, 0); /* RXDV */
1082                 select_peripheral(PC(16), PERIPH_A, 0); /* MDC  */
1083                 select_peripheral(PC(17), PERIPH_A, 0); /* MDIO */
1084
1085                 if (!data->is_rmii) {
1086                         select_peripheral(PC(0),  PERIPH_A, 0); /* COL  */
1087                         select_peripheral(PC(1),  PERIPH_A, 0); /* CRS  */
1088                         select_peripheral(PC(2),  PERIPH_A, 0); /* TXER */
1089                         select_peripheral(PC(5),  PERIPH_A, 0); /* TXD2 */
1090                         select_peripheral(PC(6),  PERIPH_A, 0); /* TXD3 */
1091                         select_peripheral(PC(11), PERIPH_A, 0); /* RXD2 */
1092                         select_peripheral(PC(12), PERIPH_A, 0); /* RXD3 */
1093                         select_peripheral(PC(14), PERIPH_A, 0); /* RXCK */
1094                         select_peripheral(PC(18), PERIPH_A, 0); /* SPD  */
1095                 }
1096                 break;
1097
1098         case 1:
1099                 pdev = &macb1_device;
1100
1101                 select_peripheral(PD(13), PERIPH_B, 0);         /* TXD0 */
1102                 select_peripheral(PD(14), PERIPH_B, 0);         /* TXD1 */
1103                 select_peripheral(PD(11), PERIPH_B, 0);         /* TXEN */
1104                 select_peripheral(PD(12), PERIPH_B, 0);         /* TXCK */
1105                 select_peripheral(PD(10), PERIPH_B, 0);         /* RXD0 */
1106                 select_peripheral(PD(6),  PERIPH_B, 0);         /* RXD1 */
1107                 select_peripheral(PD(5),  PERIPH_B, 0);         /* RXER */
1108                 select_peripheral(PD(4),  PERIPH_B, 0);         /* RXDV */
1109                 select_peripheral(PD(3),  PERIPH_B, 0);         /* MDC  */
1110                 select_peripheral(PD(2),  PERIPH_B, 0);         /* MDIO */
1111
1112                 if (!data->is_rmii) {
1113                         select_peripheral(PC(19), PERIPH_B, 0); /* COL  */
1114                         select_peripheral(PC(23), PERIPH_B, 0); /* CRS  */
1115                         select_peripheral(PC(26), PERIPH_B, 0); /* TXER */
1116                         select_peripheral(PC(27), PERIPH_B, 0); /* TXD2 */
1117                         select_peripheral(PC(28), PERIPH_B, 0); /* TXD3 */
1118                         select_peripheral(PC(29), PERIPH_B, 0); /* RXD2 */
1119                         select_peripheral(PC(30), PERIPH_B, 0); /* RXD3 */
1120                         select_peripheral(PC(24), PERIPH_B, 0); /* RXCK */
1121                         select_peripheral(PD(15), PERIPH_B, 0); /* SPD  */
1122                 }
1123                 break;
1124
1125         default:
1126                 return NULL;
1127         }
1128
1129         memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
1130         platform_device_register(pdev);
1131
1132         return pdev;
1133 }
1134 #endif
1135
1136 /* --------------------------------------------------------------------
1137  *  SPI
1138  * -------------------------------------------------------------------- */
1139 static struct resource atmel_spi0_resource[] = {
1140         PBMEM(0xffe00000),
1141         IRQ(3),
1142 };
1143 DEFINE_DEV(atmel_spi, 0);
1144 DEV_CLK(spi_clk, atmel_spi0, pba, 0);
1145
1146 static struct resource atmel_spi1_resource[] = {
1147         PBMEM(0xffe00400),
1148         IRQ(4),
1149 };
1150 DEFINE_DEV(atmel_spi, 1);
1151 DEV_CLK(spi_clk, atmel_spi1, pba, 1);
1152
1153 static void __init
1154 at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
1155                       unsigned int n, const u8 *pins)
1156 {
1157         unsigned int pin, mode;
1158
1159         for (; n; n--, b++) {
1160                 b->bus_num = bus_num;
1161                 if (b->chip_select >= 4)
1162                         continue;
1163                 pin = (unsigned)b->controller_data;
1164                 if (!pin) {
1165                         pin = pins[b->chip_select];
1166                         b->controller_data = (void *)pin;
1167                 }
1168                 mode = AT32_GPIOF_OUTPUT;
1169                 if (!(b->mode & SPI_CS_HIGH))
1170                         mode |= AT32_GPIOF_HIGH;
1171                 at32_select_gpio(pin, mode);
1172         }
1173 }
1174
1175 struct platform_device *__init
1176 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
1177 {
1178         /*
1179          * Manage the chipselects as GPIOs, normally using the same pins
1180          * the SPI controller expects; but boards can use other pins.
1181          */
1182         static u8 __initdata spi0_pins[] =
1183                 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
1184                   GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
1185         static u8 __initdata spi1_pins[] =
1186                 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
1187                   GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
1188         struct platform_device *pdev;
1189
1190         switch (id) {
1191         case 0:
1192                 pdev = &atmel_spi0_device;
1193                 /* pullup MISO so a level is always defined */
1194                 select_peripheral(PA(0),  PERIPH_A, AT32_GPIOF_PULLUP);
1195                 select_peripheral(PA(1),  PERIPH_A, 0); /* MOSI  */
1196                 select_peripheral(PA(2),  PERIPH_A, 0); /* SCK   */
1197                 at32_spi_setup_slaves(0, b, n, spi0_pins);
1198                 break;
1199
1200         case 1:
1201                 pdev = &atmel_spi1_device;
1202                 /* pullup MISO so a level is always defined */
1203                 select_peripheral(PB(0),  PERIPH_B, AT32_GPIOF_PULLUP);
1204                 select_peripheral(PB(1),  PERIPH_B, 0); /* MOSI  */
1205                 select_peripheral(PB(5),  PERIPH_B, 0); /* SCK   */
1206                 at32_spi_setup_slaves(1, b, n, spi1_pins);
1207                 break;
1208
1209         default:
1210                 return NULL;
1211         }
1212
1213         spi_register_board_info(b, n);
1214         platform_device_register(pdev);
1215         return pdev;
1216 }
1217
1218 /* --------------------------------------------------------------------
1219  *  TWI
1220  * -------------------------------------------------------------------- */
1221 static struct resource atmel_twi0_resource[] __initdata = {
1222         PBMEM(0xffe00800),
1223         IRQ(5),
1224 };
1225 static struct clk atmel_twi0_pclk = {
1226         .name           = "twi_pclk",
1227         .parent         = &pba_clk,
1228         .mode           = pba_clk_mode,
1229         .get_rate       = pba_clk_get_rate,
1230         .index          = 2,
1231 };
1232
1233 struct platform_device *__init at32_add_device_twi(unsigned int id,
1234                                                     struct i2c_board_info *b,
1235                                                     unsigned int n)
1236 {
1237         struct platform_device *pdev;
1238
1239         if (id != 0)
1240                 return NULL;
1241
1242         pdev = platform_device_alloc("atmel_twi", id);
1243         if (!pdev)
1244                 return NULL;
1245
1246         if (platform_device_add_resources(pdev, atmel_twi0_resource,
1247                                 ARRAY_SIZE(atmel_twi0_resource)))
1248                 goto err_add_resources;
1249
1250         select_peripheral(PA(6),  PERIPH_A, 0); /* SDA  */
1251         select_peripheral(PA(7),  PERIPH_A, 0); /* SDL  */
1252
1253         atmel_twi0_pclk.dev = &pdev->dev;
1254
1255         if (b)
1256                 i2c_register_board_info(id, b, n);
1257
1258         platform_device_add(pdev);
1259         return pdev;
1260
1261 err_add_resources:
1262         platform_device_put(pdev);
1263         return NULL;
1264 }
1265
1266 /* --------------------------------------------------------------------
1267  * MMC
1268  * -------------------------------------------------------------------- */
1269 static struct resource atmel_mci0_resource[] __initdata = {
1270         PBMEM(0xfff02400),
1271         IRQ(28),
1272 };
1273 static struct clk atmel_mci0_pclk = {
1274         .name           = "mci_clk",
1275         .parent         = &pbb_clk,
1276         .mode           = pbb_clk_mode,
1277         .get_rate       = pbb_clk_get_rate,
1278         .index          = 9,
1279 };
1280
1281 struct platform_device *__init at32_add_device_mci(unsigned int id)
1282 {
1283         struct platform_device *pdev;
1284
1285         if (id != 0)
1286                 return NULL;
1287
1288         pdev = platform_device_alloc("atmel_mci", id);
1289         if (!pdev)
1290                 return NULL;
1291
1292         if (platform_device_add_resources(pdev, atmel_mci0_resource,
1293                                 ARRAY_SIZE(atmel_mci0_resource)))
1294                 goto err_add_resources;
1295
1296         select_peripheral(PA(10), PERIPH_A, 0); /* CLK   */
1297         select_peripheral(PA(11), PERIPH_A, 0); /* CMD   */
1298         select_peripheral(PA(12), PERIPH_A, 0); /* DATA0 */
1299         select_peripheral(PA(13), PERIPH_A, 0); /* DATA1 */
1300         select_peripheral(PA(14), PERIPH_A, 0); /* DATA2 */
1301         select_peripheral(PA(15), PERIPH_A, 0); /* DATA3 */
1302
1303         atmel_mci0_pclk.dev = &pdev->dev;
1304
1305         platform_device_add(pdev);
1306         return pdev;
1307
1308 err_add_resources:
1309         platform_device_put(pdev);
1310         return NULL;
1311 }
1312
1313 /* --------------------------------------------------------------------
1314  *  LCDC
1315  * -------------------------------------------------------------------- */
1316 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1317 static struct atmel_lcdfb_info atmel_lcdfb0_data;
1318 static struct resource atmel_lcdfb0_resource[] = {
1319         {
1320                 .start          = 0xff000000,
1321                 .end            = 0xff000fff,
1322                 .flags          = IORESOURCE_MEM,
1323         },
1324         IRQ(1),
1325         {
1326                 /* Placeholder for pre-allocated fb memory */
1327                 .start          = 0x00000000,
1328                 .end            = 0x00000000,
1329                 .flags          = 0,
1330         },
1331 };
1332 DEFINE_DEV_DATA(atmel_lcdfb, 0);
1333 DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
1334 static struct clk atmel_lcdfb0_pixclk = {
1335         .name           = "lcdc_clk",
1336         .dev            = &atmel_lcdfb0_device.dev,
1337         .mode           = genclk_mode,
1338         .get_rate       = genclk_get_rate,
1339         .set_rate       = genclk_set_rate,
1340         .set_parent     = genclk_set_parent,
1341         .index          = 7,
1342 };
1343
1344 struct platform_device *__init
1345 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
1346                      unsigned long fbmem_start, unsigned long fbmem_len,
1347                      unsigned int pin_config)
1348 {
1349         struct platform_device *pdev;
1350         struct atmel_lcdfb_info *info;
1351         struct fb_monspecs *monspecs;
1352         struct fb_videomode *modedb;
1353         unsigned int modedb_size;
1354
1355         /*
1356          * Do a deep copy of the fb data, monspecs and modedb. Make
1357          * sure all allocations are done before setting up the
1358          * portmux.
1359          */
1360         monspecs = kmemdup(data->default_monspecs,
1361                            sizeof(struct fb_monspecs), GFP_KERNEL);
1362         if (!monspecs)
1363                 return NULL;
1364
1365         modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
1366         modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
1367         if (!modedb)
1368                 goto err_dup_modedb;
1369         monspecs->modedb = modedb;
1370
1371         switch (id) {
1372         case 0:
1373                 pdev = &atmel_lcdfb0_device;
1374
1375                 switch (pin_config) {
1376                 case 0:
1377                         select_peripheral(PC(19), PERIPH_A, 0); /* CC     */
1378                         select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC  */
1379                         select_peripheral(PC(21), PERIPH_A, 0); /* PCLK   */
1380                         select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC  */
1381                         select_peripheral(PC(23), PERIPH_A, 0); /* DVAL   */
1382                         select_peripheral(PC(24), PERIPH_A, 0); /* MODE   */
1383                         select_peripheral(PC(25), PERIPH_A, 0); /* PWR    */
1384                         select_peripheral(PC(26), PERIPH_A, 0); /* DATA0  */
1385                         select_peripheral(PC(27), PERIPH_A, 0); /* DATA1  */
1386                         select_peripheral(PC(28), PERIPH_A, 0); /* DATA2  */
1387                         select_peripheral(PC(29), PERIPH_A, 0); /* DATA3  */
1388                         select_peripheral(PC(30), PERIPH_A, 0); /* DATA4  */
1389                         select_peripheral(PC(31), PERIPH_A, 0); /* DATA5  */
1390                         select_peripheral(PD(0),  PERIPH_A, 0); /* DATA6  */
1391                         select_peripheral(PD(1),  PERIPH_A, 0); /* DATA7  */
1392                         select_peripheral(PD(2),  PERIPH_A, 0); /* DATA8  */
1393                         select_peripheral(PD(3),  PERIPH_A, 0); /* DATA9  */
1394                         select_peripheral(PD(4),  PERIPH_A, 0); /* DATA10 */
1395                         select_peripheral(PD(5),  PERIPH_A, 0); /* DATA11 */
1396                         select_peripheral(PD(6),  PERIPH_A, 0); /* DATA12 */
1397                         select_peripheral(PD(7),  PERIPH_A, 0); /* DATA13 */
1398                         select_peripheral(PD(8),  PERIPH_A, 0); /* DATA14 */
1399                         select_peripheral(PD(9),  PERIPH_A, 0); /* DATA15 */
1400                         select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
1401                         select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
1402                         select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
1403                         select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
1404                         select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
1405                         select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
1406                         select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
1407                         select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
1408                         break;
1409                 case 1:
1410                         select_peripheral(PE(0),  PERIPH_B, 0); /* CC     */
1411                         select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC  */
1412                         select_peripheral(PC(21), PERIPH_A, 0); /* PCLK   */
1413                         select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC  */
1414                         select_peripheral(PE(1),  PERIPH_B, 0); /* DVAL   */
1415                         select_peripheral(PE(2),  PERIPH_B, 0); /* MODE   */
1416                         select_peripheral(PC(25), PERIPH_A, 0); /* PWR    */
1417                         select_peripheral(PE(3),  PERIPH_B, 0); /* DATA0  */
1418                         select_peripheral(PE(4),  PERIPH_B, 0); /* DATA1  */
1419                         select_peripheral(PE(5),  PERIPH_B, 0); /* DATA2  */
1420                         select_peripheral(PE(6),  PERIPH_B, 0); /* DATA3  */
1421                         select_peripheral(PE(7),  PERIPH_B, 0); /* DATA4  */
1422                         select_peripheral(PC(31), PERIPH_A, 0); /* DATA5  */
1423                         select_peripheral(PD(0),  PERIPH_A, 0); /* DATA6  */
1424                         select_peripheral(PD(1),  PERIPH_A, 0); /* DATA7  */
1425                         select_peripheral(PE(8),  PERIPH_B, 0); /* DATA8  */
1426                         select_peripheral(PE(9),  PERIPH_B, 0); /* DATA9  */
1427                         select_peripheral(PE(10), PERIPH_B, 0); /* DATA10 */
1428                         select_peripheral(PE(11), PERIPH_B, 0); /* DATA11 */
1429                         select_peripheral(PE(12), PERIPH_B, 0); /* DATA12 */
1430                         select_peripheral(PD(7),  PERIPH_A, 0); /* DATA13 */
1431                         select_peripheral(PD(8),  PERIPH_A, 0); /* DATA14 */
1432                         select_peripheral(PD(9),  PERIPH_A, 0); /* DATA15 */
1433                         select_peripheral(PE(13), PERIPH_B, 0); /* DATA16 */
1434                         select_peripheral(PE(14), PERIPH_B, 0); /* DATA17 */
1435                         select_peripheral(PE(15), PERIPH_B, 0); /* DATA18 */
1436                         select_peripheral(PE(16), PERIPH_B, 0); /* DATA19 */
1437                         select_peripheral(PE(17), PERIPH_B, 0); /* DATA20 */
1438                         select_peripheral(PE(18), PERIPH_B, 0); /* DATA21 */
1439                         select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
1440                         select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
1441                         break;
1442                 default:
1443                         goto err_invalid_id;
1444                 }
1445
1446                 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
1447                 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
1448                 break;
1449
1450         default:
1451                 goto err_invalid_id;
1452         }
1453
1454         if (fbmem_len) {
1455                 pdev->resource[2].start = fbmem_start;
1456                 pdev->resource[2].end = fbmem_start + fbmem_len - 1;
1457                 pdev->resource[2].flags = IORESOURCE_MEM;
1458         }
1459
1460         info = pdev->dev.platform_data;
1461         memcpy(info, data, sizeof(struct atmel_lcdfb_info));
1462         info->default_monspecs = monspecs;
1463
1464         platform_device_register(pdev);
1465         return pdev;
1466
1467 err_invalid_id:
1468         kfree(modedb);
1469 err_dup_modedb:
1470         kfree(monspecs);
1471         return NULL;
1472 }
1473 #endif
1474
1475 /* --------------------------------------------------------------------
1476  *  PWM
1477  * -------------------------------------------------------------------- */
1478 static struct resource atmel_pwm0_resource[] __initdata = {
1479         PBMEM(0xfff01400),
1480         IRQ(24),
1481 };
1482 static struct clk atmel_pwm0_mck = {
1483         .name           = "pwm_clk",
1484         .parent         = &pbb_clk,
1485         .mode           = pbb_clk_mode,
1486         .get_rate       = pbb_clk_get_rate,
1487         .index          = 5,
1488 };
1489
1490 struct platform_device *__init at32_add_device_pwm(u32 mask)
1491 {
1492         struct platform_device *pdev;
1493
1494         if (!mask)
1495                 return NULL;
1496
1497         pdev = platform_device_alloc("atmel_pwm", 0);
1498         if (!pdev)
1499                 return NULL;
1500
1501         if (platform_device_add_resources(pdev, atmel_pwm0_resource,
1502                                 ARRAY_SIZE(atmel_pwm0_resource)))
1503                 goto out_free_pdev;
1504
1505         if (platform_device_add_data(pdev, &mask, sizeof(mask)))
1506                 goto out_free_pdev;
1507
1508         if (mask & (1 << 0))
1509                 select_peripheral(PA(28), PERIPH_A, 0);
1510         if (mask & (1 << 1))
1511                 select_peripheral(PA(29), PERIPH_A, 0);
1512         if (mask & (1 << 2))
1513                 select_peripheral(PA(21), PERIPH_B, 0);
1514         if (mask & (1 << 3))
1515                 select_peripheral(PA(22), PERIPH_B, 0);
1516
1517         atmel_pwm0_mck.dev = &pdev->dev;
1518
1519         platform_device_add(pdev);
1520
1521         return pdev;
1522
1523 out_free_pdev:
1524         platform_device_put(pdev);
1525         return NULL;
1526 }
1527
1528 /* --------------------------------------------------------------------
1529  *  SSC
1530  * -------------------------------------------------------------------- */
1531 static struct resource ssc0_resource[] = {
1532         PBMEM(0xffe01c00),
1533         IRQ(10),
1534 };
1535 DEFINE_DEV(ssc, 0);
1536 DEV_CLK(pclk, ssc0, pba, 7);
1537
1538 static struct resource ssc1_resource[] = {
1539         PBMEM(0xffe02000),
1540         IRQ(11),
1541 };
1542 DEFINE_DEV(ssc, 1);
1543 DEV_CLK(pclk, ssc1, pba, 8);
1544
1545 static struct resource ssc2_resource[] = {
1546         PBMEM(0xffe02400),
1547         IRQ(12),
1548 };
1549 DEFINE_DEV(ssc, 2);
1550 DEV_CLK(pclk, ssc2, pba, 9);
1551
1552 struct platform_device *__init
1553 at32_add_device_ssc(unsigned int id, unsigned int flags)
1554 {
1555         struct platform_device *pdev;
1556
1557         switch (id) {
1558         case 0:
1559                 pdev = &ssc0_device;
1560                 if (flags & ATMEL_SSC_RF)
1561                         select_peripheral(PA(21), PERIPH_A, 0); /* RF */
1562                 if (flags & ATMEL_SSC_RK)
1563                         select_peripheral(PA(22), PERIPH_A, 0); /* RK */
1564                 if (flags & ATMEL_SSC_TK)
1565                         select_peripheral(PA(23), PERIPH_A, 0); /* TK */
1566                 if (flags & ATMEL_SSC_TF)
1567                         select_peripheral(PA(24), PERIPH_A, 0); /* TF */
1568                 if (flags & ATMEL_SSC_TD)
1569                         select_peripheral(PA(25), PERIPH_A, 0); /* TD */
1570                 if (flags & ATMEL_SSC_RD)
1571                         select_peripheral(PA(26), PERIPH_A, 0); /* RD */
1572                 break;
1573         case 1:
1574                 pdev = &ssc1_device;
1575                 if (flags & ATMEL_SSC_RF)
1576                         select_peripheral(PA(0), PERIPH_B, 0);  /* RF */
1577                 if (flags & ATMEL_SSC_RK)
1578                         select_peripheral(PA(1), PERIPH_B, 0);  /* RK */
1579                 if (flags & ATMEL_SSC_TK)
1580                         select_peripheral(PA(2), PERIPH_B, 0);  /* TK */
1581                 if (flags & ATMEL_SSC_TF)
1582                         select_peripheral(PA(3), PERIPH_B, 0);  /* TF */
1583                 if (flags & ATMEL_SSC_TD)
1584                         select_peripheral(PA(4), PERIPH_B, 0);  /* TD */
1585                 if (flags & ATMEL_SSC_RD)
1586                         select_peripheral(PA(5), PERIPH_B, 0);  /* RD */
1587                 break;
1588         case 2:
1589                 pdev = &ssc2_device;
1590                 if (flags & ATMEL_SSC_TD)
1591                         select_peripheral(PB(13), PERIPH_A, 0); /* TD */
1592                 if (flags & ATMEL_SSC_RD)
1593                         select_peripheral(PB(14), PERIPH_A, 0); /* RD */
1594                 if (flags & ATMEL_SSC_TK)
1595                         select_peripheral(PB(15), PERIPH_A, 0); /* TK */
1596                 if (flags & ATMEL_SSC_TF)
1597                         select_peripheral(PB(16), PERIPH_A, 0); /* TF */
1598                 if (flags & ATMEL_SSC_RF)
1599                         select_peripheral(PB(17), PERIPH_A, 0); /* RF */
1600                 if (flags & ATMEL_SSC_RK)
1601                         select_peripheral(PB(18), PERIPH_A, 0); /* RK */
1602                 break;
1603         default:
1604                 return NULL;
1605         }
1606
1607         platform_device_register(pdev);
1608         return pdev;
1609 }
1610
1611 /* --------------------------------------------------------------------
1612  *  USB Device Controller
1613  * -------------------------------------------------------------------- */
1614 static struct resource usba0_resource[] __initdata = {
1615         {
1616                 .start          = 0xff300000,
1617                 .end            = 0xff3fffff,
1618                 .flags          = IORESOURCE_MEM,
1619         }, {
1620                 .start          = 0xfff03000,
1621                 .end            = 0xfff033ff,
1622                 .flags          = IORESOURCE_MEM,
1623         },
1624         IRQ(31),
1625 };
1626 static struct clk usba0_pclk = {
1627         .name           = "pclk",
1628         .parent         = &pbb_clk,
1629         .mode           = pbb_clk_mode,
1630         .get_rate       = pbb_clk_get_rate,
1631         .index          = 12,
1632 };
1633 static struct clk usba0_hclk = {
1634         .name           = "hclk",
1635         .parent         = &hsb_clk,
1636         .mode           = hsb_clk_mode,
1637         .get_rate       = hsb_clk_get_rate,
1638         .index          = 6,
1639 };
1640
1641 #define EP(nam, idx, maxpkt, maxbk, dma, isoc)                  \
1642         [idx] = {                                               \
1643                 .name           = nam,                          \
1644                 .index          = idx,                          \
1645                 .fifo_size      = maxpkt,                       \
1646                 .nr_banks       = maxbk,                        \
1647                 .can_dma        = dma,                          \
1648                 .can_isoc       = isoc,                         \
1649         }
1650
1651 static struct usba_ep_data at32_usba_ep[] __initdata = {
1652         EP("ep0",     0,   64, 1, 0, 0),
1653         EP("ep1",     1,  512, 2, 1, 1),
1654         EP("ep2",     2,  512, 2, 1, 1),
1655         EP("ep3-int", 3,   64, 3, 1, 0),
1656         EP("ep4-int", 4,   64, 3, 1, 0),
1657         EP("ep5",     5, 1024, 3, 1, 1),
1658         EP("ep6",     6, 1024, 3, 1, 1),
1659 };
1660
1661 #undef EP
1662
1663 struct platform_device *__init
1664 at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
1665 {
1666         /*
1667          * pdata doesn't have room for any endpoints, so we need to
1668          * append room for the ones we need right after it.
1669          */
1670         struct {
1671                 struct usba_platform_data pdata;
1672                 struct usba_ep_data ep[7];
1673         } usba_data;
1674         struct platform_device *pdev;
1675
1676         if (id != 0)
1677                 return NULL;
1678
1679         pdev = platform_device_alloc("atmel_usba_udc", 0);
1680         if (!pdev)
1681                 return NULL;
1682
1683         if (platform_device_add_resources(pdev, usba0_resource,
1684                                           ARRAY_SIZE(usba0_resource)))
1685                 goto out_free_pdev;
1686
1687         if (data)
1688                 usba_data.pdata.vbus_pin = data->vbus_pin;
1689         else
1690                 usba_data.pdata.vbus_pin = -EINVAL;
1691
1692         data = &usba_data.pdata;
1693         data->num_ep = ARRAY_SIZE(at32_usba_ep);
1694         memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep));
1695
1696         if (platform_device_add_data(pdev, data, sizeof(usba_data)))
1697                 goto out_free_pdev;
1698
1699         if (data->vbus_pin >= 0)
1700                 at32_select_gpio(data->vbus_pin, 0);
1701
1702         usba0_pclk.dev = &pdev->dev;
1703         usba0_hclk.dev = &pdev->dev;
1704
1705         platform_device_add(pdev);
1706
1707         return pdev;
1708
1709 out_free_pdev:
1710         platform_device_put(pdev);
1711         return NULL;
1712 }
1713
1714 /* --------------------------------------------------------------------
1715  * IDE / CompactFlash
1716  * -------------------------------------------------------------------- */
1717 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001)
1718 static struct resource at32_smc_cs4_resource[] __initdata = {
1719         {
1720                 .start  = 0x04000000,
1721                 .end    = 0x07ffffff,
1722                 .flags  = IORESOURCE_MEM,
1723         },
1724         IRQ(~0UL), /* Magic IRQ will be overridden */
1725 };
1726 static struct resource at32_smc_cs5_resource[] __initdata = {
1727         {
1728                 .start  = 0x20000000,
1729                 .end    = 0x23ffffff,
1730                 .flags  = IORESOURCE_MEM,
1731         },
1732         IRQ(~0UL), /* Magic IRQ will be overridden */
1733 };
1734
1735 static int __init at32_init_ide_or_cf(struct platform_device *pdev,
1736                 unsigned int cs, unsigned int extint)
1737 {
1738         static unsigned int extint_pin_map[4] __initdata = {
1739                 GPIO_PIN_PB(25),
1740                 GPIO_PIN_PB(26),
1741                 GPIO_PIN_PB(27),
1742                 GPIO_PIN_PB(28),
1743         };
1744         static bool common_pins_initialized __initdata = false;
1745         unsigned int extint_pin;
1746         int ret;
1747
1748         if (extint >= ARRAY_SIZE(extint_pin_map))
1749                 return -EINVAL;
1750         extint_pin = extint_pin_map[extint];
1751
1752         switch (cs) {
1753         case 4:
1754                 ret = platform_device_add_resources(pdev,
1755                                 at32_smc_cs4_resource,
1756                                 ARRAY_SIZE(at32_smc_cs4_resource));
1757                 if (ret)
1758                         return ret;
1759
1760                 select_peripheral(PE(21), PERIPH_A, 0); /* NCS4   -> OE_N  */
1761                 set_ebi_sfr_bits(HMATRIX_BIT(CS4A));
1762                 break;
1763         case 5:
1764                 ret = platform_device_add_resources(pdev,
1765                                 at32_smc_cs5_resource,
1766                                 ARRAY_SIZE(at32_smc_cs5_resource));
1767                 if (ret)
1768                         return ret;
1769
1770                 select_peripheral(PE(22), PERIPH_A, 0); /* NCS5   -> OE_N  */
1771                 set_ebi_sfr_bits(HMATRIX_BIT(CS5A));
1772                 break;
1773         default:
1774                 return -EINVAL;
1775         }
1776
1777         if (!common_pins_initialized) {
1778                 select_peripheral(PE(19), PERIPH_A, 0); /* CFCE1  -> CS0_N */
1779                 select_peripheral(PE(20), PERIPH_A, 0); /* CFCE2  -> CS1_N */
1780                 select_peripheral(PE(23), PERIPH_A, 0); /* CFRNW  -> DIR   */
1781                 select_peripheral(PE(24), PERIPH_A, 0); /* NWAIT  <- IORDY */
1782                 common_pins_initialized = true;
1783         }
1784
1785         at32_select_periph(extint_pin, GPIO_PERIPH_A, AT32_GPIOF_DEGLITCH);
1786
1787         pdev->resource[1].start = EIM_IRQ_BASE + extint;
1788         pdev->resource[1].end = pdev->resource[1].start;
1789
1790         return 0;
1791 }
1792
1793 struct platform_device *__init
1794 at32_add_device_ide(unsigned int id, unsigned int extint,
1795                     struct ide_platform_data *data)
1796 {
1797         struct platform_device *pdev;
1798
1799         pdev = platform_device_alloc("at32_ide", id);
1800         if (!pdev)
1801                 goto fail;
1802
1803         if (platform_device_add_data(pdev, data,
1804                                 sizeof(struct ide_platform_data)))
1805                 goto fail;
1806
1807         if (at32_init_ide_or_cf(pdev, data->cs, extint))
1808                 goto fail;
1809
1810         platform_device_add(pdev);
1811         return pdev;
1812
1813 fail:
1814         platform_device_put(pdev);
1815         return NULL;
1816 }
1817
1818 struct platform_device *__init
1819 at32_add_device_cf(unsigned int id, unsigned int extint,
1820                     struct cf_platform_data *data)
1821 {
1822         struct platform_device *pdev;
1823
1824         pdev = platform_device_alloc("at32_cf", id);
1825         if (!pdev)
1826                 goto fail;
1827
1828         if (platform_device_add_data(pdev, data,
1829                                 sizeof(struct cf_platform_data)))
1830                 goto fail;
1831
1832         if (at32_init_ide_or_cf(pdev, data->cs, extint))
1833                 goto fail;
1834
1835         if (data->detect_pin != GPIO_PIN_NONE)
1836                 at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH);
1837         if (data->reset_pin != GPIO_PIN_NONE)
1838                 at32_select_gpio(data->reset_pin, 0);
1839         if (data->vcc_pin != GPIO_PIN_NONE)
1840                 at32_select_gpio(data->vcc_pin, 0);
1841         /* READY is used as extint, so we can't select it as gpio */
1842
1843         platform_device_add(pdev);
1844         return pdev;
1845
1846 fail:
1847         platform_device_put(pdev);
1848         return NULL;
1849 }
1850 #endif
1851
1852 /* --------------------------------------------------------------------
1853  * AC97C
1854  * -------------------------------------------------------------------- */
1855 static struct resource atmel_ac97c0_resource[] __initdata = {
1856         PBMEM(0xfff02800),
1857         IRQ(29),
1858 };
1859 static struct clk atmel_ac97c0_pclk = {
1860         .name           = "pclk",
1861         .parent         = &pbb_clk,
1862         .mode           = pbb_clk_mode,
1863         .get_rate       = pbb_clk_get_rate,
1864         .index          = 10,
1865 };
1866
1867 struct platform_device *__init at32_add_device_ac97c(unsigned int id)
1868 {
1869         struct platform_device *pdev;
1870
1871         if (id != 0)
1872                 return NULL;
1873
1874         pdev = platform_device_alloc("atmel_ac97c", id);
1875         if (!pdev)
1876                 return NULL;
1877
1878         if (platform_device_add_resources(pdev, atmel_ac97c0_resource,
1879                                 ARRAY_SIZE(atmel_ac97c0_resource)))
1880                 goto err_add_resources;
1881
1882         select_peripheral(PB(20), PERIPH_B, 0); /* SYNC */
1883         select_peripheral(PB(21), PERIPH_B, 0); /* SDO  */
1884         select_peripheral(PB(22), PERIPH_B, 0); /* SDI  */
1885         select_peripheral(PB(23), PERIPH_B, 0); /* SCLK */
1886
1887         atmel_ac97c0_pclk.dev = &pdev->dev;
1888
1889         platform_device_add(pdev);
1890         return pdev;
1891
1892 err_add_resources:
1893         platform_device_put(pdev);
1894         return NULL;
1895 }
1896
1897 /* --------------------------------------------------------------------
1898  * ABDAC
1899  * -------------------------------------------------------------------- */
1900 static struct resource abdac0_resource[] __initdata = {
1901         PBMEM(0xfff02000),
1902         IRQ(27),
1903 };
1904 static struct clk abdac0_pclk = {
1905         .name           = "pclk",
1906         .parent         = &pbb_clk,
1907         .mode           = pbb_clk_mode,
1908         .get_rate       = pbb_clk_get_rate,
1909         .index          = 8,
1910 };
1911 static struct clk abdac0_sample_clk = {
1912         .name           = "sample_clk",
1913         .mode           = genclk_mode,
1914         .get_rate       = genclk_get_rate,
1915         .set_rate       = genclk_set_rate,
1916         .set_parent     = genclk_set_parent,
1917         .index          = 6,
1918 };
1919
1920 struct platform_device *__init at32_add_device_abdac(unsigned int id)
1921 {
1922         struct platform_device *pdev;
1923
1924         if (id != 0)
1925                 return NULL;
1926
1927         pdev = platform_device_alloc("abdac", id);
1928         if (!pdev)
1929                 return NULL;
1930
1931         if (platform_device_add_resources(pdev, abdac0_resource,
1932                                 ARRAY_SIZE(abdac0_resource)))
1933                 goto err_add_resources;
1934
1935         select_peripheral(PB(20), PERIPH_A, 0); /* DATA1        */
1936         select_peripheral(PB(21), PERIPH_A, 0); /* DATA0        */
1937         select_peripheral(PB(22), PERIPH_A, 0); /* DATAN1       */
1938         select_peripheral(PB(23), PERIPH_A, 0); /* DATAN0       */
1939
1940         abdac0_pclk.dev = &pdev->dev;
1941         abdac0_sample_clk.dev = &pdev->dev;
1942
1943         platform_device_add(pdev);
1944         return pdev;
1945
1946 err_add_resources:
1947         platform_device_put(pdev);
1948         return NULL;
1949 }
1950
1951 /* --------------------------------------------------------------------
1952  *  GCLK
1953  * -------------------------------------------------------------------- */
1954 static struct clk gclk0 = {
1955         .name           = "gclk0",
1956         .mode           = genclk_mode,
1957         .get_rate       = genclk_get_rate,
1958         .set_rate       = genclk_set_rate,
1959         .set_parent     = genclk_set_parent,
1960         .index          = 0,
1961 };
1962 static struct clk gclk1 = {
1963         .name           = "gclk1",
1964         .mode           = genclk_mode,
1965         .get_rate       = genclk_get_rate,
1966         .set_rate       = genclk_set_rate,
1967         .set_parent     = genclk_set_parent,
1968         .index          = 1,
1969 };
1970 static struct clk gclk2 = {
1971         .name           = "gclk2",
1972         .mode           = genclk_mode,
1973         .get_rate       = genclk_get_rate,
1974         .set_rate       = genclk_set_rate,
1975         .set_parent     = genclk_set_parent,
1976         .index          = 2,
1977 };
1978 static struct clk gclk3 = {
1979         .name           = "gclk3",
1980         .mode           = genclk_mode,
1981         .get_rate       = genclk_get_rate,
1982         .set_rate       = genclk_set_rate,
1983         .set_parent     = genclk_set_parent,
1984         .index          = 3,
1985 };
1986 static struct clk gclk4 = {
1987         .name           = "gclk4",
1988         .mode           = genclk_mode,
1989         .get_rate       = genclk_get_rate,
1990         .set_rate       = genclk_set_rate,
1991         .set_parent     = genclk_set_parent,
1992         .index          = 4,
1993 };
1994
1995 struct clk *at32_clock_list[] = {
1996         &osc32k,
1997         &osc0,
1998         &osc1,
1999         &pll0,
2000         &pll1,
2001         &cpu_clk,
2002         &hsb_clk,
2003         &pba_clk,
2004         &pbb_clk,
2005         &at32_pm_pclk,
2006         &at32_intc0_pclk,
2007         &hmatrix_clk,
2008         &ebi_clk,
2009         &hramc_clk,
2010         &sdramc_clk,
2011         &smc0_pclk,
2012         &smc0_mck,
2013         &pdc_hclk,
2014         &pdc_pclk,
2015         &dmaca0_hclk,
2016         &pico_clk,
2017         &pio0_mck,
2018         &pio1_mck,
2019         &pio2_mck,
2020         &pio3_mck,
2021         &pio4_mck,
2022         &at32_tcb0_t0_clk,
2023         &at32_tcb1_t0_clk,
2024         &atmel_psif0_pclk,
2025         &atmel_psif1_pclk,
2026         &atmel_usart0_usart,
2027         &atmel_usart1_usart,
2028         &atmel_usart2_usart,
2029         &atmel_usart3_usart,
2030         &atmel_pwm0_mck,
2031 #if defined(CONFIG_CPU_AT32AP7000)
2032         &macb0_hclk,
2033         &macb0_pclk,
2034         &macb1_hclk,
2035         &macb1_pclk,
2036 #endif
2037         &atmel_spi0_spi_clk,
2038         &atmel_spi1_spi_clk,
2039         &atmel_twi0_pclk,
2040         &atmel_mci0_pclk,
2041 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2042         &atmel_lcdfb0_hck1,
2043         &atmel_lcdfb0_pixclk,
2044 #endif
2045         &ssc0_pclk,
2046         &ssc1_pclk,
2047         &ssc2_pclk,
2048         &usba0_hclk,
2049         &usba0_pclk,
2050         &atmel_ac97c0_pclk,
2051         &abdac0_pclk,
2052         &abdac0_sample_clk,
2053         &gclk0,
2054         &gclk1,
2055         &gclk2,
2056         &gclk3,
2057         &gclk4,
2058 };
2059 unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
2060
2061 void __init setup_platform(void)
2062 {
2063         u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
2064         int i;
2065
2066         if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
2067                 main_clock = &pll0;
2068                 cpu_clk.parent = &pll0;
2069         } else {
2070                 main_clock = &osc0;
2071                 cpu_clk.parent = &osc0;
2072         }
2073
2074         if (pm_readl(PLL0) & PM_BIT(PLLOSC))
2075                 pll0.parent = &osc1;
2076         if (pm_readl(PLL1) & PM_BIT(PLLOSC))
2077                 pll1.parent = &osc1;
2078
2079         genclk_init_parent(&gclk0);
2080         genclk_init_parent(&gclk1);
2081         genclk_init_parent(&gclk2);
2082         genclk_init_parent(&gclk3);
2083         genclk_init_parent(&gclk4);
2084 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2085         genclk_init_parent(&atmel_lcdfb0_pixclk);
2086 #endif
2087         genclk_init_parent(&abdac0_sample_clk);
2088
2089         /*
2090          * Turn on all clocks that have at least one user already, and
2091          * turn off everything else. We only do this for module
2092          * clocks, and even though it isn't particularly pretty to
2093          * check the address of the mode function, it should do the
2094          * trick...
2095          */
2096         for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) {
2097                 struct clk *clk = at32_clock_list[i];
2098
2099                 if (clk->users == 0)
2100                         continue;
2101
2102                 if (clk->mode == &cpu_clk_mode)
2103                         cpu_mask |= 1 << clk->index;
2104                 else if (clk->mode == &hsb_clk_mode)
2105                         hsb_mask |= 1 << clk->index;
2106                 else if (clk->mode == &pba_clk_mode)
2107                         pba_mask |= 1 << clk->index;
2108                 else if (clk->mode == &pbb_clk_mode)
2109                         pbb_mask |= 1 << clk->index;
2110         }
2111
2112         pm_writel(CPU_MASK, cpu_mask);
2113         pm_writel(HSB_MASK, hsb_mask);
2114         pm_writel(PBA_MASK, pba_mask);
2115         pm_writel(PBB_MASK, pbb_mask);
2116
2117         /* Initialize the port muxes */
2118         at32_init_pio(&pio0_device);
2119         at32_init_pio(&pio1_device);
2120         at32_init_pio(&pio2_device);
2121         at32_init_pio(&pio3_device);
2122         at32_init_pio(&pio4_device);
2123 }
2124
2125 struct gen_pool *sram_pool;
2126
2127 static int __init sram_init(void)
2128 {
2129         struct gen_pool *pool;
2130
2131         /* 1KiB granularity */
2132         pool = gen_pool_create(10, -1);
2133         if (!pool)
2134                 goto fail;
2135
2136         if (gen_pool_add(pool, 0x24000000, 0x8000, -1))
2137                 goto err_pool_add;
2138
2139         sram_pool = pool;
2140         return 0;
2141
2142 err_pool_add:
2143         gen_pool_destroy(pool);
2144 fail:
2145         pr_err("Failed to create SRAM pool\n");
2146         return -ENOMEM;
2147 }
2148 core_initcall(sram_init);