arch/avr32/mach-at32ap/at32ap7000.c

   1 /*
   2  * Copyright (C) 2005-2006 Atmel Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 #include <linux/clk.h>
   9 #include <linux/fb.h>
  10 #include <linux/init.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/spi/spi.h>
  14
  15 #include <asm/io.h>
  16
  17 #include <asm/arch/at32ap7000.h>
  18 #include <asm/arch/board.h>
  19 #include <asm/arch/portmux.h>
  20
  21 #include <video/atmel_lcdc.h>
  22
  23 #include "clock.h"
  24 #include "hmatrix.h"
  25 #include "pio.h"
  26 #include "pm.h"
  27
  28
  29 #define PBMEM(base)                                     \
  30         {                                               \
  31                 .start          = base,                 \
  32                 .end            = base + 0x3ff,         \
  33                 .flags          = IORESOURCE_MEM,       \
  34         }
  35 #define IRQ(num)                                        \
  36         {                                               \
  37                 .start          = num,                  \
  38                 .end            = num,                  \
  39                 .flags          = IORESOURCE_IRQ,       \
  40         }
  41 #define NAMED_IRQ(num, _name)                           \
  42         {                                               \
  43                 .start          = num,                  \
  44                 .end            = num,                  \
  45                 .name           = _name,                \
  46                 .flags          = IORESOURCE_IRQ,       \
  47         }
  48
  49 /* REVISIT these assume *every* device supports DMA, but several
  50  * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
  51  */
  52 #define DEFINE_DEV(_name, _id)                                  \
  53 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK;              \
  54 static struct platform_device _name##_id##_device = {           \
  55         .name           = #_name,                               \
  56         .id             = _id,                                  \
  57         .dev            = {                                     \
  58                 .dma_mask = &_name##_id##_dma_mask,             \
  59                 .coherent_dma_mask = DMA_32BIT_MASK,            \
  60         },                                                      \
  61         .resource       = _name##_id##_resource,                \
  62         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
  63 }
  64 #define DEFINE_DEV_DATA(_name, _id)                             \
  65 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK;              \
  66 static struct platform_device _name##_id##_device = {           \
  67         .name           = #_name,                               \
  68         .id             = _id,                                  \
  69         .dev            = {                                     \
  70                 .dma_mask = &_name##_id##_dma_mask,             \
  71                 .platform_data  = &_name##_id##_data,           \
  72                 .coherent_dma_mask = DMA_32BIT_MASK,            \
  73         },                                                      \
  74         .resource       = _name##_id##_resource,                \
  75         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
  76 }
  77
  78 #define select_peripheral(pin, periph, flags)                   \
  79         at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags)
  80
  81 #define DEV_CLK(_name, devname, bus, _index)                    \
  82 static struct clk devname##_##_name = {                         \
  83         .name           = #_name,                               \
  84         .dev            = &devname##_device.dev,                \
  85         .parent         = &bus##_clk,                           \
  86         .mode           = bus##_clk_mode,                       \
  87         .get_rate       = bus##_clk_get_rate,                   \
  88         .index          = _index,                               \
  89 }
  90
  91 static DEFINE_SPINLOCK(pm_lock);
  92
  93 unsigned long at32ap7000_osc_rates[3] = {
  94         [0] = 32768,
  95         /* FIXME: these are ATSTK1002-specific */
  96         [1] = 20000000,
  97         [2] = 12000000,
  98 };
  99
 100 static unsigned long osc_get_rate(struct clk *clk)
 101 {
 102         return at32ap7000_osc_rates[clk->index];
 103 }
 104
 105 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
 106 {
 107         unsigned long div, mul, rate;
 108
 109         if (!(control & PM_BIT(PLLEN)))
 110                 return 0;
 111
 112         div = PM_BFEXT(PLLDIV, control) + 1;
 113         mul = PM_BFEXT(PLLMUL, control) + 1;
 114
 115         rate = clk->parent->get_rate(clk->parent);
 116         rate = (rate + div / 2) / div;
 117         rate *= mul;
 118
 119         return rate;
 120 }
 121
 122 static unsigned long pll0_get_rate(struct clk *clk)
 123 {
 124         u32 control;
 125
 126         control = pm_readl(PLL0);
 127
 128         return pll_get_rate(clk, control);
 129 }
 130
 131 static unsigned long pll1_get_rate(struct clk *clk)
 132 {
 133         u32 control;
 134
 135         control = pm_readl(PLL1);
 136
 137         return pll_get_rate(clk, control);
 138 }
 139
 140 /*
 141  * The AT32AP7000 has five primary clock sources: One 32kHz
 142  * oscillator, two crystal oscillators and two PLLs.
 143  */
 144 static struct clk osc32k = {
 145         .name           = "osc32k",
 146         .get_rate       = osc_get_rate,
 147         .users          = 1,
 148         .index          = 0,
 149 };
 150 static struct clk osc0 = {
 151         .name           = "osc0",
 152         .get_rate       = osc_get_rate,
 153         .users          = 1,
 154         .index          = 1,
 155 };
 156 static struct clk osc1 = {
 157         .name           = "osc1",
 158         .get_rate       = osc_get_rate,
 159         .index          = 2,
 160 };
 161 static struct clk pll0 = {
 162         .name           = "pll0",
 163         .get_rate       = pll0_get_rate,
 164         .parent         = &osc0,
 165 };
 166 static struct clk pll1 = {
 167         .name           = "pll1",
 168         .get_rate       = pll1_get_rate,
 169         .parent         = &osc0,
 170 };
 171
 172 /*
 173  * The main clock can be either osc0 or pll0.  The boot loader may
 174  * have chosen one for us, so we don't really know which one until we
 175  * have a look at the SM.
 176  */
 177 static struct clk *main_clock;
 178
 179 /*
 180  * Synchronous clocks are generated from the main clock. The clocks
 181  * must satisfy the constraint
 182  *   fCPU >= fHSB >= fPB
 183  * i.e. each clock must not be faster than its parent.
 184  */
 185 static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
 186 {
 187         return main_clock->get_rate(main_clock) >> shift;
 188 };
 189
 190 static void cpu_clk_mode(struct clk *clk, int enabled)
 191 {
 192         unsigned long flags;
 193         u32 mask;
 194
 195         spin_lock_irqsave(&pm_lock, flags);
 196         mask = pm_readl(CPU_MASK);
 197         if (enabled)
 198                 mask |= 1 << clk->index;
 199         else
 200                 mask &= ~(1 << clk->index);
 201         pm_writel(CPU_MASK, mask);
 202         spin_unlock_irqrestore(&pm_lock, flags);
 203 }
 204
 205 static unsigned long cpu_clk_get_rate(struct clk *clk)
 206 {
 207         unsigned long cksel, shift = 0;
 208
 209         cksel = pm_readl(CKSEL);
 210         if (cksel & PM_BIT(CPUDIV))
 211                 shift = PM_BFEXT(CPUSEL, cksel) + 1;
 212
 213         return bus_clk_get_rate(clk, shift);
 214 }
 215
 216 static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
 217 {
 218         u32 control;
 219         unsigned long parent_rate, child_div, actual_rate, div;
 220
 221         parent_rate = clk->parent->get_rate(clk->parent);
 222         control = pm_readl(CKSEL);
 223
 224         if (control & PM_BIT(HSBDIV))
 225                 child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
 226         else
 227                 child_div = 1;
 228
 229         if (rate > 3 * (parent_rate / 4) || child_div == 1) {
 230                 actual_rate = parent_rate;
 231                 control &= ~PM_BIT(CPUDIV);
 232         } else {
 233                 unsigned int cpusel;
 234                 div = (parent_rate + rate / 2) / rate;
 235                 if (div > child_div)
 236                         div = child_div;
 237                 cpusel = (div > 1) ? (fls(div) - 2) : 0;
 238                 control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
 239                 actual_rate = parent_rate / (1 << (cpusel + 1));
 240         }
 241
 242         pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
 243                         clk->name, rate, actual_rate);
 244
 245         if (apply)
 246                 pm_writel(CKSEL, control);
 247
 248         return actual_rate;
 249 }
 250
 251 static void hsb_clk_mode(struct clk *clk, int enabled)
 252 {
 253         unsigned long flags;
 254         u32 mask;
 255
 256         spin_lock_irqsave(&pm_lock, flags);
 257         mask = pm_readl(HSB_MASK);
 258         if (enabled)
 259                 mask |= 1 << clk->index;
 260         else
 261                 mask &= ~(1 << clk->index);
 262         pm_writel(HSB_MASK, mask);
 263         spin_unlock_irqrestore(&pm_lock, flags);
 264 }
 265
 266 static unsigned long hsb_clk_get_rate(struct clk *clk)
 267 {
 268         unsigned long cksel, shift = 0;
 269
 270         cksel = pm_readl(CKSEL);
 271         if (cksel & PM_BIT(HSBDIV))
 272                 shift = PM_BFEXT(HSBSEL, cksel) + 1;
 273
 274         return bus_clk_get_rate(clk, shift);
 275 }
 276
 277 static void pba_clk_mode(struct clk *clk, int enabled)
 278 {
 279         unsigned long flags;
 280         u32 mask;
 281
 282         spin_lock_irqsave(&pm_lock, flags);
 283         mask = pm_readl(PBA_MASK);
 284         if (enabled)
 285                 mask |= 1 << clk->index;
 286         else
 287                 mask &= ~(1 << clk->index);
 288         pm_writel(PBA_MASK, mask);
 289         spin_unlock_irqrestore(&pm_lock, flags);
 290 }
 291
 292 static unsigned long pba_clk_get_rate(struct clk *clk)
 293 {
 294         unsigned long cksel, shift = 0;
 295
 296         cksel = pm_readl(CKSEL);
 297         if (cksel & PM_BIT(PBADIV))
 298                 shift = PM_BFEXT(PBASEL, cksel) + 1;
 299
 300         return bus_clk_get_rate(clk, shift);
 301 }
 302
 303 static void pbb_clk_mode(struct clk *clk, int enabled)
 304 {
 305         unsigned long flags;
 306         u32 mask;
 307
 308         spin_lock_irqsave(&pm_lock, flags);
 309         mask = pm_readl(PBB_MASK);
 310         if (enabled)
 311                 mask |= 1 << clk->index;
 312         else
 313                 mask &= ~(1 << clk->index);
 314         pm_writel(PBB_MASK, mask);
 315         spin_unlock_irqrestore(&pm_lock, flags);
 316 }
 317
 318 static unsigned long pbb_clk_get_rate(struct clk *clk)
 319 {
 320         unsigned long cksel, shift = 0;
 321
 322         cksel = pm_readl(CKSEL);
 323         if (cksel & PM_BIT(PBBDIV))
 324                 shift = PM_BFEXT(PBBSEL, cksel) + 1;
 325
 326         return bus_clk_get_rate(clk, shift);
 327 }
 328
 329 static struct clk cpu_clk = {
 330         .name           = "cpu",
 331         .get_rate       = cpu_clk_get_rate,
 332         .set_rate       = cpu_clk_set_rate,
 333         .users          = 1,
 334 };
 335 static struct clk hsb_clk = {
 336         .name           = "hsb",
 337         .parent         = &cpu_clk,
 338         .get_rate       = hsb_clk_get_rate,
 339 };
 340 static struct clk pba_clk = {
 341         .name           = "pba",
 342         .parent         = &hsb_clk,
 343         .mode           = hsb_clk_mode,
 344         .get_rate       = pba_clk_get_rate,
 345         .index          = 1,
 346 };
 347 static struct clk pbb_clk = {
 348         .name           = "pbb",
 349         .parent         = &hsb_clk,
 350         .mode           = hsb_clk_mode,
 351         .get_rate       = pbb_clk_get_rate,
 352         .users          = 1,
 353         .index          = 2,
 354 };
 355
 356 /* --------------------------------------------------------------------
 357  *  Generic Clock operations
 358  * -------------------------------------------------------------------- */
 359
 360 static void genclk_mode(struct clk *clk, int enabled)
 361 {
 362         u32 control;
 363
 364         control = pm_readl(GCCTRL(clk->index));
 365         if (enabled)
 366                 control |= PM_BIT(CEN);
 367         else
 368                 control &= ~PM_BIT(CEN);
 369         pm_writel(GCCTRL(clk->index), control);
 370 }
 371
 372 static unsigned long genclk_get_rate(struct clk *clk)
 373 {
 374         u32 control;
 375         unsigned long div = 1;
 376
 377         control = pm_readl(GCCTRL(clk->index));
 378         if (control & PM_BIT(DIVEN))
 379                 div = 2 * (PM_BFEXT(DIV, control) + 1);
 380
 381         return clk->parent->get_rate(clk->parent) / div;
 382 }
 383
 384 static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
 385 {
 386         u32 control;
 387         unsigned long parent_rate, actual_rate, div;
 388
 389         parent_rate = clk->parent->get_rate(clk->parent);
 390         control = pm_readl(GCCTRL(clk->index));
 391
 392         if (rate > 3 * parent_rate / 4) {
 393                 actual_rate = parent_rate;
 394                 control &= ~PM_BIT(DIVEN);
 395         } else {
 396                 div = (parent_rate + rate) / (2 * rate) - 1;
 397                 control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
 398                 actual_rate = parent_rate / (2 * (div + 1));
 399         }
 400
 401         dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
 402                 clk->name, rate, actual_rate);
 403
 404         if (apply)
 405                 pm_writel(GCCTRL(clk->index), control);
 406
 407         return actual_rate;
 408 }
 409
 410 int genclk_set_parent(struct clk *clk, struct clk *parent)
 411 {
 412         u32 control;
 413
 414         dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
 415                 clk->name, parent->name, clk->parent->name);
 416
 417         control = pm_readl(GCCTRL(clk->index));
 418
 419         if (parent == &osc1 || parent == &pll1)
 420                 control |= PM_BIT(OSCSEL);
 421         else if (parent == &osc0 || parent == &pll0)
 422                 control &= ~PM_BIT(OSCSEL);
 423         else
 424                 return -EINVAL;
 425
 426         if (parent == &pll0 || parent == &pll1)
 427                 control |= PM_BIT(PLLSEL);
 428         else
 429                 control &= ~PM_BIT(PLLSEL);
 430
 431         pm_writel(GCCTRL(clk->index), control);
 432         clk->parent = parent;
 433
 434         return 0;
 435 }
 436
 437 static void __init genclk_init_parent(struct clk *clk)
 438 {
 439         u32 control;
 440         struct clk *parent;
 441
 442         BUG_ON(clk->index > 7);
 443
 444         control = pm_readl(GCCTRL(clk->index));
 445         if (control & PM_BIT(OSCSEL))
 446                 parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
 447         else
 448                 parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
 449
 450         clk->parent = parent;
 451 }
 452
 453 /* --------------------------------------------------------------------
 454  *  System peripherals
 455  * -------------------------------------------------------------------- */
 456 static struct resource at32_pm0_resource[] = {
 457         {
 458                 .start  = 0xfff00000,
 459                 .end    = 0xfff0007f,
 460                 .flags  = IORESOURCE_MEM,
 461         },
 462         IRQ(20),
 463 };
 464
 465 static struct resource at32ap700x_rtc0_resource[] = {
 466         {
 467                 .start  = 0xfff00080,
 468                 .end    = 0xfff000af,
 469                 .flags  = IORESOURCE_MEM,
 470         },
 471         IRQ(21),
 472 };
 473
 474 static struct resource at32_wdt0_resource[] = {
 475         {
 476                 .start  = 0xfff000b0,
 477                 .end    = 0xfff000bf,
 478                 .flags  = IORESOURCE_MEM,
 479         },
 480 };
 481
 482 static struct resource at32_eic0_resource[] = {
 483         {
 484                 .start  = 0xfff00100,
 485                 .end    = 0xfff0013f,
 486                 .flags  = IORESOURCE_MEM,
 487         },
 488         IRQ(19),
 489 };
 490
 491 DEFINE_DEV(at32_pm, 0);
 492 DEFINE_DEV(at32ap700x_rtc, 0);
 493 DEFINE_DEV(at32_wdt, 0);
 494 DEFINE_DEV(at32_eic, 0);
 495
 496 /*
 497  * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
 498  * is always running.
 499  */
 500 static struct clk at32_pm_pclk = {
 501         .name           = "pclk",
 502         .dev            = &at32_pm0_device.dev,
 503         .parent         = &pbb_clk,
 504         .mode           = pbb_clk_mode,
 505         .get_rate       = pbb_clk_get_rate,
 506         .users          = 1,
 507         .index          = 0,
 508 };
 509
 510 static struct resource intc0_resource[] = {
 511         PBMEM(0xfff00400),
 512 };
 513 struct platform_device at32_intc0_device = {
 514         .name           = "intc",
 515         .id             = 0,
 516         .resource       = intc0_resource,
 517         .num_resources  = ARRAY_SIZE(intc0_resource),
 518 };
 519 DEV_CLK(pclk, at32_intc0, pbb, 1);
 520
 521 static struct clk ebi_clk = {
 522         .name           = "ebi",
 523         .parent         = &hsb_clk,
 524         .mode           = hsb_clk_mode,
 525         .get_rate       = hsb_clk_get_rate,
 526         .users          = 1,
 527 };
 528 static struct clk hramc_clk = {
 529         .name           = "hramc",
 530         .parent         = &hsb_clk,
 531         .mode           = hsb_clk_mode,
 532         .get_rate       = hsb_clk_get_rate,
 533         .users          = 1,
 534         .index          = 3,
 535 };
 536
 537 static struct resource smc0_resource[] = {
 538         PBMEM(0xfff03400),
 539 };
 540 DEFINE_DEV(smc, 0);
 541 DEV_CLK(pclk, smc0, pbb, 13);
 542 DEV_CLK(mck, smc0, hsb, 0);
 543
 544 static struct platform_device pdc_device = {
 545         .name           = "pdc",
 546         .id             = 0,
 547 };
 548 DEV_CLK(hclk, pdc, hsb, 4);
 549 DEV_CLK(pclk, pdc, pba, 16);
 550
 551 static struct clk pico_clk = {
 552         .name           = "pico",
 553         .parent         = &cpu_clk,
 554         .mode           = cpu_clk_mode,
 555         .get_rate       = cpu_clk_get_rate,
 556         .users          = 1,
 557 };
 558
 559 static struct resource dmaca0_resource[] = {
 560         {
 561                 .start  = 0xff200000,
 562                 .end    = 0xff20ffff,
 563                 .flags  = IORESOURCE_MEM,
 564         },
 565         IRQ(2),
 566 };
 567 DEFINE_DEV(dmaca, 0);
 568 DEV_CLK(hclk, dmaca0, hsb, 10);
 569
 570 /* --------------------------------------------------------------------
 571  * HMATRIX
 572  * -------------------------------------------------------------------- */
 573
 574 static struct clk hmatrix_clk = {
 575         .name           = "hmatrix_clk",
 576         .parent         = &pbb_clk,
 577         .mode           = pbb_clk_mode,
 578         .get_rate       = pbb_clk_get_rate,
 579         .index          = 2,
 580         .users          = 1,
 581 };
 582 #define HMATRIX_BASE    ((void __iomem *)0xfff00800)
 583
 584 #define hmatrix_readl(reg)                                      \
 585         __raw_readl((HMATRIX_BASE) + HMATRIX_##reg)
 586 #define hmatrix_writel(reg,value)                               \
 587         __raw_writel((value), (HMATRIX_BASE) + HMATRIX_##reg)
 588
 589 /*
 590  * Set bits in the HMATRIX Special Function Register (SFR) used by the
 591  * External Bus Interface (EBI). This can be used to enable special
 592  * features like CompactFlash support, NAND Flash support, etc. on
 593  * certain chipselects.
 594  */
 595 static inline void set_ebi_sfr_bits(u32 mask)
 596 {
 597         u32 sfr;
 598
 599         clk_enable(&hmatrix_clk);
 600         sfr = hmatrix_readl(SFR4);
 601         sfr |= mask;
 602         hmatrix_writel(SFR4, sfr);
 603         clk_disable(&hmatrix_clk);
 604 }
 605
 606 /* --------------------------------------------------------------------
 607  *  System Timer/Counter (TC)
 608  * -------------------------------------------------------------------- */
 609 static struct resource at32_systc0_resource[] = {
 610         PBMEM(0xfff00c00),
 611         IRQ(22),
 612 };
 613 struct platform_device at32_systc0_device = {
 614         .name           = "systc",
 615         .id             = 0,
 616         .resource       = at32_systc0_resource,
 617         .num_resources  = ARRAY_SIZE(at32_systc0_resource),
 618 };
 619 DEV_CLK(pclk, at32_systc0, pbb, 3);
 620
 621 /* --------------------------------------------------------------------
 622  *  PIO
 623  * -------------------------------------------------------------------- */
 624
 625 static struct resource pio0_resource[] = {
 626         PBMEM(0xffe02800),
 627         IRQ(13),
 628 };
 629 DEFINE_DEV(pio, 0);
 630 DEV_CLK(mck, pio0, pba, 10);
 631
 632 static struct resource pio1_resource[] = {
 633         PBMEM(0xffe02c00),
 634         IRQ(14),
 635 };
 636 DEFINE_DEV(pio, 1);
 637 DEV_CLK(mck, pio1, pba, 11);
 638
 639 static struct resource pio2_resource[] = {
 640         PBMEM(0xffe03000),
 641         IRQ(15),
 642 };
 643 DEFINE_DEV(pio, 2);
 644 DEV_CLK(mck, pio2, pba, 12);
 645
 646 static struct resource pio3_resource[] = {
 647         PBMEM(0xffe03400),
 648         IRQ(16),
 649 };
 650 DEFINE_DEV(pio, 3);
 651 DEV_CLK(mck, pio3, pba, 13);
 652
 653 static struct resource pio4_resource[] = {
 654         PBMEM(0xffe03800),
 655         IRQ(17),
 656 };
 657 DEFINE_DEV(pio, 4);
 658 DEV_CLK(mck, pio4, pba, 14);
 659
 660 void __init at32_add_system_devices(void)
 661 {
 662         platform_device_register(&at32_pm0_device);
 663         platform_device_register(&at32_intc0_device);
 664         platform_device_register(&at32ap700x_rtc0_device);
 665         platform_device_register(&at32_wdt0_device);
 666         platform_device_register(&at32_eic0_device);
 667         platform_device_register(&smc0_device);
 668         platform_device_register(&pdc_device);
 669         platform_device_register(&dmaca0_device);
 670
 671         platform_device_register(&at32_systc0_device);
 672
 673         platform_device_register(&pio0_device);
 674         platform_device_register(&pio1_device);
 675         platform_device_register(&pio2_device);
 676         platform_device_register(&pio3_device);
 677         platform_device_register(&pio4_device);
 678 }
 679
 680 /* --------------------------------------------------------------------
 681  *  USART
 682  * -------------------------------------------------------------------- */
 683
 684 static struct atmel_uart_data atmel_usart0_data = {
 685         .use_dma_tx     = 1,
 686         .use_dma_rx     = 1,
 687 };
 688 static struct resource atmel_usart0_resource[] = {
 689         PBMEM(0xffe00c00),
 690         IRQ(6),
 691 };
 692 DEFINE_DEV_DATA(atmel_usart, 0);
 693 DEV_CLK(usart, atmel_usart0, pba, 4);
 694
 695 static struct atmel_uart_data atmel_usart1_data = {
 696         .use_dma_tx     = 1,
 697         .use_dma_rx     = 1,
 698 };
 699 static struct resource atmel_usart1_resource[] = {
 700         PBMEM(0xffe01000),
 701         IRQ(7),
 702 };
 703 DEFINE_DEV_DATA(atmel_usart, 1);
 704 DEV_CLK(usart, atmel_usart1, pba, 4);
 705
 706 static struct atmel_uart_data atmel_usart2_data = {
 707         .use_dma_tx     = 1,
 708         .use_dma_rx     = 1,
 709 };
 710 static struct resource atmel_usart2_resource[] = {
 711         PBMEM(0xffe01400),
 712         IRQ(8),
 713 };
 714 DEFINE_DEV_DATA(atmel_usart, 2);
 715 DEV_CLK(usart, atmel_usart2, pba, 5);
 716
 717 static struct atmel_uart_data atmel_usart3_data = {
 718         .use_dma_tx     = 1,
 719         .use_dma_rx     = 1,
 720 };
 721 static struct resource atmel_usart3_resource[] = {
 722         PBMEM(0xffe01800),
 723         IRQ(9),
 724 };
 725 DEFINE_DEV_DATA(atmel_usart, 3);
 726 DEV_CLK(usart, atmel_usart3, pba, 6);
 727
 728 static inline void configure_usart0_pins(void)
 729 {
 730         select_peripheral(PA(8),  PERIPH_B, 0); /* RXD  */
 731         select_peripheral(PA(9),  PERIPH_B, 0); /* TXD  */
 732 }
 733
 734 static inline void configure_usart1_pins(void)
 735 {
 736         select_peripheral(PA(17), PERIPH_A, 0); /* RXD  */
 737         select_peripheral(PA(18), PERIPH_A, 0); /* TXD  */
 738 }
 739
 740 static inline void configure_usart2_pins(void)
 741 {
 742         select_peripheral(PB(26), PERIPH_B, 0); /* RXD  */
 743         select_peripheral(PB(27), PERIPH_B, 0); /* TXD  */
 744 }
 745
 746 static inline void configure_usart3_pins(void)
 747 {
 748         select_peripheral(PB(18), PERIPH_B, 0); /* RXD  */
 749         select_peripheral(PB(17), PERIPH_B, 0); /* TXD  */
 750 }
 751
 752 static struct platform_device *__initdata at32_usarts[4];
 753
 754 void __init at32_map_usart(unsigned int hw_id, unsigned int line)
 755 {
 756         struct platform_device *pdev;
 757
 758         switch (hw_id) {
 759         case 0:
 760                 pdev = &atmel_usart0_device;
 761                 configure_usart0_pins();
 762                 break;
 763         case 1:
 764                 pdev = &atmel_usart1_device;
 765                 configure_usart1_pins();
 766                 break;
 767         case 2:
 768                 pdev = &atmel_usart2_device;
 769                 configure_usart2_pins();
 770                 break;
 771         case 3:
 772                 pdev = &atmel_usart3_device;
 773                 configure_usart3_pins();
 774                 break;
 775         default:
 776                 return;
 777         }
 778
 779         if (PXSEG(pdev->resource[0].start) == P4SEG) {
 780                 /* Addresses in the P4 segment are permanently mapped 1:1 */
 781                 struct atmel_uart_data *data = pdev->dev.platform_data;
 782                 data->regs = (void __iomem *)pdev->resource[0].start;
 783         }
 784
 785         pdev->id = line;
 786         at32_usarts[line] = pdev;
 787 }
 788
 789 struct platform_device *__init at32_add_device_usart(unsigned int id)
 790 {
 791         platform_device_register(at32_usarts[id]);
 792         return at32_usarts[id];
 793 }
 794
 795 struct platform_device *atmel_default_console_device;
 796
 797 void __init at32_setup_serial_console(unsigned int usart_id)
 798 {
 799         atmel_default_console_device = at32_usarts[usart_id];
 800 }
 801
 802 /* --------------------------------------------------------------------
 803  *  Ethernet
 804  * -------------------------------------------------------------------- */
 805
 806 static struct eth_platform_data macb0_data;
 807 static struct resource macb0_resource[] = {
 808         PBMEM(0xfff01800),
 809         IRQ(25),
 810 };
 811 DEFINE_DEV_DATA(macb, 0);
 812 DEV_CLK(hclk, macb0, hsb, 8);
 813 DEV_CLK(pclk, macb0, pbb, 6);
 814
 815 static struct eth_platform_data macb1_data;
 816 static struct resource macb1_resource[] = {
 817         PBMEM(0xfff01c00),
 818         IRQ(26),
 819 };
 820 DEFINE_DEV_DATA(macb, 1);
 821 DEV_CLK(hclk, macb1, hsb, 9);
 822 DEV_CLK(pclk, macb1, pbb, 7);
 823
 824 struct platform_device *__init
 825 at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
 826 {
 827         struct platform_device *pdev;
 828
 829         switch (id) {
 830         case 0:
 831                 pdev = &macb0_device;
 832
 833                 select_peripheral(PC(3),  PERIPH_A, 0); /* TXD0 */
 834                 select_peripheral(PC(4),  PERIPH_A, 0); /* TXD1 */
 835                 select_peripheral(PC(7),  PERIPH_A, 0); /* TXEN */
 836                 select_peripheral(PC(8),  PERIPH_A, 0); /* TXCK */
 837                 select_peripheral(PC(9),  PERIPH_A, 0); /* RXD0 */
 838                 select_peripheral(PC(10), PERIPH_A, 0); /* RXD1 */
 839                 select_peripheral(PC(13), PERIPH_A, 0); /* RXER */
 840                 select_peripheral(PC(15), PERIPH_A, 0); /* RXDV */
 841                 select_peripheral(PC(16), PERIPH_A, 0); /* MDC  */
 842                 select_peripheral(PC(17), PERIPH_A, 0); /* MDIO */
 843
 844                 if (!data->is_rmii) {
 845                         select_peripheral(PC(0),  PERIPH_A, 0); /* COL  */
 846                         select_peripheral(PC(1),  PERIPH_A, 0); /* CRS  */
 847                         select_peripheral(PC(2),  PERIPH_A, 0); /* TXER */
 848                         select_peripheral(PC(5),  PERIPH_A, 0); /* TXD2 */
 849                         select_peripheral(PC(6),  PERIPH_A, 0); /* TXD3 */
 850                         select_peripheral(PC(11), PERIPH_A, 0); /* RXD2 */
 851                         select_peripheral(PC(12), PERIPH_A, 0); /* RXD3 */
 852                         select_peripheral(PC(14), PERIPH_A, 0); /* RXCK */
 853                         select_peripheral(PC(18), PERIPH_A, 0); /* SPD  */
 854                 }
 855                 break;
 856
 857         case 1:
 858                 pdev = &macb1_device;
 859
 860                 select_peripheral(PD(13), PERIPH_B, 0);         /* TXD0 */
 861                 select_peripheral(PD(14), PERIPH_B, 0);         /* TXD1 */
 862                 select_peripheral(PD(11), PERIPH_B, 0);         /* TXEN */
 863                 select_peripheral(PD(12), PERIPH_B, 0);         /* TXCK */
 864                 select_peripheral(PD(10), PERIPH_B, 0);         /* RXD0 */
 865                 select_peripheral(PD(6),  PERIPH_B, 0);         /* RXD1 */
 866                 select_peripheral(PD(5),  PERIPH_B, 0);         /* RXER */
 867                 select_peripheral(PD(4),  PERIPH_B, 0);         /* RXDV */
 868                 select_peripheral(PD(3),  PERIPH_B, 0);         /* MDC  */
 869                 select_peripheral(PD(2),  PERIPH_B, 0);         /* MDIO */
 870
 871                 if (!data->is_rmii) {
 872                         select_peripheral(PC(19), PERIPH_B, 0); /* COL  */
 873                         select_peripheral(PC(23), PERIPH_B, 0); /* CRS  */
 874                         select_peripheral(PC(26), PERIPH_B, 0); /* TXER */
 875                         select_peripheral(PC(27), PERIPH_B, 0); /* TXD2 */
 876                         select_peripheral(PC(28), PERIPH_B, 0); /* TXD3 */
 877                         select_peripheral(PC(29), PERIPH_B, 0); /* RXD2 */
 878                         select_peripheral(PC(30), PERIPH_B, 0); /* RXD3 */
 879                         select_peripheral(PC(24), PERIPH_B, 0); /* RXCK */
 880                         select_peripheral(PD(15), PERIPH_B, 0); /* SPD  */
 881                 }
 882                 break;
 883
 884         default:
 885                 return NULL;
 886         }
 887
 888         memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
 889         platform_device_register(pdev);
 890
 891         return pdev;
 892 }
 893
 894 /* --------------------------------------------------------------------
 895  *  SPI
 896  * -------------------------------------------------------------------- */
 897 static struct resource atmel_spi0_resource[] = {
 898         PBMEM(0xffe00000),
 899         IRQ(3),
 900 };
 901 DEFINE_DEV(atmel_spi, 0);
 902 DEV_CLK(spi_clk, atmel_spi0, pba, 0);
 903
 904 static struct resource atmel_spi1_resource[] = {
 905         PBMEM(0xffe00400),
 906         IRQ(4),
 907 };
 908 DEFINE_DEV(atmel_spi, 1);
 909 DEV_CLK(spi_clk, atmel_spi1, pba, 1);
 910
 911 static void __init
 912 at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
 913                       unsigned int n, const u8 *pins)
 914 {
 915         unsigned int pin, mode;
 916
 917         for (; n; n--, b++) {
 918                 b->bus_num = bus_num;
 919                 if (b->chip_select >= 4)
 920                         continue;
 921                 pin = (unsigned)b->controller_data;
 922                 if (!pin) {
 923                         pin = pins[b->chip_select];
 924                         b->controller_data = (void *)pin;
 925                 }
 926                 mode = AT32_GPIOF_OUTPUT;
 927                 if (!(b->mode & SPI_CS_HIGH))
 928                         mode |= AT32_GPIOF_HIGH;
 929                 at32_select_gpio(pin, mode);
 930         }
 931 }
 932
 933 struct platform_device *__init
 934 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
 935 {
 936         /*
 937          * Manage the chipselects as GPIOs, normally using the same pins
 938          * the SPI controller expects; but boards can use other pins.
 939          */
 940         static u8 __initdata spi0_pins[] =
 941                 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
 942                   GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
 943         static u8 __initdata spi1_pins[] =
 944                 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
 945                   GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
 946         struct platform_device *pdev;
 947
 948         switch (id) {
 949         case 0:
 950                 pdev = &atmel_spi0_device;
 951                 select_peripheral(PA(0),  PERIPH_A, 0); /* MISO  */
 952                 select_peripheral(PA(1),  PERIPH_A, 0); /* MOSI  */
 953                 select_peripheral(PA(2),  PERIPH_A, 0); /* SCK   */
 954                 at32_spi_setup_slaves(0, b, n, spi0_pins);
 955                 break;
 956
 957         case 1:
 958                 pdev = &atmel_spi1_device;
 959                 select_peripheral(PB(0),  PERIPH_B, 0); /* MISO  */
 960                 select_peripheral(PB(1),  PERIPH_B, 0); /* MOSI  */
 961                 select_peripheral(PB(5),  PERIPH_B, 0); /* SCK   */
 962                 at32_spi_setup_slaves(1, b, n, spi1_pins);
 963                 break;
 964
 965         default:
 966                 return NULL;
 967         }
 968
 969         spi_register_board_info(b, n);
 970         platform_device_register(pdev);
 971         return pdev;
 972 }
 973
 974 /* --------------------------------------------------------------------
 975  *  TWI
 976  * -------------------------------------------------------------------- */
 977 static struct resource atmel_twi0_resource[] __initdata = {
 978         PBMEM(0xffe00800),
 979         IRQ(5),
 980 };
 981 static struct clk atmel_twi0_pclk = {
 982         .name           = "twi_pclk",
 983         .parent         = &pba_clk,
 984         .mode           = pba_clk_mode,
 985         .get_rate       = pba_clk_get_rate,
 986         .index          = 2,
 987 };
 988
 989 struct platform_device *__init at32_add_device_twi(unsigned int id)
 990 {
 991         struct platform_device *pdev;
 992
 993         if (id != 0)
 994                 return NULL;
 995
 996         pdev = platform_device_alloc("atmel_twi", id);
 997         if (!pdev)
 998                 return NULL;
 999
1000         if (platform_device_add_resources(pdev, atmel_twi0_resource,
1001                                 ARRAY_SIZE(atmel_twi0_resource)))
1002                 goto err_add_resources;
1003
1004         select_peripheral(PA(6),  PERIPH_A, 0); /* SDA  */
1005         select_peripheral(PA(7),  PERIPH_A, 0); /* SDL  */
1006
1007         atmel_twi0_pclk.dev = &pdev->dev;
1008
1009         platform_device_add(pdev);
1010         return pdev;
1011
1012 err_add_resources:
1013         platform_device_put(pdev);
1014         return NULL;
1015 }
1016
1017 /* --------------------------------------------------------------------
1018  * MMC
1019  * -------------------------------------------------------------------- */
1020 static struct resource atmel_mci0_resource[] __initdata = {
1021         PBMEM(0xfff02400),
1022         IRQ(28),
1023 };
1024 static struct clk atmel_mci0_pclk = {
1025         .name           = "mci_clk",
1026         .parent         = &pbb_clk,
1027         .mode           = pbb_clk_mode,
1028         .get_rate       = pbb_clk_get_rate,
1029         .index          = 9,
1030 };
1031
1032 struct platform_device *__init at32_add_device_mci(unsigned int id)
1033 {
1034         struct platform_device *pdev;
1035
1036         if (id != 0)
1037                 return NULL;
1038
1039         pdev = platform_device_alloc("atmel_mci", id);
1040         if (!pdev)
1041                 return NULL;
1042
1043         if (platform_device_add_resources(pdev, atmel_mci0_resource,
1044                                 ARRAY_SIZE(atmel_mci0_resource)))
1045                 goto err_add_resources;
1046
1047         select_peripheral(PA(10), PERIPH_A, 0); /* CLK   */
1048         select_peripheral(PA(11), PERIPH_A, 0); /* CMD   */
1049         select_peripheral(PA(12), PERIPH_A, 0); /* DATA0 */
1050         select_peripheral(PA(13), PERIPH_A, 0); /* DATA1 */
1051         select_peripheral(PA(14), PERIPH_A, 0); /* DATA2 */
1052         select_peripheral(PA(15), PERIPH_A, 0); /* DATA3 */
1053
1054         atmel_mci0_pclk.dev = &pdev->dev;
1055
1056         platform_device_add(pdev);
1057         return pdev;
1058
1059 err_add_resources:
1060         platform_device_put(pdev);
1061         return NULL;
1062 }
1063
1064 /* --------------------------------------------------------------------
1065  *  LCDC
1066  * -------------------------------------------------------------------- */
1067 static struct atmel_lcdfb_info atmel_lcdfb0_data;
1068 static struct resource atmel_lcdfb0_resource[] = {
1069         {
1070                 .start          = 0xff000000,
1071                 .end            = 0xff000fff,
1072                 .flags          = IORESOURCE_MEM,
1073         },
1074         IRQ(1),
1075         {
1076                 /* Placeholder for pre-allocated fb memory */
1077                 .start          = 0x00000000,
1078                 .end            = 0x00000000,
1079                 .flags          = 0,
1080         },
1081 };
1082 DEFINE_DEV_DATA(atmel_lcdfb, 0);
1083 DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
1084 static struct clk atmel_lcdfb0_pixclk = {
1085         .name           = "lcdc_clk",
1086         .dev            = &atmel_lcdfb0_device.dev,
1087         .mode           = genclk_mode,
1088         .get_rate       = genclk_get_rate,
1089         .set_rate       = genclk_set_rate,
1090         .set_parent     = genclk_set_parent,
1091         .index          = 7,
1092 };
1093
1094 struct platform_device *__init
1095 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
1096                      unsigned long fbmem_start, unsigned long fbmem_len)
1097 {
1098         struct platform_device *pdev;
1099         struct atmel_lcdfb_info *info;
1100         struct fb_monspecs *monspecs;
1101         struct fb_videomode *modedb;
1102         unsigned int modedb_size;
1103
1104         /*
1105          * Do a deep copy of the fb data, monspecs and modedb. Make
1106          * sure all allocations are done before setting up the
1107          * portmux.
1108          */
1109         monspecs = kmemdup(data->default_monspecs,
1110                            sizeof(struct fb_monspecs), GFP_KERNEL);
1111         if (!monspecs)
1112                 return NULL;
1113
1114         modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
1115         modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
1116         if (!modedb)
1117                 goto err_dup_modedb;
1118         monspecs->modedb = modedb;
1119
1120         switch (id) {
1121         case 0:
1122                 pdev = &atmel_lcdfb0_device;
1123                 select_peripheral(PC(19), PERIPH_A, 0); /* CC     */
1124                 select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC  */
1125                 select_peripheral(PC(21), PERIPH_A, 0); /* PCLK   */
1126                 select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC  */
1127                 select_peripheral(PC(23), PERIPH_A, 0); /* DVAL   */
1128                 select_peripheral(PC(24), PERIPH_A, 0); /* MODE   */
1129                 select_peripheral(PC(25), PERIPH_A, 0); /* PWR    */
1130                 select_peripheral(PC(26), PERIPH_A, 0); /* DATA0  */
1131                 select_peripheral(PC(27), PERIPH_A, 0); /* DATA1  */
1132                 select_peripheral(PC(28), PERIPH_A, 0); /* DATA2  */
1133                 select_peripheral(PC(29), PERIPH_A, 0); /* DATA3  */
1134                 select_peripheral(PC(30), PERIPH_A, 0); /* DATA4  */
1135                 select_peripheral(PC(31), PERIPH_A, 0); /* DATA5  */
1136                 select_peripheral(PD(0),  PERIPH_A, 0); /* DATA6  */
1137                 select_peripheral(PD(1),  PERIPH_A, 0); /* DATA7  */
1138                 select_peripheral(PD(2),  PERIPH_A, 0); /* DATA8  */
1139                 select_peripheral(PD(3),  PERIPH_A, 0); /* DATA9  */
1140                 select_peripheral(PD(4),  PERIPH_A, 0); /* DATA10 */
1141                 select_peripheral(PD(5),  PERIPH_A, 0); /* DATA11 */
1142                 select_peripheral(PD(6),  PERIPH_A, 0); /* DATA12 */
1143                 select_peripheral(PD(7),  PERIPH_A, 0); /* DATA13 */
1144                 select_peripheral(PD(8),  PERIPH_A, 0); /* DATA14 */
1145                 select_peripheral(PD(9),  PERIPH_A, 0); /* DATA15 */
1146                 select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
1147                 select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
1148                 select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
1149                 select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
1150                 select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
1151                 select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
1152                 select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
1153                 select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
1154
1155                 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
1156                 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
1157                 break;
1158
1159         default:
1160                 goto err_invalid_id;
1161         }
1162
1163         if (fbmem_len) {
1164                 pdev->resource[2].start = fbmem_start;
1165                 pdev->resource[2].end = fbmem_start + fbmem_len - 1;
1166                 pdev->resource[2].flags = IORESOURCE_MEM;
1167         }
1168
1169         info = pdev->dev.platform_data;
1170         memcpy(info, data, sizeof(struct atmel_lcdfb_info));
1171         info->default_monspecs = monspecs;
1172
1173         platform_device_register(pdev);
1174         return pdev;
1175
1176 err_invalid_id:
1177         kfree(modedb);
1178 err_dup_modedb:
1179         kfree(monspecs);
1180         return NULL;
1181 }
1182
1183 /* --------------------------------------------------------------------
1184  *  SSC
1185  * -------------------------------------------------------------------- */
1186 static struct resource ssc0_resource[] = {
1187         PBMEM(0xffe01c00),
1188         IRQ(10),
1189 };
1190 DEFINE_DEV(ssc, 0);
1191 DEV_CLK(pclk, ssc0, pba, 7);
1192
1193 static struct resource ssc1_resource[] = {
1194         PBMEM(0xffe02000),
1195         IRQ(11),
1196 };
1197 DEFINE_DEV(ssc, 1);
1198 DEV_CLK(pclk, ssc1, pba, 8);
1199
1200 static struct resource ssc2_resource[] = {
1201         PBMEM(0xffe02400),
1202         IRQ(12),
1203 };
1204 DEFINE_DEV(ssc, 2);
1205 DEV_CLK(pclk, ssc2, pba, 9);
1206
1207 struct platform_device *__init
1208 at32_add_device_ssc(unsigned int id, unsigned int flags)
1209 {
1210         struct platform_device *pdev;
1211
1212         switch (id) {
1213         case 0:
1214                 pdev = &ssc0_device;
1215                 if (flags & ATMEL_SSC_RF)
1216                         select_peripheral(PA(21), PERIPH_A, 0); /* RF */
1217                 if (flags & ATMEL_SSC_RK)
1218                         select_peripheral(PA(22), PERIPH_A, 0); /* RK */
1219                 if (flags & ATMEL_SSC_TK)
1220                         select_peripheral(PA(23), PERIPH_A, 0); /* TK */
1221                 if (flags & ATMEL_SSC_TF)
1222                         select_peripheral(PA(24), PERIPH_A, 0); /* TF */
1223                 if (flags & ATMEL_SSC_TD)
1224                         select_peripheral(PA(25), PERIPH_A, 0); /* TD */
1225                 if (flags & ATMEL_SSC_RD)
1226                         select_peripheral(PA(26), PERIPH_A, 0); /* RD */
1227                 break;
1228         case 1:
1229                 pdev = &ssc1_device;
1230                 if (flags & ATMEL_SSC_RF)
1231                         select_peripheral(PA(0), PERIPH_B, 0);  /* RF */
1232                 if (flags & ATMEL_SSC_RK)
1233                         select_peripheral(PA(1), PERIPH_B, 0);  /* RK */
1234                 if (flags & ATMEL_SSC_TK)
1235                         select_peripheral(PA(2), PERIPH_B, 0);  /* TK */
1236                 if (flags & ATMEL_SSC_TF)
1237                         select_peripheral(PA(3), PERIPH_B, 0);  /* TF */
1238                 if (flags & ATMEL_SSC_TD)
1239                         select_peripheral(PA(4), PERIPH_B, 0);  /* TD */
1240                 if (flags & ATMEL_SSC_RD)
1241                         select_peripheral(PA(5), PERIPH_B, 0);  /* RD */
1242                 break;
1243         case 2:
1244                 pdev = &ssc2_device;
1245                 if (flags & ATMEL_SSC_TD)
1246                         select_peripheral(PB(13), PERIPH_A, 0); /* TD */
1247                 if (flags & ATMEL_SSC_RD)
1248                         select_peripheral(PB(14), PERIPH_A, 0); /* RD */
1249                 if (flags & ATMEL_SSC_TK)
1250                         select_peripheral(PB(15), PERIPH_A, 0); /* TK */
1251                 if (flags & ATMEL_SSC_TF)
1252                         select_peripheral(PB(16), PERIPH_A, 0); /* TF */
1253                 if (flags & ATMEL_SSC_RF)
1254                         select_peripheral(PB(17), PERIPH_A, 0); /* RF */
1255                 if (flags & ATMEL_SSC_RK)
1256                         select_peripheral(PB(18), PERIPH_A, 0); /* RK */
1257                 break;
1258         default:
1259                 return NULL;
1260         }
1261
1262         platform_device_register(pdev);
1263         return pdev;
1264 }
1265
1266 /* --------------------------------------------------------------------
1267  *  USB Device Controller
1268  * -------------------------------------------------------------------- */
1269 static struct resource usba0_resource[] __initdata = {
1270         {
1271                 .start          = 0xff300000,
1272                 .end            = 0xff3fffff,
1273                 .flags          = IORESOURCE_MEM,
1274         }, {
1275                 .start          = 0xfff03000,
1276                 .end            = 0xfff033ff,
1277                 .flags          = IORESOURCE_MEM,
1278         },
1279         IRQ(31),
1280 };
1281 static struct clk usba0_pclk = {
1282         .name           = "pclk",
1283         .parent         = &pbb_clk,
1284         .mode           = pbb_clk_mode,
1285         .get_rate       = pbb_clk_get_rate,
1286         .index          = 12,
1287 };
1288 static struct clk usba0_hclk = {
1289         .name           = "hclk",
1290         .parent         = &hsb_clk,
1291         .mode           = hsb_clk_mode,
1292         .get_rate       = hsb_clk_get_rate,
1293         .index          = 6,
1294 };
1295
1296 struct platform_device *__init
1297 at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
1298 {
1299         struct platform_device *pdev;
1300
1301         if (id != 0)
1302                 return NULL;
1303
1304         pdev = platform_device_alloc("atmel_usba_udc", 0);
1305         if (!pdev)
1306                 return NULL;
1307
1308         if (platform_device_add_resources(pdev, usba0_resource,
1309                                           ARRAY_SIZE(usba0_resource)))
1310                 goto out_free_pdev;
1311
1312         if (data) {
1313                 if (platform_device_add_data(pdev, data, sizeof(*data)))
1314                         goto out_free_pdev;
1315
1316                 if (data->vbus_pin != GPIO_PIN_NONE)
1317                         at32_select_gpio(data->vbus_pin, 0);
1318         }
1319
1320         usba0_pclk.dev = &pdev->dev;
1321         usba0_hclk.dev = &pdev->dev;
1322
1323         platform_device_add(pdev);
1324
1325         return pdev;
1326
1327 out_free_pdev:
1328         platform_device_put(pdev);
1329         return NULL;
1330 }
1331
1332 /* --------------------------------------------------------------------
1333  * IDE / CompactFlash
1334  * -------------------------------------------------------------------- */
1335 static struct resource at32_smc_cs4_resource[] __initdata = {
1336         {
1337                 .start  = 0x04000000,
1338                 .end    = 0x07ffffff,
1339                 .flags  = IORESOURCE_MEM,
1340         },
1341         IRQ(~0UL), /* Magic IRQ will be overridden */
1342 };
1343 static struct resource at32_smc_cs5_resource[] __initdata = {
1344         {
1345                 .start  = 0x20000000,
1346                 .end    = 0x23ffffff,
1347                 .flags  = IORESOURCE_MEM,
1348         },
1349         IRQ(~0UL), /* Magic IRQ will be overridden */
1350 };
1351
1352 static int __init at32_init_ide_or_cf(struct platform_device *pdev,
1353                 unsigned int cs, unsigned int extint)
1354 {
1355         static unsigned int extint_pin_map[4] __initdata = {
1356                 GPIO_PIN_PB(25),
1357                 GPIO_PIN_PB(26),
1358                 GPIO_PIN_PB(27),
1359                 GPIO_PIN_PB(28),
1360         };
1361         static bool common_pins_initialized __initdata = false;
1362         unsigned int extint_pin;
1363         int ret;
1364
1365         if (extint >= ARRAY_SIZE(extint_pin_map))
1366                 return -EINVAL;
1367         extint_pin = extint_pin_map[extint];
1368
1369         switch (cs) {
1370         case 4:
1371                 ret = platform_device_add_resources(pdev,
1372                                 at32_smc_cs4_resource,
1373                                 ARRAY_SIZE(at32_smc_cs4_resource));
1374                 if (ret)
1375                         return ret;
1376
1377                 select_peripheral(PE(21), PERIPH_A, 0); /* NCS4   -> OE_N  */
1378                 set_ebi_sfr_bits(HMATRIX_BIT(CS4A));
1379                 break;
1380         case 5:
1381                 ret = platform_device_add_resources(pdev,
1382                                 at32_smc_cs5_resource,
1383                                 ARRAY_SIZE(at32_smc_cs5_resource));
1384                 if (ret)
1385                         return ret;
1386
1387                 select_peripheral(PE(22), PERIPH_A, 0); /* NCS5   -> OE_N  */
1388                 set_ebi_sfr_bits(HMATRIX_BIT(CS5A));
1389                 break;
1390         default:
1391                 return -EINVAL;
1392         }
1393
1394         if (!common_pins_initialized) {
1395                 select_peripheral(PE(19), PERIPH_A, 0); /* CFCE1  -> CS0_N */
1396                 select_peripheral(PE(20), PERIPH_A, 0); /* CFCE2  -> CS1_N */
1397                 select_peripheral(PE(23), PERIPH_A, 0); /* CFRNW  -> DIR   */
1398                 select_peripheral(PE(24), PERIPH_A, 0); /* NWAIT  <- IORDY */
1399                 common_pins_initialized = true;
1400         }
1401
1402         at32_select_periph(extint_pin, GPIO_PERIPH_A, AT32_GPIOF_DEGLITCH);
1403
1404         pdev->resource[1].start = EIM_IRQ_BASE + extint;
1405         pdev->resource[1].end = pdev->resource[1].start;
1406
1407         return 0;
1408 }
1409
1410 struct platform_device *__init
1411 at32_add_device_ide(unsigned int id, unsigned int extint,
1412                     struct ide_platform_data *data)
1413 {
1414         struct platform_device *pdev;
1415
1416         pdev = platform_device_alloc("at32_ide", id);
1417         if (!pdev)
1418                 goto fail;
1419
1420         if (platform_device_add_data(pdev, data,
1421                                 sizeof(struct ide_platform_data)))
1422                 goto fail;
1423
1424         if (at32_init_ide_or_cf(pdev, data->cs, extint))
1425                 goto fail;
1426
1427         platform_device_add(pdev);
1428         return pdev;
1429
1430 fail:
1431         platform_device_put(pdev);
1432         return NULL;
1433 }
1434
1435 struct platform_device *__init
1436 at32_add_device_cf(unsigned int id, unsigned int extint,
1437                     struct cf_platform_data *data)
1438 {
1439         struct platform_device *pdev;
1440
1441         pdev = platform_device_alloc("at32_cf", id);
1442         if (!pdev)
1443                 goto fail;
1444
1445         if (platform_device_add_data(pdev, data,
1446                                 sizeof(struct cf_platform_data)))
1447                 goto fail;
1448
1449         if (at32_init_ide_or_cf(pdev, data->cs, extint))
1450                 goto fail;
1451
1452         if (data->detect_pin != GPIO_PIN_NONE)
1453                 at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH);
1454         if (data->reset_pin != GPIO_PIN_NONE)
1455                 at32_select_gpio(data->reset_pin, 0);
1456         if (data->vcc_pin != GPIO_PIN_NONE)
1457                 at32_select_gpio(data->vcc_pin, 0);
1458         /* READY is used as extint, so we can't select it as gpio */
1459
1460         platform_device_add(pdev);
1461         return pdev;
1462
1463 fail:
1464         platform_device_put(pdev);
1465         return NULL;
1466 }
1467
1468 /* --------------------------------------------------------------------
1469  * AC97C
1470  * -------------------------------------------------------------------- */
1471 static struct resource atmel_ac97c0_resource[] __initdata = {
1472         PBMEM(0xfff02800),
1473         IRQ(29),
1474 };
1475 static struct clk atmel_ac97c0_pclk = {
1476         .name           = "pclk",
1477         .parent         = &pbb_clk,
1478         .mode           = pbb_clk_mode,
1479         .get_rate       = pbb_clk_get_rate,
1480         .index          = 10,
1481 };
1482
1483 struct platform_device *__init at32_add_device_ac97c(unsigned int id)
1484 {
1485         struct platform_device *pdev;
1486
1487         if (id != 0)
1488                 return NULL;
1489
1490         pdev = platform_device_alloc("atmel_ac97c", id);
1491         if (!pdev)
1492                 return NULL;
1493
1494         if (platform_device_add_resources(pdev, atmel_ac97c0_resource,
1495                                 ARRAY_SIZE(atmel_ac97c0_resource)))
1496                 goto err_add_resources;
1497
1498         select_peripheral(PB(20), PERIPH_B, 0); /* SYNC */
1499         select_peripheral(PB(21), PERIPH_B, 0); /* SDO  */
1500         select_peripheral(PB(22), PERIPH_B, 0); /* SDI  */
1501         select_peripheral(PB(23), PERIPH_B, 0); /* SCLK */
1502
1503         atmel_ac97c0_pclk.dev = &pdev->dev;
1504
1505         platform_device_add(pdev);
1506         return pdev;
1507
1508 err_add_resources:
1509         platform_device_put(pdev);
1510         return NULL;
1511 }
1512
1513 /* --------------------------------------------------------------------
1514  * ABDAC
1515  * -------------------------------------------------------------------- */
1516 static struct resource abdac0_resource[] __initdata = {
1517         PBMEM(0xfff02000),
1518         IRQ(27),
1519 };
1520 static struct clk abdac0_pclk = {
1521         .name           = "pclk",
1522         .parent         = &pbb_clk,
1523         .mode           = pbb_clk_mode,
1524         .get_rate       = pbb_clk_get_rate,
1525         .index          = 8,
1526 };
1527 static struct clk abdac0_sample_clk = {
1528         .name           = "sample_clk",
1529         .mode           = genclk_mode,
1530         .get_rate       = genclk_get_rate,
1531         .set_rate       = genclk_set_rate,
1532         .set_parent     = genclk_set_parent,
1533         .index          = 6,
1534 };
1535
1536 struct platform_device *__init at32_add_device_abdac(unsigned int id)
1537 {
1538         struct platform_device *pdev;
1539
1540         if (id != 0)
1541                 return NULL;
1542
1543         pdev = platform_device_alloc("abdac", id);
1544         if (!pdev)
1545                 return NULL;
1546
1547         if (platform_device_add_resources(pdev, abdac0_resource,
1548                                 ARRAY_SIZE(abdac0_resource)))
1549                 goto err_add_resources;
1550
1551         select_peripheral(PB(20), PERIPH_A, 0); /* DATA1        */
1552         select_peripheral(PB(21), PERIPH_A, 0); /* DATA0        */
1553         select_peripheral(PB(22), PERIPH_A, 0); /* DATAN1       */
1554         select_peripheral(PB(23), PERIPH_A, 0); /* DATAN0       */
1555
1556         abdac0_pclk.dev = &pdev->dev;
1557         abdac0_sample_clk.dev = &pdev->dev;
1558
1559         platform_device_add(pdev);
1560         return pdev;
1561
1562 err_add_resources:
1563         platform_device_put(pdev);
1564         return NULL;
1565 }
1566
1567 /* --------------------------------------------------------------------
1568  *  GCLK
1569  * -------------------------------------------------------------------- */
1570 static struct clk gclk0 = {
1571         .name           = "gclk0",
1572         .mode           = genclk_mode,
1573         .get_rate       = genclk_get_rate,
1574         .set_rate       = genclk_set_rate,
1575         .set_parent     = genclk_set_parent,
1576         .index          = 0,
1577 };
1578 static struct clk gclk1 = {
1579         .name           = "gclk1",
1580         .mode           = genclk_mode,
1581         .get_rate       = genclk_get_rate,
1582         .set_rate       = genclk_set_rate,
1583         .set_parent     = genclk_set_parent,
1584         .index          = 1,
1585 };
1586 static struct clk gclk2 = {
1587         .name           = "gclk2",
1588         .mode           = genclk_mode,
1589         .get_rate       = genclk_get_rate,
1590         .set_rate       = genclk_set_rate,
1591         .set_parent     = genclk_set_parent,
1592         .index          = 2,
1593 };
1594 static struct clk gclk3 = {
1595         .name           = "gclk3",
1596         .mode           = genclk_mode,
1597         .get_rate       = genclk_get_rate,
1598         .set_rate       = genclk_set_rate,
1599         .set_parent     = genclk_set_parent,
1600         .index          = 3,
1601 };
1602 static struct clk gclk4 = {
1603         .name           = "gclk4",
1604         .mode           = genclk_mode,
1605         .get_rate       = genclk_get_rate,
1606         .set_rate       = genclk_set_rate,
1607         .set_parent     = genclk_set_parent,
1608         .index          = 4,
1609 };
1610
1611 struct clk *at32_clock_list[] = {
1612         &osc32k,
1613         &osc0,
1614         &osc1,
1615         &pll0,
1616         &pll1,
1617         &cpu_clk,
1618         &hsb_clk,
1619         &pba_clk,
1620         &pbb_clk,
1621         &at32_pm_pclk,
1622         &at32_intc0_pclk,
1623         &hmatrix_clk,
1624         &ebi_clk,
1625         &hramc_clk,
1626         &smc0_pclk,
1627         &smc0_mck,
1628         &pdc_hclk,
1629         &pdc_pclk,
1630         &dmaca0_hclk,
1631         &pico_clk,
1632         &pio0_mck,
1633         &pio1_mck,
1634         &pio2_mck,
1635         &pio3_mck,
1636         &pio4_mck,
1637         &at32_systc0_pclk,
1638         &atmel_usart0_usart,
1639         &atmel_usart1_usart,
1640         &atmel_usart2_usart,
1641         &atmel_usart3_usart,
1642         &macb0_hclk,
1643         &macb0_pclk,
1644         &macb1_hclk,
1645         &macb1_pclk,
1646         &atmel_spi0_spi_clk,
1647         &atmel_spi1_spi_clk,
1648         &atmel_twi0_pclk,
1649         &atmel_mci0_pclk,
1650         &atmel_lcdfb0_hck1,
1651         &atmel_lcdfb0_pixclk,
1652         &ssc0_pclk,
1653         &ssc1_pclk,
1654         &ssc2_pclk,
1655         &usba0_hclk,
1656         &usba0_pclk,
1657         &atmel_ac97c0_pclk,
1658         &abdac0_pclk,
1659         &abdac0_sample_clk,
1660         &gclk0,
1661         &gclk1,
1662         &gclk2,
1663         &gclk3,
1664         &gclk4,
1665 };
1666 unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
1667
1668 void __init at32_portmux_init(void)
1669 {
1670         at32_init_pio(&pio0_device);
1671         at32_init_pio(&pio1_device);
1672         at32_init_pio(&pio2_device);
1673         at32_init_pio(&pio3_device);
1674         at32_init_pio(&pio4_device);
1675 }
1676
1677 void __init at32_clock_init(void)
1678 {
1679         u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
1680         int i;
1681
1682         if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
1683                 main_clock = &pll0;
1684                 cpu_clk.parent = &pll0;
1685         } else {
1686                 main_clock = &osc0;
1687                 cpu_clk.parent = &osc0;
1688         }
1689
1690         if (pm_readl(PLL0) & PM_BIT(PLLOSC))
1691                 pll0.parent = &osc1;
1692         if (pm_readl(PLL1) & PM_BIT(PLLOSC))
1693                 pll1.parent = &osc1;
1694
1695         genclk_init_parent(&gclk0);
1696         genclk_init_parent(&gclk1);
1697         genclk_init_parent(&gclk2);
1698         genclk_init_parent(&gclk3);
1699         genclk_init_parent(&gclk4);
1700         genclk_init_parent(&atmel_lcdfb0_pixclk);
1701         genclk_init_parent(&abdac0_sample_clk);
1702
1703         /*
1704          * Turn on all clocks that have at least one user already, and
1705          * turn off everything else. We only do this for module
1706          * clocks, and even though it isn't particularly pretty to
1707          * check the address of the mode function, it should do the
1708          * trick...
1709          */
1710         for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) {
1711                 struct clk *clk = at32_clock_list[i];
1712
1713                 if (clk->users == 0)
1714                         continue;
1715
1716                 if (clk->mode == &cpu_clk_mode)
1717                         cpu_mask |= 1 << clk->index;
1718                 else if (clk->mode == &hsb_clk_mode)
1719                         hsb_mask |= 1 << clk->index;
1720                 else if (clk->mode == &pba_clk_mode)
1721                         pba_mask |= 1 << clk->index;
1722                 else if (clk->mode == &pbb_clk_mode)
1723                         pbb_mask |= 1 << clk->index;
1724         }
1725
1726         pm_writel(CPU_MASK, cpu_mask);
1727         pm_writel(HSB_MASK, hsb_mask);
1728         pm_writel(PBA_MASK, pba_mask);
1729         pm_writel(PBB_MASK, pbb_mask);
1730 }