arch/arm64/boot/dts/mediatek/mt8173.dtsi

   1 /*
   2  * Copyright (c) 2014 MediaTek Inc.
   3  * Author: Eddie Huang <eddie.huang@mediatek.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15 #include <dt-bindings/interrupt-controller/arm-gic.h>
  16
  17 / {
  18         compatible = "mediatek,mt8173";
  19         interrupt-parent = <&sysirq>;
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         cpus {
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26
  27                 cpu-map {
  28                         cluster0 {
  29                                 core0 {
  30                                         cpu = <&cpu0>;
  31                                 };
  32                                 core1 {
  33                                         cpu = <&cpu1>;
  34                                 };
  35                         };
  36
  37                         cluster1 {
  38                                 core0 {
  39                                         cpu = <&cpu2>;
  40                                 };
  41                                 core1 {
  42                                         cpu = <&cpu3>;
  43                                 };
  44                         };
  45                 };
  46
  47                 cpu0: cpu@0 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a53";
  50                         reg = <0x000>;
  51                 };
  52
  53                 cpu1: cpu@1 {
  54                         device_type = "cpu";
  55                         compatible = "arm,cortex-a53";
  56                         reg = <0x001>;
  57                         enable-method = "psci";
  58                 };
  59
  60                 cpu2: cpu@100 {
  61                         device_type = "cpu";
  62                         compatible = "arm,cortex-a57";
  63                         reg = <0x100>;
  64                         enable-method = "psci";
  65                 };
  66
  67                 cpu3: cpu@101 {
  68                         device_type = "cpu";
  69                         compatible = "arm,cortex-a57";
  70                         reg = <0x101>;
  71                         enable-method = "psci";
  72                 };
  73         };
  74
  75         psci {
  76                 compatible = "arm,psci";
  77                 method = "smc";
  78                 cpu_suspend   = <0x84000001>;
  79                 cpu_off       = <0x84000002>;
  80                 cpu_on        = <0x84000003>;
  81         };
  82
  83         uart_clk: dummy26m {
  84                 compatible = "fixed-clock";
  85                 clock-frequency = <26000000>;
  86                 #clock-cells = <0>;
  87         };
  88
  89         timer {
  90                 compatible = "arm,armv8-timer";
  91                 interrupt-parent = <&gic>;
  92                 interrupts = <GIC_PPI 13
  93                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  94                              <GIC_PPI 14
  95                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  96                              <GIC_PPI 11
  97                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  98                              <GIC_PPI 10
  99                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 100         };
 101
 102         soc {
 103                 #address-cells = <2>;
 104                 #size-cells = <2>;
 105                 compatible = "simple-bus";
 106                 ranges;
 107
 108                 sysirq: intpol-controller@10200620 {
 109                         compatible = "mediatek,mt8173-sysirq",
 110                                         "mediatek,mt6577-sysirq";
 111                         interrupt-controller;
 112                         #interrupt-cells = <3>;
 113                         interrupt-parent = <&gic>;
 114                         reg = <0 0x10200620 0 0x20>;
 115                 };
 116
 117                 gic: interrupt-controller@10220000 {
 118                         compatible = "arm,gic-400";
 119                         #interrupt-cells = <3>;
 120                         interrupt-parent = <&gic>;
 121                         interrupt-controller;
 122                         reg = <0 0x10221000 0 0x1000>,
 123                               <0 0x10222000 0 0x2000>,
 124                               <0 0x10224000 0 0x2000>,
 125                               <0 0x10226000 0 0x2000>;
 126                         interrupts = <GIC_PPI 9
 127                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 128                 };
 129
 130                 uart0: serial@11002000 {
 131                         compatible = "mediatek,mt8173-uart",
 132                                         "mediatek,mt6577-uart";
 133                         reg = <0 0x11002000 0 0x400>;
 134                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
 135                         clocks = <&uart_clk>;
 136                         status = "disabled";
 137                 };
 138
 139                 uart1: serial@11003000 {
 140                         compatible = "mediatek,mt8173-uart",
 141                                         "mediatek,mt6577-uart";
 142                         reg = <0 0x11003000 0 0x400>;
 143                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
 144                         clocks = <&uart_clk>;
 145                         status = "disabled";
 146                 };
 147
 148                 uart2: serial@11004000 {
 149                         compatible = "mediatek,mt8173-uart",
 150                                         "mediatek,mt6577-uart";
 151                         reg = <0 0x11004000 0 0x400>;
 152                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
 153                         clocks = <&uart_clk>;
 154                         status = "disabled";
 155                 };
 156
 157                 uart3: serial@11005000 {
 158                         compatible = "mediatek,mt8173-uart",
 159                                         "mediatek,mt6577-uart";
 160                         reg = <0 0x11005000 0 0x400>;
 161                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
 162                         clocks = <&uart_clk>;
 163                         status = "disabled";
 164                 };
 165         };
 166
 167 };
 168