arch/arm/plat-s5p/irq-gpioint.c

   1 /* linux/arch/arm/plat-s5p/irq-gpioint.c
   2  *
   3  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   4  * Author: Kyungmin Park <kyungmin.park@samsung.com>
   5  * Author: Joonyoung Shim <jy0922.shim@samsung.com>
   6  * Author: Marek Szyprowski <m.szyprowski@samsung.com>
   7  *
   8  *  This program is free software; you can redistribute  it and/or modify it
   9  *  under  the terms of  the GNU General  Public License as published by the
  10  *  Free Software Foundation;  either version 2 of the  License, or (at your
  11  *  option) any later version.
  12  *
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/irq.h>
  18 #include <linux/io.h>
  19 #include <linux/gpio.h>
  20 #include <linux/slab.h>
  21
  22 #include <mach/map.h>
  23 #include <plat/gpio-core.h>
  24 #include <plat/gpio-cfg.h>
  25
  26 #define GPIO_BASE(chip)         (((unsigned long)(chip)->base) & 0xFFFFF000u)
  27
  28 #define CON_OFFSET              0x700
  29 #define MASK_OFFSET             0x900
  30 #define PEND_OFFSET             0xA00
  31 #define REG_OFFSET(x)           ((x) << 2)
  32
  33 struct s5p_gpioint_bank {
  34         struct list_head        list;
  35         int                     start;
  36         int                     nr_groups;
  37         int                     irq;
  38         struct s3c_gpio_chip    **chips;
  39         void                    (*handler)(unsigned int, struct irq_desc *);
  40 };
  41
  42 LIST_HEAD(banks);
  43
  44 static int s5p_gpioint_set_type(struct irq_data *d, unsigned int type)
  45 {
  46         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  47         struct irq_chip_type *ct = gc->chip_types;
  48         unsigned int shift = (d->irq - gc->irq_base) << 2;
  49
  50         switch (type) {
  51         case IRQ_TYPE_EDGE_RISING:
  52                 type = S5P_IRQ_TYPE_EDGE_RISING;
  53                 break;
  54         case IRQ_TYPE_EDGE_FALLING:
  55                 type = S5P_IRQ_TYPE_EDGE_FALLING;
  56                 break;
  57         case IRQ_TYPE_EDGE_BOTH:
  58                 type = S5P_IRQ_TYPE_EDGE_BOTH;
  59                 break;
  60         case IRQ_TYPE_LEVEL_HIGH:
  61                 type = S5P_IRQ_TYPE_LEVEL_HIGH;
  62                 break;
  63         case IRQ_TYPE_LEVEL_LOW:
  64                 type = S5P_IRQ_TYPE_LEVEL_LOW;
  65                 break;
  66         case IRQ_TYPE_NONE:
  67         default:
  68                 printk(KERN_WARNING "No irq type\n");
  69                 return -EINVAL;
  70         }
  71
  72         gc->type_cache &= ~(0x7 << shift);
  73         gc->type_cache |= type << shift;
  74         writel(gc->type_cache, gc->reg_base + ct->regs.type);
  75         return 0;
  76 }
  77
  78 static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
  79 {
  80         struct s5p_gpioint_bank *bank = irq_get_handler_data(irq);
  81         int group, pend_offset, mask_offset;
  82         unsigned int pend, mask;
  83
  84         for (group = 0; group < bank->nr_groups; group++) {
  85                 struct s3c_gpio_chip *chip = bank->chips[group];
  86                 if (!chip)
  87                         continue;
  88
  89                 pend_offset = REG_OFFSET(group);
  90                 pend = __raw_readl(GPIO_BASE(chip) + PEND_OFFSET + pend_offset);
  91                 if (!pend)
  92                         continue;
  93
  94                 mask_offset = REG_OFFSET(group);
  95                 mask = __raw_readl(GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
  96                 pend &= ~mask;
  97
  98                 while (pend) {
  99                         int offset = fls(pend) - 1;
 100                         int real_irq = chip->irq_base + offset;
 101                         generic_handle_irq(real_irq);
 102                         pend &= ~BIT(offset);
 103                 }
 104         }
 105 }
 106
 107 static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)
 108 {
 109         static int used_gpioint_groups = 0;
 110         int group = chip->group;
 111         struct s5p_gpioint_bank *bank = NULL;
 112         struct irq_chip_generic *gc;
 113         struct irq_chip_type *ct;
 114
 115         if (used_gpioint_groups >= S5P_GPIOINT_GROUP_COUNT)
 116                 return -ENOMEM;
 117
 118         list_for_each_entry(bank, &banks, list) {
 119                 if (group >= bank->start &&
 120                     group < bank->start + bank->nr_groups)
 121                         break;
 122         }
 123         if (!bank)
 124                 return -EINVAL;
 125
 126         if (!bank->handler) {
 127                 bank->chips = kzalloc(sizeof(struct s3c_gpio_chip *) *
 128                                       bank->nr_groups, GFP_KERNEL);
 129                 if (!bank->chips)
 130                         return -ENOMEM;
 131
 132                 irq_set_chained_handler(bank->irq, s5p_gpioint_handler);
 133                 irq_set_handler_data(bank->irq, bank);
 134                 bank->handler = s5p_gpioint_handler;
 135                 printk(KERN_INFO "Registered chained gpio int handler for interrupt %d.\n",
 136                        bank->irq);
 137         }
 138
 139         /*
 140          * chained GPIO irq has been successfully registered, allocate new gpio
 141          * int group and assign irq nubmers
 142          */
 143         chip->irq_base = S5P_GPIOINT_BASE +
 144                          used_gpioint_groups * S5P_GPIOINT_GROUP_SIZE;
 145         used_gpioint_groups++;
 146
 147         bank->chips[group - bank->start] = chip;
 148
 149         gc = irq_alloc_generic_chip("s5p_gpioint", 1, chip->irq_base,
 150                                     (void __iomem *)GPIO_BASE(chip),
 151                                     handle_level_irq);
 152         if (!gc)
 153                 return -ENOMEM;
 154         ct = gc->chip_types;
 155         ct->chip.irq_ack = irq_gc_ack;
 156         ct->chip.irq_mask = irq_gc_mask_set_bit;
 157         ct->chip.irq_unmask = irq_gc_mask_clr_bit;
 158         ct->chip.irq_set_type = s5p_gpioint_set_type,
 159         ct->regs.ack = PEND_OFFSET + REG_OFFSET(chip->group);
 160         ct->regs.mask = MASK_OFFSET + REG_OFFSET(chip->group);
 161         ct->regs.type = CON_OFFSET + REG_OFFSET(chip->group);
 162         irq_setup_generic_chip(gc, IRQ_MSK(chip->chip.ngpio),
 163                                IRQ_GC_INIT_MASK_CACHE,
 164                                IRQ_NOREQUEST | IRQ_NOPROBE, 0);
 165         return 0;
 166 }
 167
 168 int __init s5p_register_gpio_interrupt(int pin)
 169 {
 170         struct s3c_gpio_chip *my_chip = s3c_gpiolib_getchip(pin);
 171         int offset, group;
 172         int ret;
 173
 174         if (!my_chip)
 175                 return -EINVAL;
 176
 177         offset = pin - my_chip->chip.base;
 178         group = my_chip->group;
 179
 180         /* check if the group has been already registered */
 181         if (my_chip->irq_base)
 182                 return my_chip->irq_base + offset;
 183
 184         /* register gpio group */
 185         ret = s5p_gpioint_add(my_chip);
 186         if (ret == 0) {
 187                 my_chip->chip.to_irq = samsung_gpiolib_to_irq;
 188                 printk(KERN_INFO "Registered interrupt support for gpio group %d.\n",
 189                        group);
 190                 return my_chip->irq_base + offset;
 191         }
 192         return ret;
 193 }
 194
 195 int __init s5p_register_gpioint_bank(int chain_irq, int start, int nr_groups)
 196 {
 197         struct s5p_gpioint_bank *bank;
 198
 199         bank = kzalloc(sizeof(*bank), GFP_KERNEL);
 200         if (!bank)
 201                 return -ENOMEM;
 202
 203         bank->start = start;
 204         bank->nr_groups = nr_groups;
 205         bank->irq = chain_irq;
 206
 207         list_add_tail(&bank->list, &banks);
 208         return 0;
 209 }