arch/arm/plat-orion/time.c

   1 /*
   2  * arch/arm/plat-orion/time.c
   3  *
   4  * Marvell Orion SoC timer handling.
   5  *
   6  * This file is licensed under the terms of the GNU General Public
   7  * License version 2.  This program is licensed "as is" without any
   8  * warranty of any kind, whether express or implied.
   9  *
  10  * Timer 0 is used as free-running clocksource, while timer 1 is
  11  * used as clock_event_device.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/sched.h>
  16 #include <linux/timer.h>
  17 #include <linux/clockchips.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/irq.h>
  20 #include <asm/sched_clock.h>
  21
  22 /*
  23  * MBus bridge block registers.
  24  */
  25 #define BRIDGE_CAUSE_OFF        0x0110
  26 #define BRIDGE_MASK_OFF         0x0114
  27 #define  BRIDGE_INT_TIMER0       0x0002
  28 #define  BRIDGE_INT_TIMER1       0x0004
  29
  30
  31 /*
  32  * Timer block registers.
  33  */
  34 #define TIMER_CTRL_OFF          0x0000
  35 #define  TIMER0_EN               0x0001
  36 #define  TIMER0_RELOAD_EN        0x0002
  37 #define  TIMER1_EN               0x0004
  38 #define  TIMER1_RELOAD_EN        0x0008
  39 #define TIMER0_RELOAD_OFF       0x0010
  40 #define TIMER0_VAL_OFF          0x0014
  41 #define TIMER1_RELOAD_OFF       0x0018
  42 #define TIMER1_VAL_OFF          0x001c
  43
  44
  45 /*
  46  * SoC-specific data.
  47  */
  48 static void __iomem *bridge_base;
  49 static u32 bridge_timer1_clr_mask;
  50 static void __iomem *timer_base;
  51
  52
  53 /*
  54  * Number of timer ticks per jiffy.
  55  */
  56 static u32 ticks_per_jiffy;
  57
  58
  59 /*
  60  * Orion's sched_clock implementation. It has a resolution of
  61  * at least 7.5ns (133MHz TCLK).
  62  */
  63 static DEFINE_CLOCK_DATA(cd);
  64
  65 unsigned long long notrace sched_clock(void)
  66 {
  67         u32 cyc = ~readl(timer_base + TIMER0_VAL_OFF);
  68         return cyc_to_sched_clock(&cd, cyc, (u32)~0);
  69 }
  70
  71
  72 static void notrace orion_update_sched_clock(void)
  73 {
  74         u32 cyc = ~readl(timer_base + TIMER0_VAL_OFF);
  75         update_sched_clock(&cd, cyc, (u32)~0);
  76 }
  77
  78 static void __init setup_sched_clock(unsigned long tclk)
  79 {
  80         init_sched_clock(&cd, orion_update_sched_clock, 32, tclk);
  81 }
  82
  83 /*
  84  * Clocksource handling.
  85  */
  86 static cycle_t orion_clksrc_read(struct clocksource *cs)
  87 {
  88         return 0xffffffff - readl(timer_base + TIMER0_VAL_OFF);
  89 }
  90
  91 static struct clocksource orion_clksrc = {
  92         .name           = "orion_clocksource",
  93         .rating         = 300,
  94         .read           = orion_clksrc_read,
  95         .mask           = CLOCKSOURCE_MASK(32),
  96         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
  97 };
  98
  99
 100
 101 /*
 102  * Clockevent handling.
 103  */
 104 static int
 105 orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
 106 {
 107         unsigned long flags;
 108         u32 u;
 109
 110         if (delta == 0)
 111                 return -ETIME;
 112
 113         local_irq_save(flags);
 114
 115         /*
 116          * Clear and enable clockevent timer interrupt.
 117          */
 118         writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
 119
 120         u = readl(bridge_base + BRIDGE_MASK_OFF);
 121         u |= BRIDGE_INT_TIMER1;
 122         writel(u, bridge_base + BRIDGE_MASK_OFF);
 123
 124         /*
 125          * Setup new clockevent timer value.
 126          */
 127         writel(delta, timer_base + TIMER1_VAL_OFF);
 128
 129         /*
 130          * Enable the timer.
 131          */
 132         u = readl(timer_base + TIMER_CTRL_OFF);
 133         u = (u & ~TIMER1_RELOAD_EN) | TIMER1_EN;
 134         writel(u, timer_base + TIMER_CTRL_OFF);
 135
 136         local_irq_restore(flags);
 137
 138         return 0;
 139 }
 140
 141 static void
 142 orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
 143 {
 144         unsigned long flags;
 145         u32 u;
 146
 147         local_irq_save(flags);
 148         if (mode == CLOCK_EVT_MODE_PERIODIC) {
 149                 /*
 150                  * Setup timer to fire at 1/HZ intervals.
 151                  */
 152                 writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD_OFF);
 153                 writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL_OFF);
 154
 155                 /*
 156                  * Enable timer interrupt.
 157                  */
 158                 u = readl(bridge_base + BRIDGE_MASK_OFF);
 159                 writel(u | BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF);
 160
 161                 /*
 162                  * Enable timer.
 163                  */
 164                 u = readl(timer_base + TIMER_CTRL_OFF);
 165                 writel(u | TIMER1_EN | TIMER1_RELOAD_EN,
 166                        timer_base + TIMER_CTRL_OFF);
 167         } else {
 168                 /*
 169                  * Disable timer.
 170                  */
 171                 u = readl(timer_base + TIMER_CTRL_OFF);
 172                 writel(u & ~TIMER1_EN, timer_base + TIMER_CTRL_OFF);
 173
 174                 /*
 175                  * Disable timer interrupt.
 176                  */
 177                 u = readl(bridge_base + BRIDGE_MASK_OFF);
 178                 writel(u & ~BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF);
 179
 180                 /*
 181                  * ACK pending timer interrupt.
 182                  */
 183                 writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
 184
 185         }
 186         local_irq_restore(flags);
 187 }
 188
 189 static struct clock_event_device orion_clkevt = {
 190         .name           = "orion_tick",
 191         .features       = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
 192         .shift          = 32,
 193         .rating         = 300,
 194         .set_next_event = orion_clkevt_next_event,
 195         .set_mode       = orion_clkevt_mode,
 196 };
 197
 198 static irqreturn_t orion_timer_interrupt(int irq, void *dev_id)
 199 {
 200         /*
 201          * ACK timer interrupt and call event handler.
 202          */
 203         writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
 204         orion_clkevt.event_handler(&orion_clkevt);
 205
 206         return IRQ_HANDLED;
 207 }
 208
 209 static struct irqaction orion_timer_irq = {
 210         .name           = "orion_tick",
 211         .flags          = IRQF_DISABLED | IRQF_TIMER,
 212         .handler        = orion_timer_interrupt
 213 };
 214
 215 void __init
 216 orion_time_set_base(u32 _timer_base)
 217 {
 218         timer_base = (void __iomem *)_timer_base;
 219 }
 220
 221 void __init
 222 orion_time_init(u32 _bridge_base, u32 _bridge_timer1_clr_mask,
 223                 unsigned int irq, unsigned int tclk)
 224 {
 225         u32 u;
 226
 227         /*
 228          * Set SoC-specific data.
 229          */
 230         bridge_base = (void __iomem *)_bridge_base;
 231         bridge_timer1_clr_mask = _bridge_timer1_clr_mask;
 232
 233         ticks_per_jiffy = (tclk + HZ/2) / HZ;
 234
 235         /*
 236          * Set scale and timer for sched_clock.
 237          */
 238         setup_sched_clock(tclk);
 239
 240         /*
 241          * Setup free-running clocksource timer (interrupts
 242          * disabled).
 243          */
 244         writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
 245         writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
 246         u = readl(bridge_base + BRIDGE_MASK_OFF);
 247         writel(u & ~BRIDGE_INT_TIMER0, bridge_base + BRIDGE_MASK_OFF);
 248         u = readl(timer_base + TIMER_CTRL_OFF);
 249         writel(u | TIMER0_EN | TIMER0_RELOAD_EN, timer_base + TIMER_CTRL_OFF);
 250         clocksource_register_hz(&orion_clksrc, tclk);
 251
 252         /*
 253          * Setup clockevent timer (interrupt-driven).
 254          */
 255         setup_irq(irq, &orion_timer_irq);
 256         orion_clkevt.mult = div_sc(tclk, NSEC_PER_SEC, orion_clkevt.shift);
 257         orion_clkevt.max_delta_ns = clockevent_delta2ns(0xfffffffe, &orion_clkevt);
 258         orion_clkevt.min_delta_ns = clockevent_delta2ns(1, &orion_clkevt);
 259         orion_clkevt.cpumask = cpumask_of(0);
 260         clockevents_register_device(&orion_clkevt);
 261 }