arch/arm/plat-omap/sram.c

   1 /*
   2  * linux/arch/arm/plat-omap/sram.c
   3  *
   4  * OMAP SRAM detection and management
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * Written by Tony Lindgren <tony@atomide.com>
   8  *
   9  * Copyright (C) 2009 Texas Instruments
  10  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16 #undef DEBUG
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/init.h>
  21 #include <linux/io.h>
  22
  23 #include <asm/tlb.h>
  24 #include <asm/cacheflush.h>
  25
  26 #include <asm/mach/map.h>
  27
  28 #include <plat/sram.h>
  29 #include <plat/board.h>
  30 #include <plat/cpu.h>
  31 #include <plat/vram.h>
  32
  33 #include <plat/control.h>
  34
  35 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
  36 # include "../mach-omap2/prm.h"
  37 # include "../mach-omap2/cm.h"
  38 # include "../mach-omap2/sdrc.h"
  39 #endif
  40
  41 #define OMAP1_SRAM_PA           0x20000000
  42 #define OMAP1_SRAM_VA           VMALLOC_END
  43 #define OMAP2_SRAM_PA           0x40200000
  44 #define OMAP2_SRAM_PUB_PA       0x4020f800
  45 #define OMAP2_SRAM_VA           0xfe400000
  46 #define OMAP2_SRAM_PUB_VA       (OMAP2_SRAM_VA + 0x800)
  47 #define OMAP3_SRAM_PA           0x40200000
  48 #define OMAP3_SRAM_VA           0xfe400000
  49 #define OMAP3_SRAM_PUB_PA       0x40208000
  50 #define OMAP3_SRAM_PUB_VA       (OMAP3_SRAM_VA + 0x8000)
  51 #define OMAP4_SRAM_PA           0x40300000
  52 #define OMAP4_SRAM_VA           0xfe400000
  53 #define OMAP4_SRAM_PUB_PA       (OMAP4_SRAM_PA + 0x4000)
  54 #define OMAP4_SRAM_PUB_VA       (OMAP4_SRAM_VA + 0x4000)
  55
  56 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
  57 #define SRAM_BOOTLOADER_SZ      0x00
  58 #else
  59 #define SRAM_BOOTLOADER_SZ      0x80
  60 #endif
  61
  62 #define OMAP24XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68005048)
  63 #define OMAP24XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68005050)
  64 #define OMAP24XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68005058)
  65
  66 #define OMAP34XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68012848)
  67 #define OMAP34XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68012850)
  68 #define OMAP34XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68012858)
  69 #define OMAP34XX_VA_ADDR_MATCH2         OMAP2_L3_IO_ADDRESS(0x68012880)
  70 #define OMAP34XX_VA_SMS_RG_ATT0         OMAP2_L3_IO_ADDRESS(0x6C000048)
  71 #define OMAP34XX_VA_CONTROL_STAT        OMAP2_L4_IO_ADDRESS(0x480022F0)
  72
  73 #define GP_DEVICE               0x300
  74
  75 #define ROUND_DOWN(value,boundary)      ((value) & (~((boundary)-1)))
  76
  77 static unsigned long omap_sram_start;
  78 static unsigned long omap_sram_base;
  79 static unsigned long omap_sram_size;
  80 static unsigned long omap_sram_ceil;
  81
  82 extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
  83                                          unsigned long sram_vstart,
  84                                          unsigned long sram_size,
  85                                          unsigned long pstart_avail,
  86                                          unsigned long size_avail);
  87
  88 /*
  89  * Depending on the target RAMFS firewall setup, the public usable amount of
  90  * SRAM varies.  The default accessible size for all device types is 2k. A GP
  91  * device allows ARM11 but not other initiators for full size. This
  92  * functionality seems ok until some nice security API happens.
  93  */
  94 static int is_sram_locked(void)
  95 {
  96         int type = 0;
  97
  98         if (cpu_is_omap44xx())
  99                 /* Not yet supported */
 100                 return 0;
 101
 102         if (cpu_is_omap242x())
 103                 type = omap_rev() & OMAP2_DEVICETYPE_MASK;
 104
 105         if (type == GP_DEVICE) {
 106                 /* RAMFW: R/W access to all initiators for all qualifier sets */
 107                 if (cpu_is_omap242x()) {
 108                         __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
 109                         __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0);  /* all i-read */
 110                         __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
 111                 }
 112                 if (cpu_is_omap34xx()) {
 113                         __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
 114                         __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0);  /* all i-read */
 115                         __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
 116                         __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
 117                         __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
 118                 }
 119                 return 0;
 120         } else
 121                 return 1; /* assume locked with no PPA or security driver */
 122 }
 123
 124 /*
 125  * The amount of SRAM depends on the core type.
 126  * Note that we cannot try to test for SRAM here because writes
 127  * to secure SRAM will hang the system. Also the SRAM is not
 128  * yet mapped at this point.
 129  */
 130 void __init omap_detect_sram(void)
 131 {
 132         unsigned long reserved;
 133
 134         if (cpu_class_is_omap2()) {
 135                 if (is_sram_locked()) {
 136                         if (cpu_is_omap34xx()) {
 137                                 omap_sram_base = OMAP3_SRAM_PUB_VA;
 138                                 omap_sram_start = OMAP3_SRAM_PUB_PA;
 139                                 if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
 140                                     (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
 141                                         omap_sram_size = 0x7000; /* 28K */
 142                                 } else {
 143                                         omap_sram_size = 0x8000; /* 32K */
 144                                 }
 145                         } else if (cpu_is_omap44xx()) {
 146                                 omap_sram_base = OMAP4_SRAM_PUB_VA;
 147                                 omap_sram_start = OMAP4_SRAM_PUB_PA;
 148                                 omap_sram_size = 0xa000; /* 40K */
 149                         } else {
 150                                 omap_sram_base = OMAP2_SRAM_PUB_VA;
 151                                 omap_sram_start = OMAP2_SRAM_PUB_PA;
 152                                 omap_sram_size = 0x800; /* 2K */
 153                         }
 154                 } else {
 155                         if (cpu_is_omap34xx()) {
 156                                 omap_sram_base = OMAP3_SRAM_VA;
 157                                 omap_sram_start = OMAP3_SRAM_PA;
 158                                 omap_sram_size = 0x10000; /* 64K */
 159                         } else if (cpu_is_omap44xx()) {
 160                                 omap_sram_base = OMAP4_SRAM_VA;
 161                                 omap_sram_start = OMAP4_SRAM_PA;
 162                                 omap_sram_size = 0xe000; /* 56K */
 163                         } else {
 164                                 omap_sram_base = OMAP2_SRAM_VA;
 165                                 omap_sram_start = OMAP2_SRAM_PA;
 166                                 if (cpu_is_omap242x())
 167                                         omap_sram_size = 0xa0000; /* 640K */
 168                                 else if (cpu_is_omap243x())
 169                                         omap_sram_size = 0x10000; /* 64K */
 170                         }
 171                 }
 172         } else {
 173                 omap_sram_base = OMAP1_SRAM_VA;
 174                 omap_sram_start = OMAP1_SRAM_PA;
 175
 176                 if (cpu_is_omap7xx())
 177                         omap_sram_size = 0x32000;       /* 200K */
 178                 else if (cpu_is_omap15xx())
 179                         omap_sram_size = 0x30000;       /* 192K */
 180                 else if (cpu_is_omap1610() || cpu_is_omap1621() ||
 181                      cpu_is_omap1710())
 182                         omap_sram_size = 0x4000;        /* 16K */
 183                 else if (cpu_is_omap1611())
 184                         omap_sram_size = 0x3e800;       /* 250K */
 185                 else {
 186                         printk(KERN_ERR "Could not detect SRAM size\n");
 187                         omap_sram_size = 0x4000;
 188                 }
 189         }
 190         reserved = omapfb_reserve_sram(omap_sram_start, omap_sram_base,
 191                                        omap_sram_size,
 192                                        omap_sram_start + SRAM_BOOTLOADER_SZ,
 193                                        omap_sram_size - SRAM_BOOTLOADER_SZ);
 194         omap_sram_size -= reserved;
 195
 196         reserved = omap_vram_reserve_sram(omap_sram_start, omap_sram_base,
 197                         omap_sram_size,
 198                         omap_sram_start + SRAM_BOOTLOADER_SZ,
 199                         omap_sram_size - SRAM_BOOTLOADER_SZ);
 200         omap_sram_size -= reserved;
 201
 202         omap_sram_ceil = omap_sram_base + omap_sram_size;
 203 }
 204
 205 static struct map_desc omap_sram_io_desc[] __initdata = {
 206         {       /* .length gets filled in at runtime */
 207                 .virtual        = OMAP1_SRAM_VA,
 208                 .pfn            = __phys_to_pfn(OMAP1_SRAM_PA),
 209                 .type           = MT_MEMORY
 210         }
 211 };
 212
 213 /*
 214  * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
 215  */
 216 void __init omap_map_sram(void)
 217 {
 218         unsigned long base;
 219
 220         if (omap_sram_size == 0)
 221                 return;
 222
 223         if (cpu_is_omap24xx()) {
 224                 omap_sram_io_desc[0].virtual = OMAP2_SRAM_VA;
 225
 226                 base = OMAP2_SRAM_PA;
 227                 base = ROUND_DOWN(base, PAGE_SIZE);
 228                 omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
 229         }
 230
 231         if (cpu_is_omap34xx()) {
 232                 omap_sram_io_desc[0].virtual = OMAP3_SRAM_VA;
 233                 base = OMAP3_SRAM_PA;
 234                 base = ROUND_DOWN(base, PAGE_SIZE);
 235                 omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
 236
 237                 /*
 238                  * SRAM must be marked as non-cached on OMAP3 since the
 239                  * CORE DPLL M2 divider change code (in SRAM) runs with the
 240                  * SDRAM controller disabled, and if it is marked cached,
 241                  * the ARM may attempt to write cache lines back to SDRAM
 242                  * which will cause the system to hang.
 243                  */
 244                 omap_sram_io_desc[0].type = MT_MEMORY_NONCACHED;
 245         }
 246
 247         if (cpu_is_omap44xx()) {
 248                 omap_sram_io_desc[0].virtual = OMAP4_SRAM_VA;
 249                 base = OMAP4_SRAM_PA;
 250                 base = ROUND_DOWN(base, PAGE_SIZE);
 251                 omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
 252         }
 253         omap_sram_io_desc[0].length = 1024 * 1024;      /* Use section desc */
 254         iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc));
 255
 256         printk(KERN_INFO "SRAM: Mapped pa 0x%08lx to va 0x%08lx size: 0x%lx\n",
 257         __pfn_to_phys(omap_sram_io_desc[0].pfn),
 258         omap_sram_io_desc[0].virtual,
 259                omap_sram_io_desc[0].length);
 260
 261         /*
 262          * Normally devicemaps_init() would flush caches and tlb after
 263          * mdesc->map_io(), but since we're called from map_io(), we
 264          * must do it here.
 265          */
 266         local_flush_tlb_all();
 267         flush_cache_all();
 268
 269         /*
 270          * Looks like we need to preserve some bootloader code at the
 271          * beginning of SRAM for jumping to flash for reboot to work...
 272          */
 273         memset((void *)omap_sram_base + SRAM_BOOTLOADER_SZ, 0,
 274                omap_sram_size - SRAM_BOOTLOADER_SZ);
 275 }
 276
 277 void * omap_sram_push(void * start, unsigned long size)
 278 {
 279         if (size > (omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ))) {
 280                 printk(KERN_ERR "Not enough space in SRAM\n");
 281                 return NULL;
 282         }
 283
 284         omap_sram_ceil -= size;
 285         omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, sizeof(void *));
 286         memcpy((void *)omap_sram_ceil, start, size);
 287         flush_icache_range((unsigned long)omap_sram_ceil,
 288                 (unsigned long)(omap_sram_ceil + size));
 289
 290         return (void *)omap_sram_ceil;
 291 }
 292
 293 #ifdef CONFIG_ARCH_OMAP1
 294
 295 static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);
 296
 297 void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
 298 {
 299         BUG_ON(!_omap_sram_reprogram_clock);
 300         _omap_sram_reprogram_clock(dpllctl, ckctl);
 301 }
 302
 303 int __init omap1_sram_init(void)
 304 {
 305         _omap_sram_reprogram_clock =
 306                         omap_sram_push(omap1_sram_reprogram_clock,
 307                                         omap1_sram_reprogram_clock_sz);
 308
 309         return 0;
 310 }
 311
 312 #else
 313 #define omap1_sram_init()       do {} while (0)
 314 #endif
 315
 316 #if defined(CONFIG_ARCH_OMAP2)
 317
 318 static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
 319                               u32 base_cs, u32 force_unlock);
 320
 321 void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
 322                    u32 base_cs, u32 force_unlock)
 323 {
 324         BUG_ON(!_omap2_sram_ddr_init);
 325         _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
 326                              base_cs, force_unlock);
 327 }
 328
 329 static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
 330                                           u32 mem_type);
 331
 332 void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
 333 {
 334         BUG_ON(!_omap2_sram_reprogram_sdrc);
 335         _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
 336 }
 337
 338 static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
 339
 340 u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
 341 {
 342         BUG_ON(!_omap2_set_prcm);
 343         return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
 344 }
 345 #endif
 346
 347 #ifdef CONFIG_ARCH_OMAP2420
 348 int __init omap242x_sram_init(void)
 349 {
 350         _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
 351                                         omap242x_sram_ddr_init_sz);
 352
 353         _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
 354                                             omap242x_sram_reprogram_sdrc_sz);
 355
 356         _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
 357                                          omap242x_sram_set_prcm_sz);
 358
 359         return 0;
 360 }
 361 #else
 362 static inline int omap242x_sram_init(void)
 363 {
 364         return 0;
 365 }
 366 #endif
 367
 368 #ifdef CONFIG_ARCH_OMAP2430
 369 int __init omap243x_sram_init(void)
 370 {
 371         _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
 372                                         omap243x_sram_ddr_init_sz);
 373
 374         _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
 375                                             omap243x_sram_reprogram_sdrc_sz);
 376
 377         _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
 378                                          omap243x_sram_set_prcm_sz);
 379
 380         return 0;
 381 }
 382 #else
 383 static inline int omap243x_sram_init(void)
 384 {
 385         return 0;
 386 }
 387 #endif
 388
 389 #ifdef CONFIG_ARCH_OMAP3
 390
 391 static u32 (*_omap3_sram_configure_core_dpll)(
 392                         u32 m2, u32 unlock_dll, u32 f, u32 inc,
 393                         u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
 394                         u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
 395                         u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
 396                         u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
 397
 398 u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
 399                         u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
 400                         u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
 401                         u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
 402                         u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
 403 {
 404         BUG_ON(!_omap3_sram_configure_core_dpll);
 405         return _omap3_sram_configure_core_dpll(
 406                         m2, unlock_dll, f, inc,
 407                         sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
 408                         sdrc_actim_ctrl_b_0, sdrc_mr_0,
 409                         sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
 410                         sdrc_actim_ctrl_b_1, sdrc_mr_1);
 411 }
 412
 413 #ifdef CONFIG_PM
 414 void omap3_sram_restore_context(void)
 415 {
 416         omap_sram_ceil = omap_sram_base + omap_sram_size;
 417
 418         _omap3_sram_configure_core_dpll =
 419                 omap_sram_push(omap3_sram_configure_core_dpll,
 420                                omap3_sram_configure_core_dpll_sz);
 421         omap_push_sram_idle();
 422 }
 423 #endif /* CONFIG_PM */
 424
 425 int __init omap34xx_sram_init(void)
 426 {
 427         _omap3_sram_configure_core_dpll =
 428                 omap_sram_push(omap3_sram_configure_core_dpll,
 429                                omap3_sram_configure_core_dpll_sz);
 430         omap_push_sram_idle();
 431         return 0;
 432 }
 433 #else
 434 static inline int omap34xx_sram_init(void)
 435 {
 436         return 0;
 437 }
 438 #endif
 439
 440 int __init omap_sram_init(void)
 441 {
 442         omap_detect_sram();
 443         omap_map_sram();
 444
 445         if (!(cpu_class_is_omap2()))
 446                 omap1_sram_init();
 447         else if (cpu_is_omap242x())
 448                 omap242x_sram_init();
 449         else if (cpu_is_omap2430())
 450                 omap243x_sram_init();
 451         else if (cpu_is_omap34xx())
 452                 omap34xx_sram_init();
 453         else if (cpu_is_omap44xx())
 454                 omap34xx_sram_init(); /* FIXME: */
 455
 456         return 0;
 457 }