arch/arm/plat-omap/mcbsp.c

   1 /*
   2  * linux/arch/arm/plat-omap/mcbsp.c
   3  *
   4  * Copyright (C) 2004 Nokia Corporation
   5  * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
   6  *
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * Multichannel mode not supported.
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/device.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/wait.h>
  20 #include <linux/completion.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/err.h>
  23 #include <linux/clk.h>
  24 #include <linux/delay.h>
  25 #include <linux/io.h>
  26 #include <linux/slab.h>
  27
  28 #include <plat/dma.h>
  29 #include <plat/mcbsp.h>
  30
  31 /* XXX These "sideways" includes are a sign that something is wrong */
  32 #include "../mach-omap2/cm2xxx_3xxx.h"
  33 #include "../mach-omap2/cm-regbits-34xx.h"
  34
  35 struct omap_mcbsp **mcbsp_ptr;
  36 int omap_mcbsp_count, omap_mcbsp_cache_size;
  37
  38 static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
  39 {
  40         if (cpu_class_is_omap1()) {
  41                 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)] = (u16)val;
  42                 __raw_writew((u16)val, mcbsp->io_base + reg);
  43         } else if (cpu_is_omap2420()) {
  44                 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)] = (u16)val;
  45                 __raw_writew((u16)val, mcbsp->io_base + reg);
  46         } else {
  47                 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)] = val;
  48                 __raw_writel(val, mcbsp->io_base + reg);
  49         }
  50 }
  51
  52 static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
  53 {
  54         if (cpu_class_is_omap1()) {
  55                 return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
  56                                 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)];
  57         } else if (cpu_is_omap2420()) {
  58                 return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
  59                                 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)];
  60         } else {
  61                 return !from_cache ? __raw_readl(mcbsp->io_base + reg) :
  62                                 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)];
  63         }
  64 }
  65
  66 #ifdef CONFIG_ARCH_OMAP3
  67 static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
  68 {
  69         __raw_writel(val, mcbsp->st_data->io_base_st + reg);
  70 }
  71
  72 static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
  73 {
  74         return __raw_readl(mcbsp->st_data->io_base_st + reg);
  75 }
  76 #endif
  77
  78 #define MCBSP_READ(mcbsp, reg) \
  79                 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
  80 #define MCBSP_WRITE(mcbsp, reg, val) \
  81                 omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
  82 #define MCBSP_READ_CACHE(mcbsp, reg) \
  83                 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
  84
  85 #define MCBSP_ST_READ(mcbsp, reg) \
  86                         omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
  87 #define MCBSP_ST_WRITE(mcbsp, reg, val) \
  88                         omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
  89
  90 static void omap_mcbsp_dump_reg(u8 id)
  91 {
  92         struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
  93
  94         dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
  95         dev_dbg(mcbsp->dev, "DRR2:  0x%04x\n",
  96                         MCBSP_READ(mcbsp, DRR2));
  97         dev_dbg(mcbsp->dev, "DRR1:  0x%04x\n",
  98                         MCBSP_READ(mcbsp, DRR1));
  99         dev_dbg(mcbsp->dev, "DXR2:  0x%04x\n",
 100                         MCBSP_READ(mcbsp, DXR2));
 101         dev_dbg(mcbsp->dev, "DXR1:  0x%04x\n",
 102                         MCBSP_READ(mcbsp, DXR1));
 103         dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
 104                         MCBSP_READ(mcbsp, SPCR2));
 105         dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
 106                         MCBSP_READ(mcbsp, SPCR1));
 107         dev_dbg(mcbsp->dev, "RCR2:  0x%04x\n",
 108                         MCBSP_READ(mcbsp, RCR2));
 109         dev_dbg(mcbsp->dev, "RCR1:  0x%04x\n",
 110                         MCBSP_READ(mcbsp, RCR1));
 111         dev_dbg(mcbsp->dev, "XCR2:  0x%04x\n",
 112                         MCBSP_READ(mcbsp, XCR2));
 113         dev_dbg(mcbsp->dev, "XCR1:  0x%04x\n",
 114                         MCBSP_READ(mcbsp, XCR1));
 115         dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
 116                         MCBSP_READ(mcbsp, SRGR2));
 117         dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
 118                         MCBSP_READ(mcbsp, SRGR1));
 119         dev_dbg(mcbsp->dev, "PCR0:  0x%04x\n",
 120                         MCBSP_READ(mcbsp, PCR0));
 121         dev_dbg(mcbsp->dev, "***********************\n");
 122 }
 123
 124 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
 125 {
 126         struct omap_mcbsp *mcbsp_tx = dev_id;
 127         u16 irqst_spcr2;
 128
 129         irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2);
 130         dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
 131
 132         if (irqst_spcr2 & XSYNC_ERR) {
 133                 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
 134                         irqst_spcr2);
 135                 /* Writing zero to XSYNC_ERR clears the IRQ */
 136                 MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2));
 137         } else {
 138                 complete(&mcbsp_tx->tx_irq_completion);
 139         }
 140
 141         return IRQ_HANDLED;
 142 }
 143
 144 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
 145 {
 146         struct omap_mcbsp *mcbsp_rx = dev_id;
 147         u16 irqst_spcr1;
 148
 149         irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1);
 150         dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
 151
 152         if (irqst_spcr1 & RSYNC_ERR) {
 153                 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
 154                         irqst_spcr1);
 155                 /* Writing zero to RSYNC_ERR clears the IRQ */
 156                 MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
 157         } else {
 158                 complete(&mcbsp_rx->rx_irq_completion);
 159         }
 160
 161         return IRQ_HANDLED;
 162 }
 163
 164 static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
 165 {
 166         struct omap_mcbsp *mcbsp_dma_tx = data;
 167
 168         dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
 169                 MCBSP_READ(mcbsp_dma_tx, SPCR2));
 170
 171         /* We can free the channels */
 172         omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
 173         mcbsp_dma_tx->dma_tx_lch = -1;
 174
 175         complete(&mcbsp_dma_tx->tx_dma_completion);
 176 }
 177
 178 static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
 179 {
 180         struct omap_mcbsp *mcbsp_dma_rx = data;
 181
 182         dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
 183                 MCBSP_READ(mcbsp_dma_rx, SPCR2));
 184
 185         /* We can free the channels */
 186         omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
 187         mcbsp_dma_rx->dma_rx_lch = -1;
 188
 189         complete(&mcbsp_dma_rx->rx_dma_completion);
 190 }
 191
 192 /*
 193  * omap_mcbsp_config simply write a config to the
 194  * appropriate McBSP.
 195  * You either call this function or set the McBSP registers
 196  * by yourself before calling omap_mcbsp_start().
 197  */
 198 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
 199 {
 200         struct omap_mcbsp *mcbsp;
 201
 202         if (!omap_mcbsp_check_valid_id(id)) {
 203                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 204                 return;
 205         }
 206         mcbsp = id_to_mcbsp_ptr(id);
 207
 208         dev_dbg(mcbsp->dev, "Configuring McBSP%d  phys_base: 0x%08lx\n",
 209                         mcbsp->id, mcbsp->phys_base);
 210
 211         /* We write the given config */
 212         MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
 213         MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
 214         MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
 215         MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
 216         MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
 217         MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
 218         MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
 219         MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
 220         MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
 221         MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
 222         MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
 223         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
 224                 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
 225                 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
 226         }
 227 }
 228 EXPORT_SYMBOL(omap_mcbsp_config);
 229
 230 #ifdef CONFIG_ARCH_OMAP3
 231 static void omap_st_on(struct omap_mcbsp *mcbsp)
 232 {
 233         unsigned int w;
 234
 235         /*
 236          * Sidetone uses McBSP ICLK - which must not idle when sidetones
 237          * are enabled or sidetones start sounding ugly.
 238          */
 239         w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
 240         w &= ~(1 << (mcbsp->id - 2));
 241         omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
 242
 243         /* Enable McBSP Sidetone */
 244         w = MCBSP_READ(mcbsp, SSELCR);
 245         MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
 246
 247         w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
 248         MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE));
 249
 250         /* Enable Sidetone from Sidetone Core */
 251         w = MCBSP_ST_READ(mcbsp, SSELCR);
 252         MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
 253 }
 254
 255 static void omap_st_off(struct omap_mcbsp *mcbsp)
 256 {
 257         unsigned int w;
 258
 259         w = MCBSP_ST_READ(mcbsp, SSELCR);
 260         MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
 261
 262         w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
 263         MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w | ST_AUTOIDLE);
 264
 265         w = MCBSP_READ(mcbsp, SSELCR);
 266         MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
 267
 268         w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
 269         w |= 1 << (mcbsp->id - 2);
 270         omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
 271 }
 272
 273 static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
 274 {
 275         u16 val, i;
 276
 277         val = MCBSP_ST_READ(mcbsp, SYSCONFIG);
 278         MCBSP_ST_WRITE(mcbsp, SYSCONFIG, val & ~(ST_AUTOIDLE));
 279
 280         val = MCBSP_ST_READ(mcbsp, SSELCR);
 281
 282         if (val & ST_COEFFWREN)
 283                 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
 284
 285         MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN);
 286
 287         for (i = 0; i < 128; i++)
 288                 MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]);
 289
 290         i = 0;
 291
 292         val = MCBSP_ST_READ(mcbsp, SSELCR);
 293         while (!(val & ST_COEFFWRDONE) && (++i < 1000))
 294                 val = MCBSP_ST_READ(mcbsp, SSELCR);
 295
 296         MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
 297
 298         if (i == 1000)
 299                 dev_err(mcbsp->dev, "McBSP FIR load error!\n");
 300 }
 301
 302 static void omap_st_chgain(struct omap_mcbsp *mcbsp)
 303 {
 304         u16 w;
 305         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 306
 307         w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
 308         MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE));
 309
 310         w = MCBSP_ST_READ(mcbsp, SSELCR);
 311
 312         MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \
 313                       ST_CH1GAIN(st_data->ch1gain));
 314 }
 315
 316 int omap_st_set_chgain(unsigned int id, int channel, s16 chgain)
 317 {
 318         struct omap_mcbsp *mcbsp;
 319         struct omap_mcbsp_st_data *st_data;
 320         int ret = 0;
 321
 322         if (!omap_mcbsp_check_valid_id(id)) {
 323                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 324                 return -ENODEV;
 325         }
 326
 327         mcbsp = id_to_mcbsp_ptr(id);
 328         st_data = mcbsp->st_data;
 329
 330         if (!st_data)
 331                 return -ENOENT;
 332
 333         spin_lock_irq(&mcbsp->lock);
 334         if (channel == 0)
 335                 st_data->ch0gain = chgain;
 336         else if (channel == 1)
 337                 st_data->ch1gain = chgain;
 338         else
 339                 ret = -EINVAL;
 340
 341         if (st_data->enabled)
 342                 omap_st_chgain(mcbsp);
 343         spin_unlock_irq(&mcbsp->lock);
 344
 345         return ret;
 346 }
 347 EXPORT_SYMBOL(omap_st_set_chgain);
 348
 349 int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain)
 350 {
 351         struct omap_mcbsp *mcbsp;
 352         struct omap_mcbsp_st_data *st_data;
 353         int ret = 0;
 354
 355         if (!omap_mcbsp_check_valid_id(id)) {
 356                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 357                 return -ENODEV;
 358         }
 359
 360         mcbsp = id_to_mcbsp_ptr(id);
 361         st_data = mcbsp->st_data;
 362
 363         if (!st_data)
 364                 return -ENOENT;
 365
 366         spin_lock_irq(&mcbsp->lock);
 367         if (channel == 0)
 368                 *chgain = st_data->ch0gain;
 369         else if (channel == 1)
 370                 *chgain = st_data->ch1gain;
 371         else
 372                 ret = -EINVAL;
 373         spin_unlock_irq(&mcbsp->lock);
 374
 375         return ret;
 376 }
 377 EXPORT_SYMBOL(omap_st_get_chgain);
 378
 379 static int omap_st_start(struct omap_mcbsp *mcbsp)
 380 {
 381         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 382
 383         if (st_data && st_data->enabled && !st_data->running) {
 384                 omap_st_fir_write(mcbsp, st_data->taps);
 385                 omap_st_chgain(mcbsp);
 386
 387                 if (!mcbsp->free) {
 388                         omap_st_on(mcbsp);
 389                         st_data->running = 1;
 390                 }
 391         }
 392
 393         return 0;
 394 }
 395
 396 int omap_st_enable(unsigned int id)
 397 {
 398         struct omap_mcbsp *mcbsp;
 399         struct omap_mcbsp_st_data *st_data;
 400
 401         if (!omap_mcbsp_check_valid_id(id)) {
 402                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 403                 return -ENODEV;
 404         }
 405
 406         mcbsp = id_to_mcbsp_ptr(id);
 407         st_data = mcbsp->st_data;
 408
 409         if (!st_data)
 410                 return -ENODEV;
 411
 412         spin_lock_irq(&mcbsp->lock);
 413         st_data->enabled = 1;
 414         omap_st_start(mcbsp);
 415         spin_unlock_irq(&mcbsp->lock);
 416
 417         return 0;
 418 }
 419 EXPORT_SYMBOL(omap_st_enable);
 420
 421 static int omap_st_stop(struct omap_mcbsp *mcbsp)
 422 {
 423         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 424
 425         if (st_data && st_data->running) {
 426                 if (!mcbsp->free) {
 427                         omap_st_off(mcbsp);
 428                         st_data->running = 0;
 429                 }
 430         }
 431
 432         return 0;
 433 }
 434
 435 int omap_st_disable(unsigned int id)
 436 {
 437         struct omap_mcbsp *mcbsp;
 438         struct omap_mcbsp_st_data *st_data;
 439         int ret = 0;
 440
 441         if (!omap_mcbsp_check_valid_id(id)) {
 442                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 443                 return -ENODEV;
 444         }
 445
 446         mcbsp = id_to_mcbsp_ptr(id);
 447         st_data = mcbsp->st_data;
 448
 449         if (!st_data)
 450                 return -ENODEV;
 451
 452         spin_lock_irq(&mcbsp->lock);
 453         omap_st_stop(mcbsp);
 454         st_data->enabled = 0;
 455         spin_unlock_irq(&mcbsp->lock);
 456
 457         return ret;
 458 }
 459 EXPORT_SYMBOL(omap_st_disable);
 460
 461 int omap_st_is_enabled(unsigned int id)
 462 {
 463         struct omap_mcbsp *mcbsp;
 464         struct omap_mcbsp_st_data *st_data;
 465
 466         if (!omap_mcbsp_check_valid_id(id)) {
 467                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 468                 return -ENODEV;
 469         }
 470
 471         mcbsp = id_to_mcbsp_ptr(id);
 472         st_data = mcbsp->st_data;
 473
 474         if (!st_data)
 475                 return -ENODEV;
 476
 477
 478         return st_data->enabled;
 479 }
 480 EXPORT_SYMBOL(omap_st_is_enabled);
 481
 482 /*
 483  * omap_mcbsp_set_rx_threshold configures the transmit threshold in words.
 484  * The threshold parameter is 1 based, and it is converted (threshold - 1)
 485  * for the THRSH2 register.
 486  */
 487 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
 488 {
 489         struct omap_mcbsp *mcbsp;
 490
 491         if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
 492                 return;
 493
 494         if (!omap_mcbsp_check_valid_id(id)) {
 495                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 496                 return;
 497         }
 498         mcbsp = id_to_mcbsp_ptr(id);
 499
 500         if (threshold && threshold <= mcbsp->max_tx_thres)
 501                 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
 502 }
 503 EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
 504
 505 /*
 506  * omap_mcbsp_set_rx_threshold configures the receive threshold in words.
 507  * The threshold parameter is 1 based, and it is converted (threshold - 1)
 508  * for the THRSH1 register.
 509  */
 510 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
 511 {
 512         struct omap_mcbsp *mcbsp;
 513
 514         if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
 515                 return;
 516
 517         if (!omap_mcbsp_check_valid_id(id)) {
 518                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 519                 return;
 520         }
 521         mcbsp = id_to_mcbsp_ptr(id);
 522
 523         if (threshold && threshold <= mcbsp->max_rx_thres)
 524                 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
 525 }
 526 EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
 527
 528 /*
 529  * omap_mcbsp_get_max_tx_thres just return the current configured
 530  * maximum threshold for transmission
 531  */
 532 u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
 533 {
 534         struct omap_mcbsp *mcbsp;
 535
 536         if (!omap_mcbsp_check_valid_id(id)) {
 537                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 538                 return -ENODEV;
 539         }
 540         mcbsp = id_to_mcbsp_ptr(id);
 541
 542         return mcbsp->max_tx_thres;
 543 }
 544 EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
 545
 546 /*
 547  * omap_mcbsp_get_max_rx_thres just return the current configured
 548  * maximum threshold for reception
 549  */
 550 u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
 551 {
 552         struct omap_mcbsp *mcbsp;
 553
 554         if (!omap_mcbsp_check_valid_id(id)) {
 555                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 556                 return -ENODEV;
 557         }
 558         mcbsp = id_to_mcbsp_ptr(id);
 559
 560         return mcbsp->max_rx_thres;
 561 }
 562 EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
 563
 564 u16 omap_mcbsp_get_fifo_size(unsigned int id)
 565 {
 566         struct omap_mcbsp *mcbsp;
 567
 568         if (!omap_mcbsp_check_valid_id(id)) {
 569                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 570                 return -ENODEV;
 571         }
 572         mcbsp = id_to_mcbsp_ptr(id);
 573
 574         return mcbsp->pdata->buffer_size;
 575 }
 576 EXPORT_SYMBOL(omap_mcbsp_get_fifo_size);
 577
 578 /*
 579  * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
 580  */
 581 u16 omap_mcbsp_get_tx_delay(unsigned int id)
 582 {
 583         struct omap_mcbsp *mcbsp;
 584         u16 buffstat;
 585
 586         if (!omap_mcbsp_check_valid_id(id)) {
 587                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 588                 return -ENODEV;
 589         }
 590         mcbsp = id_to_mcbsp_ptr(id);
 591
 592         /* Returns the number of free locations in the buffer */
 593         buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
 594
 595         /* Number of slots are different in McBSP ports */
 596         return mcbsp->pdata->buffer_size - buffstat;
 597 }
 598 EXPORT_SYMBOL(omap_mcbsp_get_tx_delay);
 599
 600 /*
 601  * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
 602  * to reach the threshold value (when the DMA will be triggered to read it)
 603  */
 604 u16 omap_mcbsp_get_rx_delay(unsigned int id)
 605 {
 606         struct omap_mcbsp *mcbsp;
 607         u16 buffstat, threshold;
 608
 609         if (!omap_mcbsp_check_valid_id(id)) {
 610                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 611                 return -ENODEV;
 612         }
 613         mcbsp = id_to_mcbsp_ptr(id);
 614
 615         /* Returns the number of used locations in the buffer */
 616         buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
 617         /* RX threshold */
 618         threshold = MCBSP_READ(mcbsp, THRSH1);
 619
 620         /* Return the number of location till we reach the threshold limit */
 621         if (threshold <= buffstat)
 622                 return 0;
 623         else
 624                 return threshold - buffstat;
 625 }
 626 EXPORT_SYMBOL(omap_mcbsp_get_rx_delay);
 627
 628 /*
 629  * omap_mcbsp_get_dma_op_mode just return the current configured
 630  * operating mode for the mcbsp channel
 631  */
 632 int omap_mcbsp_get_dma_op_mode(unsigned int id)
 633 {
 634         struct omap_mcbsp *mcbsp;
 635         int dma_op_mode;
 636
 637         if (!omap_mcbsp_check_valid_id(id)) {
 638                 printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1);
 639                 return -ENODEV;
 640         }
 641         mcbsp = id_to_mcbsp_ptr(id);
 642
 643         dma_op_mode = mcbsp->dma_op_mode;
 644
 645         return dma_op_mode;
 646 }
 647 EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
 648
 649 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
 650 {
 651         /*
 652          * Enable wakup behavior, smart idle and all wakeups
 653          * REVISIT: some wakeups may be unnecessary
 654          */
 655         if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
 656                 u16 syscon;
 657
 658                 syscon = MCBSP_READ(mcbsp, SYSCON);
 659                 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
 660
 661                 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
 662                         syscon |= (ENAWAKEUP | SIDLEMODE(0x02) |
 663                                         CLOCKACTIVITY(0x02));
 664                         MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
 665                 } else {
 666                         syscon |= SIDLEMODE(0x01);
 667                 }
 668
 669                 MCBSP_WRITE(mcbsp, SYSCON, syscon);
 670         }
 671 }
 672
 673 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
 674 {
 675         /*
 676          * Disable wakup behavior, smart idle and all wakeups
 677          */
 678         if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
 679                 u16 syscon;
 680
 681                 syscon = MCBSP_READ(mcbsp, SYSCON);
 682                 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
 683                 /*
 684                  * HW bug workaround - If no_idle mode is taken, we need to
 685                  * go to smart_idle before going to always_idle, or the
 686                  * device will not hit retention anymore.
 687                  */
 688                 syscon |= SIDLEMODE(0x02);
 689                 MCBSP_WRITE(mcbsp, SYSCON, syscon);
 690
 691                 syscon &= ~(SIDLEMODE(0x03));
 692                 MCBSP_WRITE(mcbsp, SYSCON, syscon);
 693
 694                 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
 695         }
 696 }
 697 #else
 698 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {}
 699 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {}
 700 static inline void omap_st_start(struct omap_mcbsp *mcbsp) {}
 701 static inline void omap_st_stop(struct omap_mcbsp *mcbsp) {}
 702 #endif
 703
 704 /*
 705  * We can choose between IRQ based or polled IO.
 706  * This needs to be called before omap_mcbsp_request().
 707  */
 708 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
 709 {
 710         struct omap_mcbsp *mcbsp;
 711
 712         if (!omap_mcbsp_check_valid_id(id)) {
 713                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 714                 return -ENODEV;
 715         }
 716         mcbsp = id_to_mcbsp_ptr(id);
 717
 718         spin_lock(&mcbsp->lock);
 719
 720         if (!mcbsp->free) {
 721                 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
 722                         mcbsp->id);
 723                 spin_unlock(&mcbsp->lock);
 724                 return -EINVAL;
 725         }
 726
 727         mcbsp->io_type = io_type;
 728
 729         spin_unlock(&mcbsp->lock);
 730
 731         return 0;
 732 }
 733 EXPORT_SYMBOL(omap_mcbsp_set_io_type);
 734
 735 int omap_mcbsp_request(unsigned int id)
 736 {
 737         struct omap_mcbsp *mcbsp;
 738         void *reg_cache;
 739         int err;
 740
 741         if (!omap_mcbsp_check_valid_id(id)) {
 742                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 743                 return -ENODEV;
 744         }
 745         mcbsp = id_to_mcbsp_ptr(id);
 746
 747         reg_cache = kzalloc(omap_mcbsp_cache_size, GFP_KERNEL);
 748         if (!reg_cache) {
 749                 return -ENOMEM;
 750         }
 751
 752         spin_lock(&mcbsp->lock);
 753         if (!mcbsp->free) {
 754                 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
 755                         mcbsp->id);
 756                 err = -EBUSY;
 757                 goto err_kfree;
 758         }
 759
 760         mcbsp->free = false;
 761         mcbsp->reg_cache = reg_cache;
 762         spin_unlock(&mcbsp->lock);
 763
 764         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
 765                 mcbsp->pdata->ops->request(id);
 766
 767         clk_enable(mcbsp->iclk);
 768         clk_enable(mcbsp->fclk);
 769
 770         /* Do procedure specific to omap34xx arch, if applicable */
 771         omap34xx_mcbsp_request(mcbsp);
 772
 773         /*
 774          * Make sure that transmitter, receiver and sample-rate generator are
 775          * not running before activating IRQs.
 776          */
 777         MCBSP_WRITE(mcbsp, SPCR1, 0);
 778         MCBSP_WRITE(mcbsp, SPCR2, 0);
 779
 780         if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
 781                 /* We need to get IRQs here */
 782                 init_completion(&mcbsp->tx_irq_completion);
 783                 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
 784                                         0, "McBSP", (void *)mcbsp);
 785                 if (err != 0) {
 786                         dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
 787                                         "for McBSP%d\n", mcbsp->tx_irq,
 788                                         mcbsp->id);
 789                         goto err_clk_disable;
 790                 }
 791
 792                 if (mcbsp->rx_irq) {
 793                         init_completion(&mcbsp->rx_irq_completion);
 794                         err = request_irq(mcbsp->rx_irq,
 795                                         omap_mcbsp_rx_irq_handler,
 796                                         0, "McBSP", (void *)mcbsp);
 797                         if (err != 0) {
 798                                 dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
 799                                                 "for McBSP%d\n", mcbsp->rx_irq,
 800                                                 mcbsp->id);
 801                                 goto err_free_irq;
 802                         }
 803                 }
 804         }
 805
 806         return 0;
 807 err_free_irq:
 808         free_irq(mcbsp->tx_irq, (void *)mcbsp);
 809 err_clk_disable:
 810         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 811                 mcbsp->pdata->ops->free(id);
 812
 813         /* Do procedure specific to omap34xx arch, if applicable */
 814         omap34xx_mcbsp_free(mcbsp);
 815
 816         clk_disable(mcbsp->fclk);
 817         clk_disable(mcbsp->iclk);
 818
 819         spin_lock(&mcbsp->lock);
 820         mcbsp->free = true;
 821         mcbsp->reg_cache = NULL;
 822 err_kfree:
 823         spin_unlock(&mcbsp->lock);
 824         kfree(reg_cache);
 825
 826         return err;
 827 }
 828 EXPORT_SYMBOL(omap_mcbsp_request);
 829
 830 void omap_mcbsp_free(unsigned int id)
 831 {
 832         struct omap_mcbsp *mcbsp;
 833         void *reg_cache;
 834
 835         if (!omap_mcbsp_check_valid_id(id)) {
 836                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 837                 return;
 838         }
 839         mcbsp = id_to_mcbsp_ptr(id);
 840
 841         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 842                 mcbsp->pdata->ops->free(id);
 843
 844         /* Do procedure specific to omap34xx arch, if applicable */
 845         omap34xx_mcbsp_free(mcbsp);
 846
 847         clk_disable(mcbsp->fclk);
 848         clk_disable(mcbsp->iclk);
 849
 850         if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
 851                 /* Free IRQs */
 852                 if (mcbsp->rx_irq)
 853                         free_irq(mcbsp->rx_irq, (void *)mcbsp);
 854                 free_irq(mcbsp->tx_irq, (void *)mcbsp);
 855         }
 856
 857         reg_cache = mcbsp->reg_cache;
 858
 859         spin_lock(&mcbsp->lock);
 860         if (mcbsp->free)
 861                 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
 862         else
 863                 mcbsp->free = true;
 864         mcbsp->reg_cache = NULL;
 865         spin_unlock(&mcbsp->lock);
 866
 867         if (reg_cache)
 868                 kfree(reg_cache);
 869 }
 870 EXPORT_SYMBOL(omap_mcbsp_free);
 871
 872 /*
 873  * Here we start the McBSP, by enabling transmitter, receiver or both.
 874  * If no transmitter or receiver is active prior calling, then sample-rate
 875  * generator and frame sync are started.
 876  */
 877 void omap_mcbsp_start(unsigned int id, int tx, int rx)
 878 {
 879         struct omap_mcbsp *mcbsp;
 880         int enable_srg = 0;
 881         u16 w;
 882
 883         if (!omap_mcbsp_check_valid_id(id)) {
 884                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 885                 return;
 886         }
 887         mcbsp = id_to_mcbsp_ptr(id);
 888
 889         if (cpu_is_omap34xx())
 890                 omap_st_start(mcbsp);
 891
 892         mcbsp->rx_word_length = (MCBSP_READ_CACHE(mcbsp, RCR1) >> 5) & 0x7;
 893         mcbsp->tx_word_length = (MCBSP_READ_CACHE(mcbsp, XCR1) >> 5) & 0x7;
 894
 895         /* Only enable SRG, if McBSP is master */
 896         w = MCBSP_READ_CACHE(mcbsp, PCR0);
 897         if (w & (FSXM | FSRM | CLKXM | CLKRM))
 898                 enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
 899                                 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
 900
 901         if (enable_srg) {
 902                 /* Start the sample generator */
 903                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 904                 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
 905         }
 906
 907         /* Enable transmitter and receiver */
 908         tx &= 1;
 909         w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 910         MCBSP_WRITE(mcbsp, SPCR2, w | tx);
 911
 912         rx &= 1;
 913         w = MCBSP_READ_CACHE(mcbsp, SPCR1);
 914         MCBSP_WRITE(mcbsp, SPCR1, w | rx);
 915
 916         /*
 917          * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
 918          * REVISIT: 100us may give enough time for two CLKSRG, however
 919          * due to some unknown PM related, clock gating etc. reason it
 920          * is now at 500us.
 921          */
 922         udelay(500);
 923
 924         if (enable_srg) {
 925                 /* Start frame sync */
 926                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 927                 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
 928         }
 929
 930         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
 931                 /* Release the transmitter and receiver */
 932                 w = MCBSP_READ_CACHE(mcbsp, XCCR);
 933                 w &= ~(tx ? XDISABLE : 0);
 934                 MCBSP_WRITE(mcbsp, XCCR, w);
 935                 w = MCBSP_READ_CACHE(mcbsp, RCCR);
 936                 w &= ~(rx ? RDISABLE : 0);
 937                 MCBSP_WRITE(mcbsp, RCCR, w);
 938         }
 939
 940         /* Dump McBSP Regs */
 941         omap_mcbsp_dump_reg(id);
 942 }
 943 EXPORT_SYMBOL(omap_mcbsp_start);
 944
 945 void omap_mcbsp_stop(unsigned int id, int tx, int rx)
 946 {
 947         struct omap_mcbsp *mcbsp;
 948         int idle;
 949         u16 w;
 950
 951         if (!omap_mcbsp_check_valid_id(id)) {
 952                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 953                 return;
 954         }
 955
 956         mcbsp = id_to_mcbsp_ptr(id);
 957
 958         /* Reset transmitter */
 959         tx &= 1;
 960         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
 961                 w = MCBSP_READ_CACHE(mcbsp, XCCR);
 962                 w |= (tx ? XDISABLE : 0);
 963                 MCBSP_WRITE(mcbsp, XCCR, w);
 964         }
 965         w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 966         MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
 967
 968         /* Reset receiver */
 969         rx &= 1;
 970         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
 971                 w = MCBSP_READ_CACHE(mcbsp, RCCR);
 972                 w |= (rx ? RDISABLE : 0);
 973                 MCBSP_WRITE(mcbsp, RCCR, w);
 974         }
 975         w = MCBSP_READ_CACHE(mcbsp, SPCR1);
 976         MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
 977
 978         idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
 979                         MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
 980
 981         if (idle) {
 982                 /* Reset the sample rate generator */
 983                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 984                 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
 985         }
 986
 987         if (cpu_is_omap34xx())
 988                 omap_st_stop(mcbsp);
 989 }
 990 EXPORT_SYMBOL(omap_mcbsp_stop);
 991
 992 /* polled mcbsp i/o operations */
 993 int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
 994 {
 995         struct omap_mcbsp *mcbsp;
 996
 997         if (!omap_mcbsp_check_valid_id(id)) {
 998                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 999                 return -ENODEV;
1000         }
1001
1002         mcbsp = id_to_mcbsp_ptr(id);
1003
1004         MCBSP_WRITE(mcbsp, DXR1, buf);
1005         /* if frame sync error - clear the error */
1006         if (MCBSP_READ(mcbsp, SPCR2) & XSYNC_ERR) {
1007                 /* clear error */
1008                 MCBSP_WRITE(mcbsp, SPCR2, MCBSP_READ_CACHE(mcbsp, SPCR2));
1009                 /* resend */
1010                 return -1;
1011         } else {
1012                 /* wait for transmit confirmation */
1013                 int attemps = 0;
1014                 while (!(MCBSP_READ(mcbsp, SPCR2) & XRDY)) {
1015                         if (attemps++ > 1000) {
1016                                 MCBSP_WRITE(mcbsp, SPCR2,
1017                                                 MCBSP_READ_CACHE(mcbsp, SPCR2) &
1018                                                 (~XRST));
1019                                 udelay(10);
1020                                 MCBSP_WRITE(mcbsp, SPCR2,
1021                                                 MCBSP_READ_CACHE(mcbsp, SPCR2) |
1022                                                 (XRST));
1023                                 udelay(10);
1024                                 dev_err(mcbsp->dev, "Could not write to"
1025                                         " McBSP%d Register\n", mcbsp->id);
1026                                 return -2;
1027                         }
1028                 }
1029         }
1030
1031         return 0;
1032 }
1033 EXPORT_SYMBOL(omap_mcbsp_pollwrite);
1034
1035 int omap_mcbsp_pollread(unsigned int id, u16 *buf)
1036 {
1037         struct omap_mcbsp *mcbsp;
1038
1039         if (!omap_mcbsp_check_valid_id(id)) {
1040                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1041                 return -ENODEV;
1042         }
1043         mcbsp = id_to_mcbsp_ptr(id);
1044
1045         /* if frame sync error - clear the error */
1046         if (MCBSP_READ(mcbsp, SPCR1) & RSYNC_ERR) {
1047                 /* clear error */
1048                 MCBSP_WRITE(mcbsp, SPCR1, MCBSP_READ_CACHE(mcbsp, SPCR1));
1049                 /* resend */
1050                 return -1;
1051         } else {
1052                 /* wait for recieve confirmation */
1053                 int attemps = 0;
1054                 while (!(MCBSP_READ(mcbsp, SPCR1) & RRDY)) {
1055                         if (attemps++ > 1000) {
1056                                 MCBSP_WRITE(mcbsp, SPCR1,
1057                                                 MCBSP_READ_CACHE(mcbsp, SPCR1) &
1058                                                 (~RRST));
1059                                 udelay(10);
1060                                 MCBSP_WRITE(mcbsp, SPCR1,
1061                                                 MCBSP_READ_CACHE(mcbsp, SPCR1) |
1062                                                 (RRST));
1063                                 udelay(10);
1064                                 dev_err(mcbsp->dev, "Could not read from"
1065                                         " McBSP%d Register\n", mcbsp->id);
1066                                 return -2;
1067                         }
1068                 }
1069         }
1070         *buf = MCBSP_READ(mcbsp, DRR1);
1071
1072         return 0;
1073 }
1074 EXPORT_SYMBOL(omap_mcbsp_pollread);
1075
1076 /*
1077  * IRQ based word transmission.
1078  */
1079 void omap_mcbsp_xmit_word(unsigned int id, u32 word)
1080 {
1081         struct omap_mcbsp *mcbsp;
1082         omap_mcbsp_word_length word_length;
1083
1084         if (!omap_mcbsp_check_valid_id(id)) {
1085                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1086                 return;
1087         }
1088
1089         mcbsp = id_to_mcbsp_ptr(id);
1090         word_length = mcbsp->tx_word_length;
1091
1092         wait_for_completion(&mcbsp->tx_irq_completion);
1093
1094         if (word_length > OMAP_MCBSP_WORD_16)
1095                 MCBSP_WRITE(mcbsp, DXR2, word >> 16);
1096         MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
1097 }
1098 EXPORT_SYMBOL(omap_mcbsp_xmit_word);
1099
1100 u32 omap_mcbsp_recv_word(unsigned int id)
1101 {
1102         struct omap_mcbsp *mcbsp;
1103         u16 word_lsb, word_msb = 0;
1104         omap_mcbsp_word_length word_length;
1105
1106         if (!omap_mcbsp_check_valid_id(id)) {
1107                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1108                 return -ENODEV;
1109         }
1110         mcbsp = id_to_mcbsp_ptr(id);
1111
1112         word_length = mcbsp->rx_word_length;
1113
1114         wait_for_completion(&mcbsp->rx_irq_completion);
1115
1116         if (word_length > OMAP_MCBSP_WORD_16)
1117                 word_msb = MCBSP_READ(mcbsp, DRR2);
1118         word_lsb = MCBSP_READ(mcbsp, DRR1);
1119
1120         return (word_lsb | (word_msb << 16));
1121 }
1122 EXPORT_SYMBOL(omap_mcbsp_recv_word);
1123
1124 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
1125 {
1126         struct omap_mcbsp *mcbsp;
1127         omap_mcbsp_word_length tx_word_length;
1128         omap_mcbsp_word_length rx_word_length;
1129         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
1130
1131         if (!omap_mcbsp_check_valid_id(id)) {
1132                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1133                 return -ENODEV;
1134         }
1135         mcbsp = id_to_mcbsp_ptr(id);
1136         tx_word_length = mcbsp->tx_word_length;
1137         rx_word_length = mcbsp->rx_word_length;
1138
1139         if (tx_word_length != rx_word_length)
1140                 return -EINVAL;
1141
1142         /* First we wait for the transmitter to be ready */
1143         spcr2 = MCBSP_READ(mcbsp, SPCR2);
1144         while (!(spcr2 & XRDY)) {
1145                 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1146                 if (attempts++ > 1000) {
1147                         /* We must reset the transmitter */
1148                         MCBSP_WRITE(mcbsp, SPCR2,
1149                                     MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
1150                         udelay(10);
1151                         MCBSP_WRITE(mcbsp, SPCR2,
1152                                     MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
1153                         udelay(10);
1154                         dev_err(mcbsp->dev, "McBSP%d transmitter not "
1155                                 "ready\n", mcbsp->id);
1156                         return -EAGAIN;
1157                 }
1158         }
1159
1160         /* Now we can push the data */
1161         if (tx_word_length > OMAP_MCBSP_WORD_16)
1162                 MCBSP_WRITE(mcbsp, DXR2, word >> 16);
1163         MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
1164
1165         /* We wait for the receiver to be ready */
1166         spcr1 = MCBSP_READ(mcbsp, SPCR1);
1167         while (!(spcr1 & RRDY)) {
1168                 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1169                 if (attempts++ > 1000) {
1170                         /* We must reset the receiver */
1171                         MCBSP_WRITE(mcbsp, SPCR1,
1172                                     MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
1173                         udelay(10);
1174                         MCBSP_WRITE(mcbsp, SPCR1,
1175                                     MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
1176                         udelay(10);
1177                         dev_err(mcbsp->dev, "McBSP%d receiver not "
1178                                 "ready\n", mcbsp->id);
1179                         return -EAGAIN;
1180                 }
1181         }
1182
1183         /* Receiver is ready, let's read the dummy data */
1184         if (rx_word_length > OMAP_MCBSP_WORD_16)
1185                 word_msb = MCBSP_READ(mcbsp, DRR2);
1186         word_lsb = MCBSP_READ(mcbsp, DRR1);
1187
1188         return 0;
1189 }
1190 EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
1191
1192 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
1193 {
1194         struct omap_mcbsp *mcbsp;
1195         u32 clock_word = 0;
1196         omap_mcbsp_word_length tx_word_length;
1197         omap_mcbsp_word_length rx_word_length;
1198         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
1199
1200         if (!omap_mcbsp_check_valid_id(id)) {
1201                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1202                 return -ENODEV;
1203         }
1204
1205         mcbsp = id_to_mcbsp_ptr(id);
1206
1207         tx_word_length = mcbsp->tx_word_length;
1208         rx_word_length = mcbsp->rx_word_length;
1209
1210         if (tx_word_length != rx_word_length)
1211                 return -EINVAL;
1212
1213         /* First we wait for the transmitter to be ready */
1214         spcr2 = MCBSP_READ(mcbsp, SPCR2);
1215         while (!(spcr2 & XRDY)) {
1216                 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1217                 if (attempts++ > 1000) {
1218                         /* We must reset the transmitter */
1219                         MCBSP_WRITE(mcbsp, SPCR2,
1220                                     MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
1221                         udelay(10);
1222                         MCBSP_WRITE(mcbsp, SPCR2,
1223                                     MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
1224                         udelay(10);
1225                         dev_err(mcbsp->dev, "McBSP%d transmitter not "
1226                                 "ready\n", mcbsp->id);
1227                         return -EAGAIN;
1228                 }
1229         }
1230
1231         /* We first need to enable the bus clock */
1232         if (tx_word_length > OMAP_MCBSP_WORD_16)
1233                 MCBSP_WRITE(mcbsp, DXR2, clock_word >> 16);
1234         MCBSP_WRITE(mcbsp, DXR1, clock_word & 0xffff);
1235
1236         /* We wait for the receiver to be ready */
1237         spcr1 = MCBSP_READ(mcbsp, SPCR1);
1238         while (!(spcr1 & RRDY)) {
1239                 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1240                 if (attempts++ > 1000) {
1241                         /* We must reset the receiver */
1242                         MCBSP_WRITE(mcbsp, SPCR1,
1243                                     MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
1244                         udelay(10);
1245                         MCBSP_WRITE(mcbsp, SPCR1,
1246                                     MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
1247                         udelay(10);
1248                         dev_err(mcbsp->dev, "McBSP%d receiver not "
1249                                 "ready\n", mcbsp->id);
1250                         return -EAGAIN;
1251                 }
1252         }
1253
1254         /* Receiver is ready, there is something for us */
1255         if (rx_word_length > OMAP_MCBSP_WORD_16)
1256                 word_msb = MCBSP_READ(mcbsp, DRR2);
1257         word_lsb = MCBSP_READ(mcbsp, DRR1);
1258
1259         word[0] = (word_lsb | (word_msb << 16));
1260
1261         return 0;
1262 }
1263 EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
1264
1265 /*
1266  * Simple DMA based buffer rx/tx routines.
1267  * Nothing fancy, just a single buffer tx/rx through DMA.
1268  * The DMA resources are released once the transfer is done.
1269  * For anything fancier, you should use your own customized DMA
1270  * routines and callbacks.
1271  */
1272 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
1273                                 unsigned int length)
1274 {
1275         struct omap_mcbsp *mcbsp;
1276         int dma_tx_ch;
1277         int src_port = 0;
1278         int dest_port = 0;
1279         int sync_dev = 0;
1280
1281         if (!omap_mcbsp_check_valid_id(id)) {
1282                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1283                 return -ENODEV;
1284         }
1285         mcbsp = id_to_mcbsp_ptr(id);
1286
1287         if (omap_request_dma(mcbsp->dma_tx_sync, "McBSP TX",
1288                                 omap_mcbsp_tx_dma_callback,
1289                                 mcbsp,
1290                                 &dma_tx_ch)) {
1291                 dev_err(mcbsp->dev, " Unable to request DMA channel for "
1292                                 "McBSP%d TX. Trying IRQ based TX\n",
1293                                 mcbsp->id);
1294                 return -EAGAIN;
1295         }
1296         mcbsp->dma_tx_lch = dma_tx_ch;
1297
1298         dev_err(mcbsp->dev, "McBSP%d TX DMA on channel %d\n", mcbsp->id,
1299                 dma_tx_ch);
1300
1301         init_completion(&mcbsp->tx_dma_completion);
1302
1303         if (cpu_class_is_omap1()) {
1304                 src_port = OMAP_DMA_PORT_TIPB;
1305                 dest_port = OMAP_DMA_PORT_EMIFF;
1306         }
1307         if (cpu_class_is_omap2())
1308                 sync_dev = mcbsp->dma_tx_sync;
1309
1310         omap_set_dma_transfer_params(mcbsp->dma_tx_lch,
1311                                      OMAP_DMA_DATA_TYPE_S16,
1312                                      length >> 1, 1,
1313                                      OMAP_DMA_SYNC_ELEMENT,
1314          sync_dev, 0);
1315
1316         omap_set_dma_dest_params(mcbsp->dma_tx_lch,
1317                                  src_port,
1318                                  OMAP_DMA_AMODE_CONSTANT,
1319                                  mcbsp->phys_base + OMAP_MCBSP_REG_DXR1,
1320                                  0, 0);
1321
1322         omap_set_dma_src_params(mcbsp->dma_tx_lch,
1323                                 dest_port,
1324                                 OMAP_DMA_AMODE_POST_INC,
1325                                 buffer,
1326                                 0, 0);
1327
1328         omap_start_dma(mcbsp->dma_tx_lch);
1329         wait_for_completion(&mcbsp->tx_dma_completion);
1330
1331         return 0;
1332 }
1333 EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
1334
1335 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
1336                                 unsigned int length)
1337 {
1338         struct omap_mcbsp *mcbsp;
1339         int dma_rx_ch;
1340         int src_port = 0;
1341         int dest_port = 0;
1342         int sync_dev = 0;
1343
1344         if (!omap_mcbsp_check_valid_id(id)) {
1345                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1346                 return -ENODEV;
1347         }
1348         mcbsp = id_to_mcbsp_ptr(id);
1349
1350         if (omap_request_dma(mcbsp->dma_rx_sync, "McBSP RX",
1351                                 omap_mcbsp_rx_dma_callback,
1352                                 mcbsp,
1353                                 &dma_rx_ch)) {
1354                 dev_err(mcbsp->dev, "Unable to request DMA channel for "
1355                                 "McBSP%d RX. Trying IRQ based RX\n",
1356                                 mcbsp->id);
1357                 return -EAGAIN;
1358         }
1359         mcbsp->dma_rx_lch = dma_rx_ch;
1360
1361         dev_err(mcbsp->dev, "McBSP%d RX DMA on channel %d\n", mcbsp->id,
1362                 dma_rx_ch);
1363
1364         init_completion(&mcbsp->rx_dma_completion);
1365
1366         if (cpu_class_is_omap1()) {
1367                 src_port = OMAP_DMA_PORT_TIPB;
1368                 dest_port = OMAP_DMA_PORT_EMIFF;
1369         }
1370         if (cpu_class_is_omap2())
1371                 sync_dev = mcbsp->dma_rx_sync;
1372
1373         omap_set_dma_transfer_params(mcbsp->dma_rx_lch,
1374                                         OMAP_DMA_DATA_TYPE_S16,
1375                                         length >> 1, 1,
1376                                         OMAP_DMA_SYNC_ELEMENT,
1377                                         sync_dev, 0);
1378
1379         omap_set_dma_src_params(mcbsp->dma_rx_lch,
1380                                 src_port,
1381                                 OMAP_DMA_AMODE_CONSTANT,
1382                                 mcbsp->phys_base + OMAP_MCBSP_REG_DRR1,
1383                                 0, 0);
1384
1385         omap_set_dma_dest_params(mcbsp->dma_rx_lch,
1386                                         dest_port,
1387                                         OMAP_DMA_AMODE_POST_INC,
1388                                         buffer,
1389                                         0, 0);
1390
1391         omap_start_dma(mcbsp->dma_rx_lch);
1392         wait_for_completion(&mcbsp->rx_dma_completion);
1393
1394         return 0;
1395 }
1396 EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
1397
1398 /*
1399  * SPI wrapper.
1400  * Since SPI setup is much simpler than the generic McBSP one,
1401  * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
1402  * Once this is done, you can call omap_mcbsp_start().
1403  */
1404 void omap_mcbsp_set_spi_mode(unsigned int id,
1405                                 const struct omap_mcbsp_spi_cfg *spi_cfg)
1406 {
1407         struct omap_mcbsp *mcbsp;
1408         struct omap_mcbsp_reg_cfg mcbsp_cfg;
1409
1410         if (!omap_mcbsp_check_valid_id(id)) {
1411                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1412                 return;
1413         }
1414         mcbsp = id_to_mcbsp_ptr(id);
1415
1416         memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
1417
1418         /* SPI has only one frame */
1419         mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
1420         mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
1421
1422         /* Clock stop mode */
1423         if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
1424                 mcbsp_cfg.spcr1 |= (1 << 12);
1425         else
1426                 mcbsp_cfg.spcr1 |= (3 << 11);
1427
1428         /* Set clock parities */
1429         if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1430                 mcbsp_cfg.pcr0 |= CLKRP;
1431         else
1432                 mcbsp_cfg.pcr0 &= ~CLKRP;
1433
1434         if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1435                 mcbsp_cfg.pcr0 &= ~CLKXP;
1436         else
1437                 mcbsp_cfg.pcr0 |= CLKXP;
1438
1439         /* Set SCLKME to 0 and CLKSM to 1 */
1440         mcbsp_cfg.pcr0 &= ~SCLKME;
1441         mcbsp_cfg.srgr2 |= CLKSM;
1442
1443         /* Set FSXP */
1444         if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
1445                 mcbsp_cfg.pcr0 &= ~FSXP;
1446         else
1447                 mcbsp_cfg.pcr0 |= FSXP;
1448
1449         if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
1450                 mcbsp_cfg.pcr0 |= CLKXM;
1451                 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);
1452                 mcbsp_cfg.pcr0 |= FSXM;
1453                 mcbsp_cfg.srgr2 &= ~FSGM;
1454                 mcbsp_cfg.xcr2 |= XDATDLY(1);
1455                 mcbsp_cfg.rcr2 |= RDATDLY(1);
1456         } else {
1457                 mcbsp_cfg.pcr0 &= ~CLKXM;
1458                 mcbsp_cfg.srgr1 |= CLKGDV(1);
1459                 mcbsp_cfg.pcr0 &= ~FSXM;
1460                 mcbsp_cfg.xcr2 &= ~XDATDLY(3);
1461                 mcbsp_cfg.rcr2 &= ~RDATDLY(3);
1462         }
1463
1464         mcbsp_cfg.xcr2 &= ~XPHASE;
1465         mcbsp_cfg.rcr2 &= ~RPHASE;
1466
1467         omap_mcbsp_config(id, &mcbsp_cfg);
1468 }
1469 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
1470
1471 #ifdef CONFIG_ARCH_OMAP3
1472 #define max_thres(m)                    (mcbsp->pdata->buffer_size)
1473 #define valid_threshold(m, val)         ((val) <= max_thres(m))
1474 #define THRESHOLD_PROP_BUILDER(prop)                                    \
1475 static ssize_t prop##_show(struct device *dev,                          \
1476                         struct device_attribute *attr, char *buf)       \
1477 {                                                                       \
1478         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
1479                                                                         \
1480         return sprintf(buf, "%u\n", mcbsp->prop);                       \
1481 }                                                                       \
1482                                                                         \
1483 static ssize_t prop##_store(struct device *dev,                         \
1484                                 struct device_attribute *attr,          \
1485                                 const char *buf, size_t size)           \
1486 {                                                                       \
1487         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
1488         unsigned long val;                                              \
1489         int status;                                                     \
1490                                                                         \
1491         status = strict_strtoul(buf, 0, &val);                          \
1492         if (status)                                                     \
1493                 return status;                                          \
1494                                                                         \
1495         if (!valid_threshold(mcbsp, val))                               \
1496                 return -EDOM;                                           \
1497                                                                         \
1498         mcbsp->prop = val;                                              \
1499         return size;                                                    \
1500 }                                                                       \
1501                                                                         \
1502 static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
1503
1504 THRESHOLD_PROP_BUILDER(max_tx_thres);
1505 THRESHOLD_PROP_BUILDER(max_rx_thres);
1506
1507 static const char *dma_op_modes[] = {
1508         "element", "threshold", "frame",
1509 };
1510
1511 static ssize_t dma_op_mode_show(struct device *dev,
1512                         struct device_attribute *attr, char *buf)
1513 {
1514         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1515         int dma_op_mode, i = 0;
1516         ssize_t len = 0;
1517         const char * const *s;
1518
1519         dma_op_mode = mcbsp->dma_op_mode;
1520
1521         for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
1522                 if (dma_op_mode == i)
1523                         len += sprintf(buf + len, "[%s] ", *s);
1524                 else
1525                         len += sprintf(buf + len, "%s ", *s);
1526         }
1527         len += sprintf(buf + len, "\n");
1528
1529         return len;
1530 }
1531
1532 static ssize_t dma_op_mode_store(struct device *dev,
1533                                 struct device_attribute *attr,
1534                                 const char *buf, size_t size)
1535 {
1536         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1537         const char * const *s;
1538         int i = 0;
1539
1540         for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
1541                 if (sysfs_streq(buf, *s))
1542                         break;
1543
1544         if (i == ARRAY_SIZE(dma_op_modes))
1545                 return -EINVAL;
1546
1547         spin_lock_irq(&mcbsp->lock);
1548         if (!mcbsp->free) {
1549                 size = -EBUSY;
1550                 goto unlock;
1551         }
1552         mcbsp->dma_op_mode = i;
1553
1554 unlock:
1555         spin_unlock_irq(&mcbsp->lock);
1556
1557         return size;
1558 }
1559
1560 static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
1561
1562 static ssize_t st_taps_show(struct device *dev,
1563                             struct device_attribute *attr, char *buf)
1564 {
1565         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1566         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1567         ssize_t status = 0;
1568         int i;
1569
1570         spin_lock_irq(&mcbsp->lock);
1571         for (i = 0; i < st_data->nr_taps; i++)
1572                 status += sprintf(&buf[status], (i ? ", %d" : "%d"),
1573                                   st_data->taps[i]);
1574         if (i)
1575                 status += sprintf(&buf[status], "\n");
1576         spin_unlock_irq(&mcbsp->lock);
1577
1578         return status;
1579 }
1580
1581 static ssize_t st_taps_store(struct device *dev,
1582                              struct device_attribute *attr,
1583                              const char *buf, size_t size)
1584 {
1585         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1586         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1587         int val, tmp, status, i = 0;
1588
1589         spin_lock_irq(&mcbsp->lock);
1590         memset(st_data->taps, 0, sizeof(st_data->taps));
1591         st_data->nr_taps = 0;
1592
1593         do {
1594                 status = sscanf(buf, "%d%n", &val, &tmp);
1595                 if (status < 0 || status == 0) {
1596                         size = -EINVAL;
1597                         goto out;
1598                 }
1599                 if (val < -32768 || val > 32767) {
1600                         size = -EINVAL;
1601                         goto out;
1602                 }
1603                 st_data->taps[i++] = val;
1604                 buf += tmp;
1605                 if (*buf != ',')
1606                         break;
1607                 buf++;
1608         } while (1);
1609
1610         st_data->nr_taps = i;
1611
1612 out:
1613         spin_unlock_irq(&mcbsp->lock);
1614
1615         return size;
1616 }
1617
1618 static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
1619
1620 static const struct attribute *additional_attrs[] = {
1621         &dev_attr_max_tx_thres.attr,
1622         &dev_attr_max_rx_thres.attr,
1623         &dev_attr_dma_op_mode.attr,
1624         NULL,
1625 };
1626
1627 static const struct attribute_group additional_attr_group = {
1628         .attrs = (struct attribute **)additional_attrs,
1629 };
1630
1631 static inline int __devinit omap_additional_add(struct device *dev)
1632 {
1633         return sysfs_create_group(&dev->kobj, &additional_attr_group);
1634 }
1635
1636 static inline void __devexit omap_additional_remove(struct device *dev)
1637 {
1638         sysfs_remove_group(&dev->kobj, &additional_attr_group);
1639 }
1640
1641 static const struct attribute *sidetone_attrs[] = {
1642         &dev_attr_st_taps.attr,
1643         NULL,
1644 };
1645
1646 static const struct attribute_group sidetone_attr_group = {
1647         .attrs = (struct attribute **)sidetone_attrs,
1648 };
1649
1650 static int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
1651 {
1652         struct omap_mcbsp_platform_data *pdata = mcbsp->pdata;
1653         struct omap_mcbsp_st_data *st_data;
1654         int err;
1655
1656         st_data = kzalloc(sizeof(*mcbsp->st_data), GFP_KERNEL);
1657         if (!st_data) {
1658                 err = -ENOMEM;
1659                 goto err1;
1660         }
1661
1662         st_data->io_base_st = ioremap(pdata->phys_base_st, SZ_4K);
1663         if (!st_data->io_base_st) {
1664                 err = -ENOMEM;
1665                 goto err2;
1666         }
1667
1668         err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1669         if (err)
1670                 goto err3;
1671
1672         mcbsp->st_data = st_data;
1673         return 0;
1674
1675 err3:
1676         iounmap(st_data->io_base_st);
1677 err2:
1678         kfree(st_data);
1679 err1:
1680         return err;
1681
1682 }
1683
1684 static void __devexit omap_st_remove(struct omap_mcbsp *mcbsp)
1685 {
1686         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1687
1688         if (st_data) {
1689                 sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1690                 iounmap(st_data->io_base_st);
1691                 kfree(st_data);
1692         }
1693 }
1694
1695 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
1696 {
1697         mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1698         if (cpu_is_omap34xx()) {
1699                 /*
1700                  * Initially configure the maximum thresholds to a safe value.
1701                  * The McBSP FIFO usage with these values should not go under
1702                  * 16 locations.
1703                  * If the whole FIFO without safety buffer is used, than there
1704                  * is a possibility that the DMA will be not able to push the
1705                  * new data on time, causing channel shifts in runtime.
1706                  */
1707                 mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
1708                 mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
1709                 /*
1710                  * REVISIT: Set dmap_op_mode to THRESHOLD as default
1711                  * for mcbsp2 instances.
1712                  */
1713                 if (omap_additional_add(mcbsp->dev))
1714                         dev_warn(mcbsp->dev,
1715                                 "Unable to create additional controls\n");
1716
1717                 if (mcbsp->id == 2 || mcbsp->id == 3)
1718                         if (omap_st_add(mcbsp))
1719                                 dev_warn(mcbsp->dev,
1720                                  "Unable to create sidetone controls\n");
1721
1722         } else {
1723                 mcbsp->max_tx_thres = -EINVAL;
1724                 mcbsp->max_rx_thres = -EINVAL;
1725         }
1726 }
1727
1728 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
1729 {
1730         if (cpu_is_omap34xx()) {
1731                 omap_additional_remove(mcbsp->dev);
1732
1733                 if (mcbsp->id == 2 || mcbsp->id == 3)
1734                         omap_st_remove(mcbsp);
1735         }
1736 }
1737 #else
1738 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
1739 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
1740 #endif /* CONFIG_ARCH_OMAP3 */
1741
1742 /*
1743  * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
1744  * 730 has only 2 McBSP, and both of them are MPU peripherals.
1745  */
1746 static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1747 {
1748         struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
1749         struct omap_mcbsp *mcbsp;
1750         int id = pdev->id - 1;
1751         int ret = 0;
1752
1753         if (!pdata) {
1754                 dev_err(&pdev->dev, "McBSP device initialized without"
1755                                 "platform data\n");
1756                 ret = -EINVAL;
1757                 goto exit;
1758         }
1759
1760         dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
1761
1762         if (id >= omap_mcbsp_count) {
1763                 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
1764                 ret = -EINVAL;
1765                 goto exit;
1766         }
1767
1768         mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
1769         if (!mcbsp) {
1770                 ret = -ENOMEM;
1771                 goto exit;
1772         }
1773
1774         spin_lock_init(&mcbsp->lock);
1775         mcbsp->id = id + 1;
1776         mcbsp->free = true;
1777         mcbsp->dma_tx_lch = -1;
1778         mcbsp->dma_rx_lch = -1;
1779
1780         mcbsp->phys_base = pdata->phys_base;
1781         mcbsp->io_base = ioremap(pdata->phys_base, SZ_4K);
1782         if (!mcbsp->io_base) {
1783                 ret = -ENOMEM;
1784                 goto err_ioremap;
1785         }
1786
1787         /* Default I/O is IRQ based */
1788         mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
1789         mcbsp->tx_irq = pdata->tx_irq;
1790         mcbsp->rx_irq = pdata->rx_irq;
1791         mcbsp->dma_rx_sync = pdata->dma_rx_sync;
1792         mcbsp->dma_tx_sync = pdata->dma_tx_sync;
1793
1794         mcbsp->iclk = clk_get(&pdev->dev, "ick");
1795         if (IS_ERR(mcbsp->iclk)) {
1796                 ret = PTR_ERR(mcbsp->iclk);
1797                 dev_err(&pdev->dev, "unable to get ick: %d\n", ret);
1798                 goto err_iclk;
1799         }
1800
1801         mcbsp->fclk = clk_get(&pdev->dev, "fck");
1802         if (IS_ERR(mcbsp->fclk)) {
1803                 ret = PTR_ERR(mcbsp->fclk);
1804                 dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
1805                 goto err_fclk;
1806         }
1807
1808         mcbsp->pdata = pdata;
1809         mcbsp->dev = &pdev->dev;
1810         mcbsp_ptr[id] = mcbsp;
1811         platform_set_drvdata(pdev, mcbsp);
1812
1813         /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
1814         omap34xx_device_init(mcbsp);
1815
1816         return 0;
1817
1818 err_fclk:
1819         clk_put(mcbsp->iclk);
1820 err_iclk:
1821         iounmap(mcbsp->io_base);
1822 err_ioremap:
1823         kfree(mcbsp);
1824 exit:
1825         return ret;
1826 }
1827
1828 static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
1829 {
1830         struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
1831
1832         platform_set_drvdata(pdev, NULL);
1833         if (mcbsp) {
1834
1835                 if (mcbsp->pdata && mcbsp->pdata->ops &&
1836                                 mcbsp->pdata->ops->free)
1837                         mcbsp->pdata->ops->free(mcbsp->id);
1838
1839                 omap34xx_device_exit(mcbsp);
1840
1841                 clk_put(mcbsp->fclk);
1842                 clk_put(mcbsp->iclk);
1843
1844                 iounmap(mcbsp->io_base);
1845                 kfree(mcbsp);
1846         }
1847
1848         return 0;
1849 }
1850
1851 static struct platform_driver omap_mcbsp_driver = {
1852         .probe          = omap_mcbsp_probe,
1853         .remove         = __devexit_p(omap_mcbsp_remove),
1854         .driver         = {
1855                 .name   = "omap-mcbsp",
1856         },
1857 };
1858
1859 int __init omap_mcbsp_init(void)
1860 {
1861         /* Register the McBSP driver */
1862         return platform_driver_register(&omap_mcbsp_driver);
1863 }