arch/arm/plat-omap/mcbsp.c

   1 /*
   2  * linux/arch/arm/plat-omap/mcbsp.c
   3  *
   4  * Copyright (C) 2004 Nokia Corporation
   5  * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
   6  *
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * Multichannel mode not supported.
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/device.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/wait.h>
  20 #include <linux/completion.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/err.h>
  23 #include <linux/clk.h>
  24 #include <linux/delay.h>
  25 #include <linux/io.h>
  26 #include <linux/slab.h>
  27
  28 #include <plat/dma.h>
  29 #include <plat/mcbsp.h>
  30
  31 #include "../mach-omap2/cm-regbits-34xx.h"
  32
  33 struct omap_mcbsp **mcbsp_ptr;
  34 int omap_mcbsp_count, omap_mcbsp_cache_size;
  35
  36 void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
  37 {
  38         if (cpu_class_is_omap1()) {
  39                 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)] = (u16)val;
  40                 __raw_writew((u16)val, mcbsp->io_base + reg);
  41         } else if (cpu_is_omap2420()) {
  42                 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)] = (u16)val;
  43                 __raw_writew((u16)val, mcbsp->io_base + reg);
  44         } else {
  45                 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)] = val;
  46                 __raw_writel(val, mcbsp->io_base + reg);
  47         }
  48 }
  49
  50 int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
  51 {
  52         if (cpu_class_is_omap1()) {
  53                 return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
  54                                 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)];
  55         } else if (cpu_is_omap2420()) {
  56                 return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
  57                                 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)];
  58         } else {
  59                 return !from_cache ? __raw_readl(mcbsp->io_base + reg) :
  60                                 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)];
  61         }
  62 }
  63
  64 #ifdef CONFIG_ARCH_OMAP3
  65 void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
  66 {
  67         __raw_writel(val, mcbsp->st_data->io_base_st + reg);
  68 }
  69
  70 int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
  71 {
  72         return __raw_readl(mcbsp->st_data->io_base_st + reg);
  73 }
  74 #endif
  75
  76 #define MCBSP_READ(mcbsp, reg) \
  77                 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
  78 #define MCBSP_WRITE(mcbsp, reg, val) \
  79                 omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
  80 #define MCBSP_READ_CACHE(mcbsp, reg) \
  81                 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
  82
  83 #define omap_mcbsp_check_valid_id(id)   (id < omap_mcbsp_count)
  84 #define id_to_mcbsp_ptr(id)             mcbsp_ptr[id];
  85
  86 #define MCBSP_ST_READ(mcbsp, reg) \
  87                         omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
  88 #define MCBSP_ST_WRITE(mcbsp, reg, val) \
  89                         omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
  90
  91 static void omap_mcbsp_dump_reg(u8 id)
  92 {
  93         struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
  94
  95         dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
  96         dev_dbg(mcbsp->dev, "DRR2:  0x%04x\n",
  97                         MCBSP_READ(mcbsp, DRR2));
  98         dev_dbg(mcbsp->dev, "DRR1:  0x%04x\n",
  99                         MCBSP_READ(mcbsp, DRR1));
 100         dev_dbg(mcbsp->dev, "DXR2:  0x%04x\n",
 101                         MCBSP_READ(mcbsp, DXR2));
 102         dev_dbg(mcbsp->dev, "DXR1:  0x%04x\n",
 103                         MCBSP_READ(mcbsp, DXR1));
 104         dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
 105                         MCBSP_READ(mcbsp, SPCR2));
 106         dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
 107                         MCBSP_READ(mcbsp, SPCR1));
 108         dev_dbg(mcbsp->dev, "RCR2:  0x%04x\n",
 109                         MCBSP_READ(mcbsp, RCR2));
 110         dev_dbg(mcbsp->dev, "RCR1:  0x%04x\n",
 111                         MCBSP_READ(mcbsp, RCR1));
 112         dev_dbg(mcbsp->dev, "XCR2:  0x%04x\n",
 113                         MCBSP_READ(mcbsp, XCR2));
 114         dev_dbg(mcbsp->dev, "XCR1:  0x%04x\n",
 115                         MCBSP_READ(mcbsp, XCR1));
 116         dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
 117                         MCBSP_READ(mcbsp, SRGR2));
 118         dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
 119                         MCBSP_READ(mcbsp, SRGR1));
 120         dev_dbg(mcbsp->dev, "PCR0:  0x%04x\n",
 121                         MCBSP_READ(mcbsp, PCR0));
 122         dev_dbg(mcbsp->dev, "***********************\n");
 123 }
 124
 125 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
 126 {
 127         struct omap_mcbsp *mcbsp_tx = dev_id;
 128         u16 irqst_spcr2;
 129
 130         irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2);
 131         dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
 132
 133         if (irqst_spcr2 & XSYNC_ERR) {
 134                 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
 135                         irqst_spcr2);
 136                 /* Writing zero to XSYNC_ERR clears the IRQ */
 137                 MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2));
 138         } else {
 139                 complete(&mcbsp_tx->tx_irq_completion);
 140         }
 141
 142         return IRQ_HANDLED;
 143 }
 144
 145 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
 146 {
 147         struct omap_mcbsp *mcbsp_rx = dev_id;
 148         u16 irqst_spcr1;
 149
 150         irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1);
 151         dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
 152
 153         if (irqst_spcr1 & RSYNC_ERR) {
 154                 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
 155                         irqst_spcr1);
 156                 /* Writing zero to RSYNC_ERR clears the IRQ */
 157                 MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
 158         } else {
 159                 complete(&mcbsp_rx->tx_irq_completion);
 160         }
 161
 162         return IRQ_HANDLED;
 163 }
 164
 165 static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
 166 {
 167         struct omap_mcbsp *mcbsp_dma_tx = data;
 168
 169         dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
 170                 MCBSP_READ(mcbsp_dma_tx, SPCR2));
 171
 172         /* We can free the channels */
 173         omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
 174         mcbsp_dma_tx->dma_tx_lch = -1;
 175
 176         complete(&mcbsp_dma_tx->tx_dma_completion);
 177 }
 178
 179 static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
 180 {
 181         struct omap_mcbsp *mcbsp_dma_rx = data;
 182
 183         dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
 184                 MCBSP_READ(mcbsp_dma_rx, SPCR2));
 185
 186         /* We can free the channels */
 187         omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
 188         mcbsp_dma_rx->dma_rx_lch = -1;
 189
 190         complete(&mcbsp_dma_rx->rx_dma_completion);
 191 }
 192
 193 /*
 194  * omap_mcbsp_config simply write a config to the
 195  * appropriate McBSP.
 196  * You either call this function or set the McBSP registers
 197  * by yourself before calling omap_mcbsp_start().
 198  */
 199 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
 200 {
 201         struct omap_mcbsp *mcbsp;
 202
 203         if (!omap_mcbsp_check_valid_id(id)) {
 204                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 205                 return;
 206         }
 207         mcbsp = id_to_mcbsp_ptr(id);
 208
 209         dev_dbg(mcbsp->dev, "Configuring McBSP%d  phys_base: 0x%08lx\n",
 210                         mcbsp->id, mcbsp->phys_base);
 211
 212         /* We write the given config */
 213         MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
 214         MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
 215         MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
 216         MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
 217         MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
 218         MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
 219         MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
 220         MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
 221         MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
 222         MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
 223         MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
 224         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
 225                 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
 226                 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
 227         }
 228 }
 229 EXPORT_SYMBOL(omap_mcbsp_config);
 230
 231 #ifdef CONFIG_ARCH_OMAP3
 232 static void omap_st_on(struct omap_mcbsp *mcbsp)
 233 {
 234         unsigned int w;
 235
 236         /*
 237          * Sidetone uses McBSP ICLK - which must not idle when sidetones
 238          * are enabled or sidetones start sounding ugly.
 239          */
 240         w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
 241         w &= ~(1 << (mcbsp->id - 2));
 242         cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
 243
 244         /* Enable McBSP Sidetone */
 245         w = MCBSP_READ(mcbsp, SSELCR);
 246         MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
 247
 248         w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
 249         MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE));
 250
 251         /* Enable Sidetone from Sidetone Core */
 252         w = MCBSP_ST_READ(mcbsp, SSELCR);
 253         MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
 254 }
 255
 256 static void omap_st_off(struct omap_mcbsp *mcbsp)
 257 {
 258         unsigned int w;
 259
 260         w = MCBSP_ST_READ(mcbsp, SSELCR);
 261         MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
 262
 263         w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
 264         MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w | ST_AUTOIDLE);
 265
 266         w = MCBSP_READ(mcbsp, SSELCR);
 267         MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
 268
 269         w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
 270         w |= 1 << (mcbsp->id - 2);
 271         cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
 272 }
 273
 274 static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
 275 {
 276         u16 val, i;
 277
 278         val = MCBSP_ST_READ(mcbsp, SYSCONFIG);
 279         MCBSP_ST_WRITE(mcbsp, SYSCONFIG, val & ~(ST_AUTOIDLE));
 280
 281         val = MCBSP_ST_READ(mcbsp, SSELCR);
 282
 283         if (val & ST_COEFFWREN)
 284                 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
 285
 286         MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN);
 287
 288         for (i = 0; i < 128; i++)
 289                 MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]);
 290
 291         i = 0;
 292
 293         val = MCBSP_ST_READ(mcbsp, SSELCR);
 294         while (!(val & ST_COEFFWRDONE) && (++i < 1000))
 295                 val = MCBSP_ST_READ(mcbsp, SSELCR);
 296
 297         MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
 298
 299         if (i == 1000)
 300                 dev_err(mcbsp->dev, "McBSP FIR load error!\n");
 301 }
 302
 303 static void omap_st_chgain(struct omap_mcbsp *mcbsp)
 304 {
 305         u16 w;
 306         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 307
 308         w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
 309         MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE));
 310
 311         w = MCBSP_ST_READ(mcbsp, SSELCR);
 312
 313         MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \
 314                       ST_CH1GAIN(st_data->ch1gain));
 315 }
 316
 317 int omap_st_set_chgain(unsigned int id, int channel, s16 chgain)
 318 {
 319         struct omap_mcbsp *mcbsp;
 320         struct omap_mcbsp_st_data *st_data;
 321         int ret = 0;
 322
 323         if (!omap_mcbsp_check_valid_id(id)) {
 324                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 325                 return -ENODEV;
 326         }
 327
 328         mcbsp = id_to_mcbsp_ptr(id);
 329         st_data = mcbsp->st_data;
 330
 331         if (!st_data)
 332                 return -ENOENT;
 333
 334         spin_lock_irq(&mcbsp->lock);
 335         if (channel == 0)
 336                 st_data->ch0gain = chgain;
 337         else if (channel == 1)
 338                 st_data->ch1gain = chgain;
 339         else
 340                 ret = -EINVAL;
 341
 342         if (st_data->enabled)
 343                 omap_st_chgain(mcbsp);
 344         spin_unlock_irq(&mcbsp->lock);
 345
 346         return ret;
 347 }
 348 EXPORT_SYMBOL(omap_st_set_chgain);
 349
 350 int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain)
 351 {
 352         struct omap_mcbsp *mcbsp;
 353         struct omap_mcbsp_st_data *st_data;
 354         int ret = 0;
 355
 356         if (!omap_mcbsp_check_valid_id(id)) {
 357                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 358                 return -ENODEV;
 359         }
 360
 361         mcbsp = id_to_mcbsp_ptr(id);
 362         st_data = mcbsp->st_data;
 363
 364         if (!st_data)
 365                 return -ENOENT;
 366
 367         spin_lock_irq(&mcbsp->lock);
 368         if (channel == 0)
 369                 *chgain = st_data->ch0gain;
 370         else if (channel == 1)
 371                 *chgain = st_data->ch1gain;
 372         else
 373                 ret = -EINVAL;
 374         spin_unlock_irq(&mcbsp->lock);
 375
 376         return ret;
 377 }
 378 EXPORT_SYMBOL(omap_st_get_chgain);
 379
 380 static int omap_st_start(struct omap_mcbsp *mcbsp)
 381 {
 382         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 383
 384         if (st_data && st_data->enabled && !st_data->running) {
 385                 omap_st_fir_write(mcbsp, st_data->taps);
 386                 omap_st_chgain(mcbsp);
 387
 388                 if (!mcbsp->free) {
 389                         omap_st_on(mcbsp);
 390                         st_data->running = 1;
 391                 }
 392         }
 393
 394         return 0;
 395 }
 396
 397 int omap_st_enable(unsigned int id)
 398 {
 399         struct omap_mcbsp *mcbsp;
 400         struct omap_mcbsp_st_data *st_data;
 401
 402         if (!omap_mcbsp_check_valid_id(id)) {
 403                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 404                 return -ENODEV;
 405         }
 406
 407         mcbsp = id_to_mcbsp_ptr(id);
 408         st_data = mcbsp->st_data;
 409
 410         if (!st_data)
 411                 return -ENODEV;
 412
 413         spin_lock_irq(&mcbsp->lock);
 414         st_data->enabled = 1;
 415         omap_st_start(mcbsp);
 416         spin_unlock_irq(&mcbsp->lock);
 417
 418         return 0;
 419 }
 420 EXPORT_SYMBOL(omap_st_enable);
 421
 422 static int omap_st_stop(struct omap_mcbsp *mcbsp)
 423 {
 424         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 425
 426         if (st_data && st_data->running) {
 427                 if (!mcbsp->free) {
 428                         omap_st_off(mcbsp);
 429                         st_data->running = 0;
 430                 }
 431         }
 432
 433         return 0;
 434 }
 435
 436 int omap_st_disable(unsigned int id)
 437 {
 438         struct omap_mcbsp *mcbsp;
 439         struct omap_mcbsp_st_data *st_data;
 440         int ret = 0;
 441
 442         if (!omap_mcbsp_check_valid_id(id)) {
 443                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 444                 return -ENODEV;
 445         }
 446
 447         mcbsp = id_to_mcbsp_ptr(id);
 448         st_data = mcbsp->st_data;
 449
 450         if (!st_data)
 451                 return -ENODEV;
 452
 453         spin_lock_irq(&mcbsp->lock);
 454         omap_st_stop(mcbsp);
 455         st_data->enabled = 0;
 456         spin_unlock_irq(&mcbsp->lock);
 457
 458         return ret;
 459 }
 460 EXPORT_SYMBOL(omap_st_disable);
 461
 462 int omap_st_is_enabled(unsigned int id)
 463 {
 464         struct omap_mcbsp *mcbsp;
 465         struct omap_mcbsp_st_data *st_data;
 466
 467         if (!omap_mcbsp_check_valid_id(id)) {
 468                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 469                 return -ENODEV;
 470         }
 471
 472         mcbsp = id_to_mcbsp_ptr(id);
 473         st_data = mcbsp->st_data;
 474
 475         if (!st_data)
 476                 return -ENODEV;
 477
 478
 479         return st_data->enabled;
 480 }
 481 EXPORT_SYMBOL(omap_st_is_enabled);
 482
 483 /*
 484  * omap_mcbsp_set_tx_threshold configures how to deal
 485  * with transmit threshold. the threshold value and handler can be
 486  * configure in here.
 487  */
 488 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
 489 {
 490         struct omap_mcbsp *mcbsp;
 491
 492         if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
 493                 return;
 494
 495         if (!omap_mcbsp_check_valid_id(id)) {
 496                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 497                 return;
 498         }
 499         mcbsp = id_to_mcbsp_ptr(id);
 500
 501         MCBSP_WRITE(mcbsp, THRSH2, threshold);
 502 }
 503 EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
 504
 505 /*
 506  * omap_mcbsp_set_rx_threshold configures how to deal
 507  * with receive threshold. the threshold value and handler can be
 508  * configure in here.
 509  */
 510 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
 511 {
 512         struct omap_mcbsp *mcbsp;
 513
 514         if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
 515                 return;
 516
 517         if (!omap_mcbsp_check_valid_id(id)) {
 518                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 519                 return;
 520         }
 521         mcbsp = id_to_mcbsp_ptr(id);
 522
 523         MCBSP_WRITE(mcbsp, THRSH1, threshold);
 524 }
 525 EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
 526
 527 /*
 528  * omap_mcbsp_get_max_tx_thres just return the current configured
 529  * maximum threshold for transmission
 530  */
 531 u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
 532 {
 533         struct omap_mcbsp *mcbsp;
 534
 535         if (!omap_mcbsp_check_valid_id(id)) {
 536                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 537                 return -ENODEV;
 538         }
 539         mcbsp = id_to_mcbsp_ptr(id);
 540
 541         return mcbsp->max_tx_thres;
 542 }
 543 EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
 544
 545 /*
 546  * omap_mcbsp_get_max_rx_thres just return the current configured
 547  * maximum threshold for reception
 548  */
 549 u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
 550 {
 551         struct omap_mcbsp *mcbsp;
 552
 553         if (!omap_mcbsp_check_valid_id(id)) {
 554                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 555                 return -ENODEV;
 556         }
 557         mcbsp = id_to_mcbsp_ptr(id);
 558
 559         return mcbsp->max_rx_thres;
 560 }
 561 EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
 562
 563 #define MCBSP2_FIFO_SIZE        0x500 /* 1024 + 256 locations */
 564 #define MCBSP1345_FIFO_SIZE     0x80  /* 128 locations */
 565 /*
 566  * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
 567  */
 568 u16 omap_mcbsp_get_tx_delay(unsigned int id)
 569 {
 570         struct omap_mcbsp *mcbsp;
 571         u16 buffstat;
 572
 573         if (!omap_mcbsp_check_valid_id(id)) {
 574                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 575                 return -ENODEV;
 576         }
 577         mcbsp = id_to_mcbsp_ptr(id);
 578
 579         /* Returns the number of free locations in the buffer */
 580         buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
 581
 582         /* Number of slots are different in McBSP ports */
 583         if (mcbsp->id == 2)
 584                 return MCBSP2_FIFO_SIZE - buffstat;
 585         else
 586                 return MCBSP1345_FIFO_SIZE - buffstat;
 587 }
 588 EXPORT_SYMBOL(omap_mcbsp_get_tx_delay);
 589
 590 /*
 591  * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
 592  * to reach the threshold value (when the DMA will be triggered to read it)
 593  */
 594 u16 omap_mcbsp_get_rx_delay(unsigned int id)
 595 {
 596         struct omap_mcbsp *mcbsp;
 597         u16 buffstat, threshold;
 598
 599         if (!omap_mcbsp_check_valid_id(id)) {
 600                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 601                 return -ENODEV;
 602         }
 603         mcbsp = id_to_mcbsp_ptr(id);
 604
 605         /* Returns the number of used locations in the buffer */
 606         buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
 607         /* RX threshold */
 608         threshold = MCBSP_READ(mcbsp, THRSH1);
 609
 610         /* Return the number of location till we reach the threshold limit */
 611         if (threshold <= buffstat)
 612                 return 0;
 613         else
 614                 return threshold - buffstat;
 615 }
 616 EXPORT_SYMBOL(omap_mcbsp_get_rx_delay);
 617
 618 /*
 619  * omap_mcbsp_get_dma_op_mode just return the current configured
 620  * operating mode for the mcbsp channel
 621  */
 622 int omap_mcbsp_get_dma_op_mode(unsigned int id)
 623 {
 624         struct omap_mcbsp *mcbsp;
 625         int dma_op_mode;
 626
 627         if (!omap_mcbsp_check_valid_id(id)) {
 628                 printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1);
 629                 return -ENODEV;
 630         }
 631         mcbsp = id_to_mcbsp_ptr(id);
 632
 633         dma_op_mode = mcbsp->dma_op_mode;
 634
 635         return dma_op_mode;
 636 }
 637 EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
 638
 639 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
 640 {
 641         /*
 642          * Enable wakup behavior, smart idle and all wakeups
 643          * REVISIT: some wakeups may be unnecessary
 644          */
 645         if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
 646                 u16 syscon;
 647
 648                 syscon = MCBSP_READ(mcbsp, SYSCON);
 649                 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
 650
 651                 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
 652                         syscon |= (ENAWAKEUP | SIDLEMODE(0x02) |
 653                                         CLOCKACTIVITY(0x02));
 654                         MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
 655                 } else {
 656                         syscon |= SIDLEMODE(0x01);
 657                 }
 658
 659                 MCBSP_WRITE(mcbsp, SYSCON, syscon);
 660         }
 661 }
 662
 663 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
 664 {
 665         /*
 666          * Disable wakup behavior, smart idle and all wakeups
 667          */
 668         if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
 669                 u16 syscon;
 670
 671                 syscon = MCBSP_READ(mcbsp, SYSCON);
 672                 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
 673                 /*
 674                  * HW bug workaround - If no_idle mode is taken, we need to
 675                  * go to smart_idle before going to always_idle, or the
 676                  * device will not hit retention anymore.
 677                  */
 678                 syscon |= SIDLEMODE(0x02);
 679                 MCBSP_WRITE(mcbsp, SYSCON, syscon);
 680
 681                 syscon &= ~(SIDLEMODE(0x03));
 682                 MCBSP_WRITE(mcbsp, SYSCON, syscon);
 683
 684                 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
 685         }
 686 }
 687 #else
 688 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {}
 689 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {}
 690 static inline void omap_st_start(struct omap_mcbsp *mcbsp) {}
 691 static inline void omap_st_stop(struct omap_mcbsp *mcbsp) {}
 692 #endif
 693
 694 /*
 695  * We can choose between IRQ based or polled IO.
 696  * This needs to be called before omap_mcbsp_request().
 697  */
 698 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
 699 {
 700         struct omap_mcbsp *mcbsp;
 701
 702         if (!omap_mcbsp_check_valid_id(id)) {
 703                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 704                 return -ENODEV;
 705         }
 706         mcbsp = id_to_mcbsp_ptr(id);
 707
 708         spin_lock(&mcbsp->lock);
 709
 710         if (!mcbsp->free) {
 711                 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
 712                         mcbsp->id);
 713                 spin_unlock(&mcbsp->lock);
 714                 return -EINVAL;
 715         }
 716
 717         mcbsp->io_type = io_type;
 718
 719         spin_unlock(&mcbsp->lock);
 720
 721         return 0;
 722 }
 723 EXPORT_SYMBOL(omap_mcbsp_set_io_type);
 724
 725 int omap_mcbsp_request(unsigned int id)
 726 {
 727         struct omap_mcbsp *mcbsp;
 728         void *reg_cache;
 729         int err;
 730
 731         if (!omap_mcbsp_check_valid_id(id)) {
 732                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 733                 return -ENODEV;
 734         }
 735         mcbsp = id_to_mcbsp_ptr(id);
 736
 737         reg_cache = kzalloc(omap_mcbsp_cache_size, GFP_KERNEL);
 738         if (!reg_cache) {
 739                 return -ENOMEM;
 740         }
 741
 742         spin_lock(&mcbsp->lock);
 743         if (!mcbsp->free) {
 744                 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
 745                         mcbsp->id);
 746                 err = -EBUSY;
 747                 goto err_kfree;
 748         }
 749
 750         mcbsp->free = 0;
 751         mcbsp->reg_cache = reg_cache;
 752         spin_unlock(&mcbsp->lock);
 753
 754         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
 755                 mcbsp->pdata->ops->request(id);
 756
 757         clk_enable(mcbsp->iclk);
 758         clk_enable(mcbsp->fclk);
 759
 760         /* Do procedure specific to omap34xx arch, if applicable */
 761         omap34xx_mcbsp_request(mcbsp);
 762
 763         /*
 764          * Make sure that transmitter, receiver and sample-rate generator are
 765          * not running before activating IRQs.
 766          */
 767         MCBSP_WRITE(mcbsp, SPCR1, 0);
 768         MCBSP_WRITE(mcbsp, SPCR2, 0);
 769
 770         if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
 771                 /* We need to get IRQs here */
 772                 init_completion(&mcbsp->tx_irq_completion);
 773                 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
 774                                         0, "McBSP", (void *)mcbsp);
 775                 if (err != 0) {
 776                         dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
 777                                         "for McBSP%d\n", mcbsp->tx_irq,
 778                                         mcbsp->id);
 779                         goto err_clk_disable;
 780                 }
 781
 782                 if (mcbsp->rx_irq) {
 783                         init_completion(&mcbsp->rx_irq_completion);
 784                         err = request_irq(mcbsp->rx_irq,
 785                                         omap_mcbsp_rx_irq_handler,
 786                                         0, "McBSP", (void *)mcbsp);
 787                         if (err != 0) {
 788                                 dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
 789                                                 "for McBSP%d\n", mcbsp->rx_irq,
 790                                                 mcbsp->id);
 791                                 goto err_free_irq;
 792                         }
 793                 }
 794         }
 795
 796         return 0;
 797 err_free_irq:
 798         free_irq(mcbsp->tx_irq, (void *)mcbsp);
 799 err_clk_disable:
 800         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 801                 mcbsp->pdata->ops->free(id);
 802
 803         /* Do procedure specific to omap34xx arch, if applicable */
 804         omap34xx_mcbsp_free(mcbsp);
 805
 806         clk_disable(mcbsp->fclk);
 807         clk_disable(mcbsp->iclk);
 808
 809         spin_lock(&mcbsp->lock);
 810         mcbsp->free = 1;
 811         mcbsp->reg_cache = NULL;
 812 err_kfree:
 813         spin_unlock(&mcbsp->lock);
 814         kfree(reg_cache);
 815
 816         return err;
 817 }
 818 EXPORT_SYMBOL(omap_mcbsp_request);
 819
 820 void omap_mcbsp_free(unsigned int id)
 821 {
 822         struct omap_mcbsp *mcbsp;
 823         void *reg_cache;
 824
 825         if (!omap_mcbsp_check_valid_id(id)) {
 826                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 827                 return;
 828         }
 829         mcbsp = id_to_mcbsp_ptr(id);
 830
 831         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 832                 mcbsp->pdata->ops->free(id);
 833
 834         /* Do procedure specific to omap34xx arch, if applicable */
 835         omap34xx_mcbsp_free(mcbsp);
 836
 837         clk_disable(mcbsp->fclk);
 838         clk_disable(mcbsp->iclk);
 839
 840         if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
 841                 /* Free IRQs */
 842                 if (mcbsp->rx_irq)
 843                         free_irq(mcbsp->rx_irq, (void *)mcbsp);
 844                 free_irq(mcbsp->tx_irq, (void *)mcbsp);
 845         }
 846
 847         reg_cache = mcbsp->reg_cache;
 848
 849         spin_lock(&mcbsp->lock);
 850         if (mcbsp->free)
 851                 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
 852         else
 853                 mcbsp->free = 1;
 854         mcbsp->reg_cache = NULL;
 855         spin_unlock(&mcbsp->lock);
 856
 857         if (reg_cache)
 858                 kfree(reg_cache);
 859 }
 860 EXPORT_SYMBOL(omap_mcbsp_free);
 861
 862 /*
 863  * Here we start the McBSP, by enabling transmitter, receiver or both.
 864  * If no transmitter or receiver is active prior calling, then sample-rate
 865  * generator and frame sync are started.
 866  */
 867 void omap_mcbsp_start(unsigned int id, int tx, int rx)
 868 {
 869         struct omap_mcbsp *mcbsp;
 870         int idle;
 871         u16 w;
 872
 873         if (!omap_mcbsp_check_valid_id(id)) {
 874                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 875                 return;
 876         }
 877         mcbsp = id_to_mcbsp_ptr(id);
 878
 879         if (cpu_is_omap34xx())
 880                 omap_st_start(mcbsp);
 881
 882         mcbsp->rx_word_length = (MCBSP_READ_CACHE(mcbsp, RCR1) >> 5) & 0x7;
 883         mcbsp->tx_word_length = (MCBSP_READ_CACHE(mcbsp, XCR1) >> 5) & 0x7;
 884
 885         idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
 886                         MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
 887
 888         if (idle) {
 889                 /* Start the sample generator */
 890                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 891                 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
 892         }
 893
 894         /* Enable transmitter and receiver */
 895         tx &= 1;
 896         w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 897         MCBSP_WRITE(mcbsp, SPCR2, w | tx);
 898
 899         rx &= 1;
 900         w = MCBSP_READ_CACHE(mcbsp, SPCR1);
 901         MCBSP_WRITE(mcbsp, SPCR1, w | rx);
 902
 903         /*
 904          * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
 905          * REVISIT: 100us may give enough time for two CLKSRG, however
 906          * due to some unknown PM related, clock gating etc. reason it
 907          * is now at 500us.
 908          */
 909         udelay(500);
 910
 911         if (idle) {
 912                 /* Start frame sync */
 913                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 914                 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
 915         }
 916
 917         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
 918                 /* Release the transmitter and receiver */
 919                 w = MCBSP_READ_CACHE(mcbsp, XCCR);
 920                 w &= ~(tx ? XDISABLE : 0);
 921                 MCBSP_WRITE(mcbsp, XCCR, w);
 922                 w = MCBSP_READ_CACHE(mcbsp, RCCR);
 923                 w &= ~(rx ? RDISABLE : 0);
 924                 MCBSP_WRITE(mcbsp, RCCR, w);
 925         }
 926
 927         /* Dump McBSP Regs */
 928         omap_mcbsp_dump_reg(id);
 929 }
 930 EXPORT_SYMBOL(omap_mcbsp_start);
 931
 932 void omap_mcbsp_stop(unsigned int id, int tx, int rx)
 933 {
 934         struct omap_mcbsp *mcbsp;
 935         int idle;
 936         u16 w;
 937
 938         if (!omap_mcbsp_check_valid_id(id)) {
 939                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 940                 return;
 941         }
 942
 943         mcbsp = id_to_mcbsp_ptr(id);
 944
 945         /* Reset transmitter */
 946         tx &= 1;
 947         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
 948                 w = MCBSP_READ_CACHE(mcbsp, XCCR);
 949                 w |= (tx ? XDISABLE : 0);
 950                 MCBSP_WRITE(mcbsp, XCCR, w);
 951         }
 952         w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 953         MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
 954
 955         /* Reset receiver */
 956         rx &= 1;
 957         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
 958                 w = MCBSP_READ_CACHE(mcbsp, RCCR);
 959                 w |= (rx ? RDISABLE : 0);
 960                 MCBSP_WRITE(mcbsp, RCCR, w);
 961         }
 962         w = MCBSP_READ_CACHE(mcbsp, SPCR1);
 963         MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
 964
 965         idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
 966                         MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
 967
 968         if (idle) {
 969                 /* Reset the sample rate generator */
 970                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 971                 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
 972         }
 973
 974         if (cpu_is_omap34xx())
 975                 omap_st_stop(mcbsp);
 976 }
 977 EXPORT_SYMBOL(omap_mcbsp_stop);
 978
 979 /* polled mcbsp i/o operations */
 980 int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
 981 {
 982         struct omap_mcbsp *mcbsp;
 983
 984         if (!omap_mcbsp_check_valid_id(id)) {
 985                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 986                 return -ENODEV;
 987         }
 988
 989         mcbsp = id_to_mcbsp_ptr(id);
 990
 991         MCBSP_WRITE(mcbsp, DXR1, buf);
 992         /* if frame sync error - clear the error */
 993         if (MCBSP_READ(mcbsp, SPCR2) & XSYNC_ERR) {
 994                 /* clear error */
 995                 MCBSP_WRITE(mcbsp, SPCR2, MCBSP_READ_CACHE(mcbsp, SPCR2));
 996                 /* resend */
 997                 return -1;
 998         } else {
 999                 /* wait for transmit confirmation */
1000                 int attemps = 0;
1001                 while (!(MCBSP_READ(mcbsp, SPCR2) & XRDY)) {
1002                         if (attemps++ > 1000) {
1003                                 MCBSP_WRITE(mcbsp, SPCR2,
1004                                                 MCBSP_READ_CACHE(mcbsp, SPCR2) &
1005                                                 (~XRST));
1006                                 udelay(10);
1007                                 MCBSP_WRITE(mcbsp, SPCR2,
1008                                                 MCBSP_READ_CACHE(mcbsp, SPCR2) |
1009                                                 (XRST));
1010                                 udelay(10);
1011                                 dev_err(mcbsp->dev, "Could not write to"
1012                                         " McBSP%d Register\n", mcbsp->id);
1013                                 return -2;
1014                         }
1015                 }
1016         }
1017
1018         return 0;
1019 }
1020 EXPORT_SYMBOL(omap_mcbsp_pollwrite);
1021
1022 int omap_mcbsp_pollread(unsigned int id, u16 *buf)
1023 {
1024         struct omap_mcbsp *mcbsp;
1025
1026         if (!omap_mcbsp_check_valid_id(id)) {
1027                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1028                 return -ENODEV;
1029         }
1030         mcbsp = id_to_mcbsp_ptr(id);
1031
1032         /* if frame sync error - clear the error */
1033         if (MCBSP_READ(mcbsp, SPCR1) & RSYNC_ERR) {
1034                 /* clear error */
1035                 MCBSP_WRITE(mcbsp, SPCR1, MCBSP_READ_CACHE(mcbsp, SPCR1));
1036                 /* resend */
1037                 return -1;
1038         } else {
1039                 /* wait for recieve confirmation */
1040                 int attemps = 0;
1041                 while (!(MCBSP_READ(mcbsp, SPCR1) & RRDY)) {
1042                         if (attemps++ > 1000) {
1043                                 MCBSP_WRITE(mcbsp, SPCR1,
1044                                                 MCBSP_READ_CACHE(mcbsp, SPCR1) &
1045                                                 (~RRST));
1046                                 udelay(10);
1047                                 MCBSP_WRITE(mcbsp, SPCR1,
1048                                                 MCBSP_READ_CACHE(mcbsp, SPCR1) |
1049                                                 (RRST));
1050                                 udelay(10);
1051                                 dev_err(mcbsp->dev, "Could not read from"
1052                                         " McBSP%d Register\n", mcbsp->id);
1053                                 return -2;
1054                         }
1055                 }
1056         }
1057         *buf = MCBSP_READ(mcbsp, DRR1);
1058
1059         return 0;
1060 }
1061 EXPORT_SYMBOL(omap_mcbsp_pollread);
1062
1063 /*
1064  * IRQ based word transmission.
1065  */
1066 void omap_mcbsp_xmit_word(unsigned int id, u32 word)
1067 {
1068         struct omap_mcbsp *mcbsp;
1069         omap_mcbsp_word_length word_length;
1070
1071         if (!omap_mcbsp_check_valid_id(id)) {
1072                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1073                 return;
1074         }
1075
1076         mcbsp = id_to_mcbsp_ptr(id);
1077         word_length = mcbsp->tx_word_length;
1078
1079         wait_for_completion(&mcbsp->tx_irq_completion);
1080
1081         if (word_length > OMAP_MCBSP_WORD_16)
1082                 MCBSP_WRITE(mcbsp, DXR2, word >> 16);
1083         MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
1084 }
1085 EXPORT_SYMBOL(omap_mcbsp_xmit_word);
1086
1087 u32 omap_mcbsp_recv_word(unsigned int id)
1088 {
1089         struct omap_mcbsp *mcbsp;
1090         u16 word_lsb, word_msb = 0;
1091         omap_mcbsp_word_length word_length;
1092
1093         if (!omap_mcbsp_check_valid_id(id)) {
1094                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1095                 return -ENODEV;
1096         }
1097         mcbsp = id_to_mcbsp_ptr(id);
1098
1099         word_length = mcbsp->rx_word_length;
1100
1101         wait_for_completion(&mcbsp->rx_irq_completion);
1102
1103         if (word_length > OMAP_MCBSP_WORD_16)
1104                 word_msb = MCBSP_READ(mcbsp, DRR2);
1105         word_lsb = MCBSP_READ(mcbsp, DRR1);
1106
1107         return (word_lsb | (word_msb << 16));
1108 }
1109 EXPORT_SYMBOL(omap_mcbsp_recv_word);
1110
1111 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
1112 {
1113         struct omap_mcbsp *mcbsp;
1114         omap_mcbsp_word_length tx_word_length;
1115         omap_mcbsp_word_length rx_word_length;
1116         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
1117
1118         if (!omap_mcbsp_check_valid_id(id)) {
1119                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1120                 return -ENODEV;
1121         }
1122         mcbsp = id_to_mcbsp_ptr(id);
1123         tx_word_length = mcbsp->tx_word_length;
1124         rx_word_length = mcbsp->rx_word_length;
1125
1126         if (tx_word_length != rx_word_length)
1127                 return -EINVAL;
1128
1129         /* First we wait for the transmitter to be ready */
1130         spcr2 = MCBSP_READ(mcbsp, SPCR2);
1131         while (!(spcr2 & XRDY)) {
1132                 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1133                 if (attempts++ > 1000) {
1134                         /* We must reset the transmitter */
1135                         MCBSP_WRITE(mcbsp, SPCR2,
1136                                     MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
1137                         udelay(10);
1138                         MCBSP_WRITE(mcbsp, SPCR2,
1139                                     MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
1140                         udelay(10);
1141                         dev_err(mcbsp->dev, "McBSP%d transmitter not "
1142                                 "ready\n", mcbsp->id);
1143                         return -EAGAIN;
1144                 }
1145         }
1146
1147         /* Now we can push the data */
1148         if (tx_word_length > OMAP_MCBSP_WORD_16)
1149                 MCBSP_WRITE(mcbsp, DXR2, word >> 16);
1150         MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
1151
1152         /* We wait for the receiver to be ready */
1153         spcr1 = MCBSP_READ(mcbsp, SPCR1);
1154         while (!(spcr1 & RRDY)) {
1155                 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1156                 if (attempts++ > 1000) {
1157                         /* We must reset the receiver */
1158                         MCBSP_WRITE(mcbsp, SPCR1,
1159                                     MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
1160                         udelay(10);
1161                         MCBSP_WRITE(mcbsp, SPCR1,
1162                                     MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
1163                         udelay(10);
1164                         dev_err(mcbsp->dev, "McBSP%d receiver not "
1165                                 "ready\n", mcbsp->id);
1166                         return -EAGAIN;
1167                 }
1168         }
1169
1170         /* Receiver is ready, let's read the dummy data */
1171         if (rx_word_length > OMAP_MCBSP_WORD_16)
1172                 word_msb = MCBSP_READ(mcbsp, DRR2);
1173         word_lsb = MCBSP_READ(mcbsp, DRR1);
1174
1175         return 0;
1176 }
1177 EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
1178
1179 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
1180 {
1181         struct omap_mcbsp *mcbsp;
1182         u32 clock_word = 0;
1183         omap_mcbsp_word_length tx_word_length;
1184         omap_mcbsp_word_length rx_word_length;
1185         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
1186
1187         if (!omap_mcbsp_check_valid_id(id)) {
1188                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1189                 return -ENODEV;
1190         }
1191
1192         mcbsp = id_to_mcbsp_ptr(id);
1193
1194         tx_word_length = mcbsp->tx_word_length;
1195         rx_word_length = mcbsp->rx_word_length;
1196
1197         if (tx_word_length != rx_word_length)
1198                 return -EINVAL;
1199
1200         /* First we wait for the transmitter to be ready */
1201         spcr2 = MCBSP_READ(mcbsp, SPCR2);
1202         while (!(spcr2 & XRDY)) {
1203                 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1204                 if (attempts++ > 1000) {
1205                         /* We must reset the transmitter */
1206                         MCBSP_WRITE(mcbsp, SPCR2,
1207                                     MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
1208                         udelay(10);
1209                         MCBSP_WRITE(mcbsp, SPCR2,
1210                                     MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
1211                         udelay(10);
1212                         dev_err(mcbsp->dev, "McBSP%d transmitter not "
1213                                 "ready\n", mcbsp->id);
1214                         return -EAGAIN;
1215                 }
1216         }
1217
1218         /* We first need to enable the bus clock */
1219         if (tx_word_length > OMAP_MCBSP_WORD_16)
1220                 MCBSP_WRITE(mcbsp, DXR2, clock_word >> 16);
1221         MCBSP_WRITE(mcbsp, DXR1, clock_word & 0xffff);
1222
1223         /* We wait for the receiver to be ready */
1224         spcr1 = MCBSP_READ(mcbsp, SPCR1);
1225         while (!(spcr1 & RRDY)) {
1226                 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1227                 if (attempts++ > 1000) {
1228                         /* We must reset the receiver */
1229                         MCBSP_WRITE(mcbsp, SPCR1,
1230                                     MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
1231                         udelay(10);
1232                         MCBSP_WRITE(mcbsp, SPCR1,
1233                                     MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
1234                         udelay(10);
1235                         dev_err(mcbsp->dev, "McBSP%d receiver not "
1236                                 "ready\n", mcbsp->id);
1237                         return -EAGAIN;
1238                 }
1239         }
1240
1241         /* Receiver is ready, there is something for us */
1242         if (rx_word_length > OMAP_MCBSP_WORD_16)
1243                 word_msb = MCBSP_READ(mcbsp, DRR2);
1244         word_lsb = MCBSP_READ(mcbsp, DRR1);
1245
1246         word[0] = (word_lsb | (word_msb << 16));
1247
1248         return 0;
1249 }
1250 EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
1251
1252 /*
1253  * Simple DMA based buffer rx/tx routines.
1254  * Nothing fancy, just a single buffer tx/rx through DMA.
1255  * The DMA resources are released once the transfer is done.
1256  * For anything fancier, you should use your own customized DMA
1257  * routines and callbacks.
1258  */
1259 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
1260                                 unsigned int length)
1261 {
1262         struct omap_mcbsp *mcbsp;
1263         int dma_tx_ch;
1264         int src_port = 0;
1265         int dest_port = 0;
1266         int sync_dev = 0;
1267
1268         if (!omap_mcbsp_check_valid_id(id)) {
1269                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1270                 return -ENODEV;
1271         }
1272         mcbsp = id_to_mcbsp_ptr(id);
1273
1274         if (omap_request_dma(mcbsp->dma_tx_sync, "McBSP TX",
1275                                 omap_mcbsp_tx_dma_callback,
1276                                 mcbsp,
1277                                 &dma_tx_ch)) {
1278                 dev_err(mcbsp->dev, " Unable to request DMA channel for "
1279                                 "McBSP%d TX. Trying IRQ based TX\n",
1280                                 mcbsp->id);
1281                 return -EAGAIN;
1282         }
1283         mcbsp->dma_tx_lch = dma_tx_ch;
1284
1285         dev_err(mcbsp->dev, "McBSP%d TX DMA on channel %d\n", mcbsp->id,
1286                 dma_tx_ch);
1287
1288         init_completion(&mcbsp->tx_dma_completion);
1289
1290         if (cpu_class_is_omap1()) {
1291                 src_port = OMAP_DMA_PORT_TIPB;
1292                 dest_port = OMAP_DMA_PORT_EMIFF;
1293         }
1294         if (cpu_class_is_omap2())
1295                 sync_dev = mcbsp->dma_tx_sync;
1296
1297         omap_set_dma_transfer_params(mcbsp->dma_tx_lch,
1298                                      OMAP_DMA_DATA_TYPE_S16,
1299                                      length >> 1, 1,
1300                                      OMAP_DMA_SYNC_ELEMENT,
1301          sync_dev, 0);
1302
1303         omap_set_dma_dest_params(mcbsp->dma_tx_lch,
1304                                  src_port,
1305                                  OMAP_DMA_AMODE_CONSTANT,
1306                                  mcbsp->phys_base + OMAP_MCBSP_REG_DXR1,
1307                                  0, 0);
1308
1309         omap_set_dma_src_params(mcbsp->dma_tx_lch,
1310                                 dest_port,
1311                                 OMAP_DMA_AMODE_POST_INC,
1312                                 buffer,
1313                                 0, 0);
1314
1315         omap_start_dma(mcbsp->dma_tx_lch);
1316         wait_for_completion(&mcbsp->tx_dma_completion);
1317
1318         return 0;
1319 }
1320 EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
1321
1322 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
1323                                 unsigned int length)
1324 {
1325         struct omap_mcbsp *mcbsp;
1326         int dma_rx_ch;
1327         int src_port = 0;
1328         int dest_port = 0;
1329         int sync_dev = 0;
1330
1331         if (!omap_mcbsp_check_valid_id(id)) {
1332                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1333                 return -ENODEV;
1334         }
1335         mcbsp = id_to_mcbsp_ptr(id);
1336
1337         if (omap_request_dma(mcbsp->dma_rx_sync, "McBSP RX",
1338                                 omap_mcbsp_rx_dma_callback,
1339                                 mcbsp,
1340                                 &dma_rx_ch)) {
1341                 dev_err(mcbsp->dev, "Unable to request DMA channel for "
1342                                 "McBSP%d RX. Trying IRQ based RX\n",
1343                                 mcbsp->id);
1344                 return -EAGAIN;
1345         }
1346         mcbsp->dma_rx_lch = dma_rx_ch;
1347
1348         dev_err(mcbsp->dev, "McBSP%d RX DMA on channel %d\n", mcbsp->id,
1349                 dma_rx_ch);
1350
1351         init_completion(&mcbsp->rx_dma_completion);
1352
1353         if (cpu_class_is_omap1()) {
1354                 src_port = OMAP_DMA_PORT_TIPB;
1355                 dest_port = OMAP_DMA_PORT_EMIFF;
1356         }
1357         if (cpu_class_is_omap2())
1358                 sync_dev = mcbsp->dma_rx_sync;
1359
1360         omap_set_dma_transfer_params(mcbsp->dma_rx_lch,
1361                                         OMAP_DMA_DATA_TYPE_S16,
1362                                         length >> 1, 1,
1363                                         OMAP_DMA_SYNC_ELEMENT,
1364                                         sync_dev, 0);
1365
1366         omap_set_dma_src_params(mcbsp->dma_rx_lch,
1367                                 src_port,
1368                                 OMAP_DMA_AMODE_CONSTANT,
1369                                 mcbsp->phys_base + OMAP_MCBSP_REG_DRR1,
1370                                 0, 0);
1371
1372         omap_set_dma_dest_params(mcbsp->dma_rx_lch,
1373                                         dest_port,
1374                                         OMAP_DMA_AMODE_POST_INC,
1375                                         buffer,
1376                                         0, 0);
1377
1378         omap_start_dma(mcbsp->dma_rx_lch);
1379         wait_for_completion(&mcbsp->rx_dma_completion);
1380
1381         return 0;
1382 }
1383 EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
1384
1385 /*
1386  * SPI wrapper.
1387  * Since SPI setup is much simpler than the generic McBSP one,
1388  * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
1389  * Once this is done, you can call omap_mcbsp_start().
1390  */
1391 void omap_mcbsp_set_spi_mode(unsigned int id,
1392                                 const struct omap_mcbsp_spi_cfg *spi_cfg)
1393 {
1394         struct omap_mcbsp *mcbsp;
1395         struct omap_mcbsp_reg_cfg mcbsp_cfg;
1396
1397         if (!omap_mcbsp_check_valid_id(id)) {
1398                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1399                 return;
1400         }
1401         mcbsp = id_to_mcbsp_ptr(id);
1402
1403         memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
1404
1405         /* SPI has only one frame */
1406         mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
1407         mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
1408
1409         /* Clock stop mode */
1410         if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
1411                 mcbsp_cfg.spcr1 |= (1 << 12);
1412         else
1413                 mcbsp_cfg.spcr1 |= (3 << 11);
1414
1415         /* Set clock parities */
1416         if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1417                 mcbsp_cfg.pcr0 |= CLKRP;
1418         else
1419                 mcbsp_cfg.pcr0 &= ~CLKRP;
1420
1421         if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1422                 mcbsp_cfg.pcr0 &= ~CLKXP;
1423         else
1424                 mcbsp_cfg.pcr0 |= CLKXP;
1425
1426         /* Set SCLKME to 0 and CLKSM to 1 */
1427         mcbsp_cfg.pcr0 &= ~SCLKME;
1428         mcbsp_cfg.srgr2 |= CLKSM;
1429
1430         /* Set FSXP */
1431         if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
1432                 mcbsp_cfg.pcr0 &= ~FSXP;
1433         else
1434                 mcbsp_cfg.pcr0 |= FSXP;
1435
1436         if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
1437                 mcbsp_cfg.pcr0 |= CLKXM;
1438                 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);
1439                 mcbsp_cfg.pcr0 |= FSXM;
1440                 mcbsp_cfg.srgr2 &= ~FSGM;
1441                 mcbsp_cfg.xcr2 |= XDATDLY(1);
1442                 mcbsp_cfg.rcr2 |= RDATDLY(1);
1443         } else {
1444                 mcbsp_cfg.pcr0 &= ~CLKXM;
1445                 mcbsp_cfg.srgr1 |= CLKGDV(1);
1446                 mcbsp_cfg.pcr0 &= ~FSXM;
1447                 mcbsp_cfg.xcr2 &= ~XDATDLY(3);
1448                 mcbsp_cfg.rcr2 &= ~RDATDLY(3);
1449         }
1450
1451         mcbsp_cfg.xcr2 &= ~XPHASE;
1452         mcbsp_cfg.rcr2 &= ~RPHASE;
1453
1454         omap_mcbsp_config(id, &mcbsp_cfg);
1455 }
1456 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
1457
1458 #ifdef CONFIG_ARCH_OMAP3
1459 #define max_thres(m)                    (mcbsp->pdata->buffer_size)
1460 #define valid_threshold(m, val)         ((val) <= max_thres(m))
1461 #define THRESHOLD_PROP_BUILDER(prop)                                    \
1462 static ssize_t prop##_show(struct device *dev,                          \
1463                         struct device_attribute *attr, char *buf)       \
1464 {                                                                       \
1465         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
1466                                                                         \
1467         return sprintf(buf, "%u\n", mcbsp->prop);                       \
1468 }                                                                       \
1469                                                                         \
1470 static ssize_t prop##_store(struct device *dev,                         \
1471                                 struct device_attribute *attr,          \
1472                                 const char *buf, size_t size)           \
1473 {                                                                       \
1474         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
1475         unsigned long val;                                              \
1476         int status;                                                     \
1477                                                                         \
1478         status = strict_strtoul(buf, 0, &val);                          \
1479         if (status)                                                     \
1480                 return status;                                          \
1481                                                                         \
1482         if (!valid_threshold(mcbsp, val))                               \
1483                 return -EDOM;                                           \
1484                                                                         \
1485         mcbsp->prop = val;                                              \
1486         return size;                                                    \
1487 }                                                                       \
1488                                                                         \
1489 static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
1490
1491 THRESHOLD_PROP_BUILDER(max_tx_thres);
1492 THRESHOLD_PROP_BUILDER(max_rx_thres);
1493
1494 static const char *dma_op_modes[] = {
1495         "element", "threshold", "frame",
1496 };
1497
1498 static ssize_t dma_op_mode_show(struct device *dev,
1499                         struct device_attribute *attr, char *buf)
1500 {
1501         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1502         int dma_op_mode, i = 0;
1503         ssize_t len = 0;
1504         const char * const *s;
1505
1506         dma_op_mode = mcbsp->dma_op_mode;
1507
1508         for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
1509                 if (dma_op_mode == i)
1510                         len += sprintf(buf + len, "[%s] ", *s);
1511                 else
1512                         len += sprintf(buf + len, "%s ", *s);
1513         }
1514         len += sprintf(buf + len, "\n");
1515
1516         return len;
1517 }
1518
1519 static ssize_t dma_op_mode_store(struct device *dev,
1520                                 struct device_attribute *attr,
1521                                 const char *buf, size_t size)
1522 {
1523         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1524         const char * const *s;
1525         int i = 0;
1526
1527         for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
1528                 if (sysfs_streq(buf, *s))
1529                         break;
1530
1531         if (i == ARRAY_SIZE(dma_op_modes))
1532                 return -EINVAL;
1533
1534         spin_lock_irq(&mcbsp->lock);
1535         if (!mcbsp->free) {
1536                 size = -EBUSY;
1537                 goto unlock;
1538         }
1539         mcbsp->dma_op_mode = i;
1540
1541 unlock:
1542         spin_unlock_irq(&mcbsp->lock);
1543
1544         return size;
1545 }
1546
1547 static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
1548
1549 static ssize_t st_taps_show(struct device *dev,
1550                             struct device_attribute *attr, char *buf)
1551 {
1552         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1553         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1554         ssize_t status = 0;
1555         int i;
1556
1557         spin_lock_irq(&mcbsp->lock);
1558         for (i = 0; i < st_data->nr_taps; i++)
1559                 status += sprintf(&buf[status], (i ? ", %d" : "%d"),
1560                                   st_data->taps[i]);
1561         if (i)
1562                 status += sprintf(&buf[status], "\n");
1563         spin_unlock_irq(&mcbsp->lock);
1564
1565         return status;
1566 }
1567
1568 static ssize_t st_taps_store(struct device *dev,
1569                              struct device_attribute *attr,
1570                              const char *buf, size_t size)
1571 {
1572         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1573         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1574         int val, tmp, status, i = 0;
1575
1576         spin_lock_irq(&mcbsp->lock);
1577         memset(st_data->taps, 0, sizeof(st_data->taps));
1578         st_data->nr_taps = 0;
1579
1580         do {
1581                 status = sscanf(buf, "%d%n", &val, &tmp);
1582                 if (status < 0 || status == 0) {
1583                         size = -EINVAL;
1584                         goto out;
1585                 }
1586                 if (val < -32768 || val > 32767) {
1587                         size = -EINVAL;
1588                         goto out;
1589                 }
1590                 st_data->taps[i++] = val;
1591                 buf += tmp;
1592                 if (*buf != ',')
1593                         break;
1594                 buf++;
1595         } while (1);
1596
1597         st_data->nr_taps = i;
1598
1599 out:
1600         spin_unlock_irq(&mcbsp->lock);
1601
1602         return size;
1603 }
1604
1605 static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
1606
1607 static const struct attribute *additional_attrs[] = {
1608         &dev_attr_max_tx_thres.attr,
1609         &dev_attr_max_rx_thres.attr,
1610         &dev_attr_dma_op_mode.attr,
1611         NULL,
1612 };
1613
1614 static const struct attribute_group additional_attr_group = {
1615         .attrs = (struct attribute **)additional_attrs,
1616 };
1617
1618 static inline int __devinit omap_additional_add(struct device *dev)
1619 {
1620         return sysfs_create_group(&dev->kobj, &additional_attr_group);
1621 }
1622
1623 static inline void __devexit omap_additional_remove(struct device *dev)
1624 {
1625         sysfs_remove_group(&dev->kobj, &additional_attr_group);
1626 }
1627
1628 static const struct attribute *sidetone_attrs[] = {
1629         &dev_attr_st_taps.attr,
1630         NULL,
1631 };
1632
1633 static const struct attribute_group sidetone_attr_group = {
1634         .attrs = (struct attribute **)sidetone_attrs,
1635 };
1636
1637 int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
1638 {
1639         struct omap_mcbsp_platform_data *pdata = mcbsp->pdata;
1640         struct omap_mcbsp_st_data *st_data;
1641         int err;
1642
1643         st_data = kzalloc(sizeof(*mcbsp->st_data), GFP_KERNEL);
1644         if (!st_data) {
1645                 err = -ENOMEM;
1646                 goto err1;
1647         }
1648
1649         st_data->io_base_st = ioremap(pdata->phys_base_st, SZ_4K);
1650         if (!st_data->io_base_st) {
1651                 err = -ENOMEM;
1652                 goto err2;
1653         }
1654
1655         err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1656         if (err)
1657                 goto err3;
1658
1659         mcbsp->st_data = st_data;
1660         return 0;
1661
1662 err3:
1663         iounmap(st_data->io_base_st);
1664 err2:
1665         kfree(st_data);
1666 err1:
1667         return err;
1668
1669 }
1670
1671 static void __devexit omap_st_remove(struct omap_mcbsp *mcbsp)
1672 {
1673         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1674
1675         if (st_data) {
1676                 sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1677                 iounmap(st_data->io_base_st);
1678                 kfree(st_data);
1679         }
1680 }
1681
1682 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
1683 {
1684         mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1685         if (cpu_is_omap34xx()) {
1686                 mcbsp->max_tx_thres = max_thres(mcbsp);
1687                 mcbsp->max_rx_thres = max_thres(mcbsp);
1688                 /*
1689                  * REVISIT: Set dmap_op_mode to THRESHOLD as default
1690                  * for mcbsp2 instances.
1691                  */
1692                 if (omap_additional_add(mcbsp->dev))
1693                         dev_warn(mcbsp->dev,
1694                                 "Unable to create additional controls\n");
1695
1696                 if (mcbsp->id == 2 || mcbsp->id == 3)
1697                         if (omap_st_add(mcbsp))
1698                                 dev_warn(mcbsp->dev,
1699                                  "Unable to create sidetone controls\n");
1700
1701         } else {
1702                 mcbsp->max_tx_thres = -EINVAL;
1703                 mcbsp->max_rx_thres = -EINVAL;
1704         }
1705 }
1706
1707 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
1708 {
1709         if (cpu_is_omap34xx()) {
1710                 omap_additional_remove(mcbsp->dev);
1711
1712                 if (mcbsp->id == 2 || mcbsp->id == 3)
1713                         omap_st_remove(mcbsp);
1714         }
1715 }
1716 #else
1717 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
1718 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
1719 #endif /* CONFIG_ARCH_OMAP3 */
1720
1721 /*
1722  * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
1723  * 730 has only 2 McBSP, and both of them are MPU peripherals.
1724  */
1725 static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1726 {
1727         struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
1728         struct omap_mcbsp *mcbsp;
1729         int id = pdev->id - 1;
1730         int ret = 0;
1731
1732         if (!pdata) {
1733                 dev_err(&pdev->dev, "McBSP device initialized without"
1734                                 "platform data\n");
1735                 ret = -EINVAL;
1736                 goto exit;
1737         }
1738
1739         dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
1740
1741         if (id >= omap_mcbsp_count) {
1742                 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
1743                 ret = -EINVAL;
1744                 goto exit;
1745         }
1746
1747         mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
1748         if (!mcbsp) {
1749                 ret = -ENOMEM;
1750                 goto exit;
1751         }
1752
1753         spin_lock_init(&mcbsp->lock);
1754         mcbsp->id = id + 1;
1755         mcbsp->free = 1;
1756         mcbsp->dma_tx_lch = -1;
1757         mcbsp->dma_rx_lch = -1;
1758
1759         mcbsp->phys_base = pdata->phys_base;
1760         mcbsp->io_base = ioremap(pdata->phys_base, SZ_4K);
1761         if (!mcbsp->io_base) {
1762                 ret = -ENOMEM;
1763                 goto err_ioremap;
1764         }
1765
1766         /* Default I/O is IRQ based */
1767         mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
1768         mcbsp->tx_irq = pdata->tx_irq;
1769         mcbsp->rx_irq = pdata->rx_irq;
1770         mcbsp->dma_rx_sync = pdata->dma_rx_sync;
1771         mcbsp->dma_tx_sync = pdata->dma_tx_sync;
1772
1773         mcbsp->iclk = clk_get(&pdev->dev, "ick");
1774         if (IS_ERR(mcbsp->iclk)) {
1775                 ret = PTR_ERR(mcbsp->iclk);
1776                 dev_err(&pdev->dev, "unable to get ick: %d\n", ret);
1777                 goto err_iclk;
1778         }
1779
1780         mcbsp->fclk = clk_get(&pdev->dev, "fck");
1781         if (IS_ERR(mcbsp->fclk)) {
1782                 ret = PTR_ERR(mcbsp->fclk);
1783                 dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
1784                 goto err_fclk;
1785         }
1786
1787         mcbsp->pdata = pdata;
1788         mcbsp->dev = &pdev->dev;
1789         mcbsp_ptr[id] = mcbsp;
1790         platform_set_drvdata(pdev, mcbsp);
1791
1792         /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
1793         omap34xx_device_init(mcbsp);
1794
1795         return 0;
1796
1797 err_fclk:
1798         clk_put(mcbsp->iclk);
1799 err_iclk:
1800         iounmap(mcbsp->io_base);
1801 err_ioremap:
1802         kfree(mcbsp);
1803 exit:
1804         return ret;
1805 }
1806
1807 static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
1808 {
1809         struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
1810
1811         platform_set_drvdata(pdev, NULL);
1812         if (mcbsp) {
1813
1814                 if (mcbsp->pdata && mcbsp->pdata->ops &&
1815                                 mcbsp->pdata->ops->free)
1816                         mcbsp->pdata->ops->free(mcbsp->id);
1817
1818                 omap34xx_device_exit(mcbsp);
1819
1820                 clk_disable(mcbsp->fclk);
1821                 clk_disable(mcbsp->iclk);
1822                 clk_put(mcbsp->fclk);
1823                 clk_put(mcbsp->iclk);
1824
1825                 iounmap(mcbsp->io_base);
1826
1827                 mcbsp->fclk = NULL;
1828                 mcbsp->iclk = NULL;
1829                 mcbsp->free = 0;
1830                 mcbsp->dev = NULL;
1831         }
1832
1833         return 0;
1834 }
1835
1836 static struct platform_driver omap_mcbsp_driver = {
1837         .probe          = omap_mcbsp_probe,
1838         .remove         = __devexit_p(omap_mcbsp_remove),
1839         .driver         = {
1840                 .name   = "omap-mcbsp",
1841         },
1842 };
1843
1844 int __init omap_mcbsp_init(void)
1845 {
1846         /* Register the McBSP driver */
1847         return platform_driver_register(&omap_mcbsp_driver);
1848 }