2 * linux/arch/arm/plat-omap/mcbsp.c
4 * Copyright (C) 2004 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Multichannel mode not supported.
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/device.h>
18 #include <linux/platform_device.h>
19 #include <linux/wait.h>
20 #include <linux/completion.h>
21 #include <linux/interrupt.h>
22 #include <linux/err.h>
23 #include <linux/clk.h>
24 #include <linux/delay.h>
26 #include <linux/slab.h>
29 #include <plat/mcbsp.h>
30 #include <plat/omap_device.h>
32 /* XXX These "sideways" includes are a sign that something is wrong */
33 #include "../mach-omap2/cm2xxx_3xxx.h"
34 #include "../mach-omap2/cm-regbits-34xx.h"
36 struct omap_mcbsp **mcbsp_ptr;
37 int omap_mcbsp_count, omap_mcbsp_cache_size;
39 static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
41 if (cpu_class_is_omap1()) {
42 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)] = (u16)val;
43 __raw_writew((u16)val, mcbsp->io_base + reg);
44 } else if (cpu_is_omap2420()) {
45 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)] = (u16)val;
46 __raw_writew((u16)val, mcbsp->io_base + reg);
48 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)] = val;
49 __raw_writel(val, mcbsp->io_base + reg);
53 static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
55 if (cpu_class_is_omap1()) {
56 return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
57 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)];
58 } else if (cpu_is_omap2420()) {
59 return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
60 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)];
62 return !from_cache ? __raw_readl(mcbsp->io_base + reg) :
63 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)];
67 #ifdef CONFIG_ARCH_OMAP3
68 static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
70 __raw_writel(val, mcbsp->st_data->io_base_st + reg);
73 static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
75 return __raw_readl(mcbsp->st_data->io_base_st + reg);
79 #define MCBSP_READ(mcbsp, reg) \
80 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
81 #define MCBSP_WRITE(mcbsp, reg, val) \
82 omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
83 #define MCBSP_READ_CACHE(mcbsp, reg) \
84 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
86 #define MCBSP_ST_READ(mcbsp, reg) \
87 omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
88 #define MCBSP_ST_WRITE(mcbsp, reg, val) \
89 omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
91 static void omap_mcbsp_dump_reg(u8 id)
93 struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
95 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
96 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n",
97 MCBSP_READ(mcbsp, DRR2));
98 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n",
99 MCBSP_READ(mcbsp, DRR1));
100 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n",
101 MCBSP_READ(mcbsp, DXR2));
102 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n",
103 MCBSP_READ(mcbsp, DXR1));
104 dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
105 MCBSP_READ(mcbsp, SPCR2));
106 dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
107 MCBSP_READ(mcbsp, SPCR1));
108 dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n",
109 MCBSP_READ(mcbsp, RCR2));
110 dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n",
111 MCBSP_READ(mcbsp, RCR1));
112 dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n",
113 MCBSP_READ(mcbsp, XCR2));
114 dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n",
115 MCBSP_READ(mcbsp, XCR1));
116 dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
117 MCBSP_READ(mcbsp, SRGR2));
118 dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
119 MCBSP_READ(mcbsp, SRGR1));
120 dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n",
121 MCBSP_READ(mcbsp, PCR0));
122 dev_dbg(mcbsp->dev, "***********************\n");
125 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
127 struct omap_mcbsp *mcbsp_tx = dev_id;
130 irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2);
131 dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
133 if (irqst_spcr2 & XSYNC_ERR) {
134 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
136 /* Writing zero to XSYNC_ERR clears the IRQ */
137 MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2));
139 complete(&mcbsp_tx->tx_irq_completion);
145 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
147 struct omap_mcbsp *mcbsp_rx = dev_id;
150 irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1);
151 dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
153 if (irqst_spcr1 & RSYNC_ERR) {
154 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
156 /* Writing zero to RSYNC_ERR clears the IRQ */
157 MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
159 complete(&mcbsp_rx->rx_irq_completion);
165 static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
167 struct omap_mcbsp *mcbsp_dma_tx = data;
169 dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
170 MCBSP_READ(mcbsp_dma_tx, SPCR2));
172 /* We can free the channels */
173 omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
174 mcbsp_dma_tx->dma_tx_lch = -1;
176 complete(&mcbsp_dma_tx->tx_dma_completion);
179 static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
181 struct omap_mcbsp *mcbsp_dma_rx = data;
183 dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
184 MCBSP_READ(mcbsp_dma_rx, SPCR2));
186 /* We can free the channels */
187 omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
188 mcbsp_dma_rx->dma_rx_lch = -1;
190 complete(&mcbsp_dma_rx->rx_dma_completion);
194 * omap_mcbsp_config simply write a config to the
196 * You either call this function or set the McBSP registers
197 * by yourself before calling omap_mcbsp_start().
199 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
201 struct omap_mcbsp *mcbsp;
203 if (!omap_mcbsp_check_valid_id(id)) {
204 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
207 mcbsp = id_to_mcbsp_ptr(id);
209 dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
210 mcbsp->id, mcbsp->phys_base);
212 /* We write the given config */
213 MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
214 MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
215 MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
216 MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
217 MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
218 MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
219 MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
220 MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
221 MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
222 MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
223 MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
224 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
225 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
226 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
229 EXPORT_SYMBOL(omap_mcbsp_config);
231 #ifdef CONFIG_ARCH_OMAP3
232 static struct omap_device *find_omap_device_by_dev(struct device *dev)
234 struct platform_device *pdev = container_of(dev,
235 struct platform_device, dev);
236 return container_of(pdev, struct omap_device, pdev);
239 static void omap_st_on(struct omap_mcbsp *mcbsp)
242 struct omap_device *od;
244 od = find_omap_device_by_dev(mcbsp->dev);
247 * Sidetone uses McBSP ICLK - which must not idle when sidetones
248 * are enabled or sidetones start sounding ugly.
250 w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
251 w &= ~(1 << (mcbsp->id - 2));
252 omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
254 /* Enable McBSP Sidetone */
255 w = MCBSP_READ(mcbsp, SSELCR);
256 MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
258 /* Enable Sidetone from Sidetone Core */
259 w = MCBSP_ST_READ(mcbsp, SSELCR);
260 MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
263 static void omap_st_off(struct omap_mcbsp *mcbsp)
266 struct omap_device *od;
268 od = find_omap_device_by_dev(mcbsp->dev);
270 w = MCBSP_ST_READ(mcbsp, SSELCR);
271 MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
273 w = MCBSP_READ(mcbsp, SSELCR);
274 MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
276 w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
277 w |= 1 << (mcbsp->id - 2);
278 omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
281 static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
284 struct omap_device *od;
286 od = find_omap_device_by_dev(mcbsp->dev);
288 val = MCBSP_ST_READ(mcbsp, SSELCR);
290 if (val & ST_COEFFWREN)
291 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
293 MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN);
295 for (i = 0; i < 128; i++)
296 MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]);
300 val = MCBSP_ST_READ(mcbsp, SSELCR);
301 while (!(val & ST_COEFFWRDONE) && (++i < 1000))
302 val = MCBSP_ST_READ(mcbsp, SSELCR);
304 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
307 dev_err(mcbsp->dev, "McBSP FIR load error!\n");
310 static void omap_st_chgain(struct omap_mcbsp *mcbsp)
313 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
314 struct omap_device *od;
316 od = find_omap_device_by_dev(mcbsp->dev);
318 w = MCBSP_ST_READ(mcbsp, SSELCR);
320 MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \
321 ST_CH1GAIN(st_data->ch1gain));
324 int omap_st_set_chgain(unsigned int id, int channel, s16 chgain)
326 struct omap_mcbsp *mcbsp;
327 struct omap_mcbsp_st_data *st_data;
330 if (!omap_mcbsp_check_valid_id(id)) {
331 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
335 mcbsp = id_to_mcbsp_ptr(id);
336 st_data = mcbsp->st_data;
341 spin_lock_irq(&mcbsp->lock);
343 st_data->ch0gain = chgain;
344 else if (channel == 1)
345 st_data->ch1gain = chgain;
349 if (st_data->enabled)
350 omap_st_chgain(mcbsp);
351 spin_unlock_irq(&mcbsp->lock);
355 EXPORT_SYMBOL(omap_st_set_chgain);
357 int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain)
359 struct omap_mcbsp *mcbsp;
360 struct omap_mcbsp_st_data *st_data;
363 if (!omap_mcbsp_check_valid_id(id)) {
364 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
368 mcbsp = id_to_mcbsp_ptr(id);
369 st_data = mcbsp->st_data;
374 spin_lock_irq(&mcbsp->lock);
376 *chgain = st_data->ch0gain;
377 else if (channel == 1)
378 *chgain = st_data->ch1gain;
381 spin_unlock_irq(&mcbsp->lock);
385 EXPORT_SYMBOL(omap_st_get_chgain);
387 static int omap_st_start(struct omap_mcbsp *mcbsp)
389 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
391 if (st_data && st_data->enabled && !st_data->running) {
392 omap_st_fir_write(mcbsp, st_data->taps);
393 omap_st_chgain(mcbsp);
397 st_data->running = 1;
404 int omap_st_enable(unsigned int id)
406 struct omap_mcbsp *mcbsp;
407 struct omap_mcbsp_st_data *st_data;
409 if (!omap_mcbsp_check_valid_id(id)) {
410 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
414 mcbsp = id_to_mcbsp_ptr(id);
415 st_data = mcbsp->st_data;
420 spin_lock_irq(&mcbsp->lock);
421 st_data->enabled = 1;
422 omap_st_start(mcbsp);
423 spin_unlock_irq(&mcbsp->lock);
427 EXPORT_SYMBOL(omap_st_enable);
429 static int omap_st_stop(struct omap_mcbsp *mcbsp)
431 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
433 if (st_data && st_data->running) {
436 st_data->running = 0;
443 int omap_st_disable(unsigned int id)
445 struct omap_mcbsp *mcbsp;
446 struct omap_mcbsp_st_data *st_data;
449 if (!omap_mcbsp_check_valid_id(id)) {
450 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
454 mcbsp = id_to_mcbsp_ptr(id);
455 st_data = mcbsp->st_data;
460 spin_lock_irq(&mcbsp->lock);
462 st_data->enabled = 0;
463 spin_unlock_irq(&mcbsp->lock);
467 EXPORT_SYMBOL(omap_st_disable);
469 int omap_st_is_enabled(unsigned int id)
471 struct omap_mcbsp *mcbsp;
472 struct omap_mcbsp_st_data *st_data;
474 if (!omap_mcbsp_check_valid_id(id)) {
475 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
479 mcbsp = id_to_mcbsp_ptr(id);
480 st_data = mcbsp->st_data;
486 return st_data->enabled;
488 EXPORT_SYMBOL(omap_st_is_enabled);
491 * omap_mcbsp_set_rx_threshold configures the transmit threshold in words.
492 * The threshold parameter is 1 based, and it is converted (threshold - 1)
493 * for the THRSH2 register.
495 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
497 struct omap_mcbsp *mcbsp;
499 if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
502 if (!omap_mcbsp_check_valid_id(id)) {
503 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
506 mcbsp = id_to_mcbsp_ptr(id);
508 if (threshold && threshold <= mcbsp->max_tx_thres)
509 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
511 EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
514 * omap_mcbsp_set_rx_threshold configures the receive threshold in words.
515 * The threshold parameter is 1 based, and it is converted (threshold - 1)
516 * for the THRSH1 register.
518 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
520 struct omap_mcbsp *mcbsp;
522 if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
525 if (!omap_mcbsp_check_valid_id(id)) {
526 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
529 mcbsp = id_to_mcbsp_ptr(id);
531 if (threshold && threshold <= mcbsp->max_rx_thres)
532 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
534 EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
537 * omap_mcbsp_get_max_tx_thres just return the current configured
538 * maximum threshold for transmission
540 u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
542 struct omap_mcbsp *mcbsp;
544 if (!omap_mcbsp_check_valid_id(id)) {
545 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
548 mcbsp = id_to_mcbsp_ptr(id);
550 return mcbsp->max_tx_thres;
552 EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
555 * omap_mcbsp_get_max_rx_thres just return the current configured
556 * maximum threshold for reception
558 u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
560 struct omap_mcbsp *mcbsp;
562 if (!omap_mcbsp_check_valid_id(id)) {
563 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
566 mcbsp = id_to_mcbsp_ptr(id);
568 return mcbsp->max_rx_thres;
570 EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
572 u16 omap_mcbsp_get_fifo_size(unsigned int id)
574 struct omap_mcbsp *mcbsp;
576 if (!omap_mcbsp_check_valid_id(id)) {
577 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
580 mcbsp = id_to_mcbsp_ptr(id);
582 return mcbsp->pdata->buffer_size;
584 EXPORT_SYMBOL(omap_mcbsp_get_fifo_size);
587 * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
589 u16 omap_mcbsp_get_tx_delay(unsigned int id)
591 struct omap_mcbsp *mcbsp;
594 if (!omap_mcbsp_check_valid_id(id)) {
595 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
598 mcbsp = id_to_mcbsp_ptr(id);
600 /* Returns the number of free locations in the buffer */
601 buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
603 /* Number of slots are different in McBSP ports */
604 return mcbsp->pdata->buffer_size - buffstat;
606 EXPORT_SYMBOL(omap_mcbsp_get_tx_delay);
609 * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
610 * to reach the threshold value (when the DMA will be triggered to read it)
612 u16 omap_mcbsp_get_rx_delay(unsigned int id)
614 struct omap_mcbsp *mcbsp;
615 u16 buffstat, threshold;
617 if (!omap_mcbsp_check_valid_id(id)) {
618 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
621 mcbsp = id_to_mcbsp_ptr(id);
623 /* Returns the number of used locations in the buffer */
624 buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
626 threshold = MCBSP_READ(mcbsp, THRSH1);
628 /* Return the number of location till we reach the threshold limit */
629 if (threshold <= buffstat)
632 return threshold - buffstat;
634 EXPORT_SYMBOL(omap_mcbsp_get_rx_delay);
637 * omap_mcbsp_get_dma_op_mode just return the current configured
638 * operating mode for the mcbsp channel
640 int omap_mcbsp_get_dma_op_mode(unsigned int id)
642 struct omap_mcbsp *mcbsp;
645 if (!omap_mcbsp_check_valid_id(id)) {
646 printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1);
649 mcbsp = id_to_mcbsp_ptr(id);
651 dma_op_mode = mcbsp->dma_op_mode;
655 EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
657 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
659 struct omap_device *od;
661 od = find_omap_device_by_dev(mcbsp->dev);
663 * Enable wakup behavior, smart idle and all wakeups
664 * REVISIT: some wakeups may be unnecessary
666 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
667 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
671 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
673 struct omap_device *od;
675 od = find_omap_device_by_dev(mcbsp->dev);
678 * Disable wakup behavior, smart idle and all wakeups
680 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
682 * HW bug workaround - If no_idle mode is taken, we need to
683 * go to smart_idle before going to always_idle, or the
684 * device will not hit retention anymore.
687 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
691 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {}
692 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {}
693 static inline void omap_st_start(struct omap_mcbsp *mcbsp) {}
694 static inline void omap_st_stop(struct omap_mcbsp *mcbsp) {}
698 * We can choose between IRQ based or polled IO.
699 * This needs to be called before omap_mcbsp_request().
701 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
703 struct omap_mcbsp *mcbsp;
705 if (!omap_mcbsp_check_valid_id(id)) {
706 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
709 mcbsp = id_to_mcbsp_ptr(id);
711 spin_lock(&mcbsp->lock);
714 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
716 spin_unlock(&mcbsp->lock);
720 mcbsp->io_type = io_type;
722 spin_unlock(&mcbsp->lock);
726 EXPORT_SYMBOL(omap_mcbsp_set_io_type);
728 int omap_mcbsp_request(unsigned int id)
730 struct omap_mcbsp *mcbsp;
734 if (!omap_mcbsp_check_valid_id(id)) {
735 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
738 mcbsp = id_to_mcbsp_ptr(id);
740 reg_cache = kzalloc(omap_mcbsp_cache_size, GFP_KERNEL);
745 spin_lock(&mcbsp->lock);
747 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
754 mcbsp->reg_cache = reg_cache;
755 spin_unlock(&mcbsp->lock);
757 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
758 mcbsp->pdata->ops->request(id);
760 clk_enable(mcbsp->iclk);
761 clk_enable(mcbsp->fclk);
763 /* Do procedure specific to omap34xx arch, if applicable */
764 omap34xx_mcbsp_request(mcbsp);
767 * Make sure that transmitter, receiver and sample-rate generator are
768 * not running before activating IRQs.
770 MCBSP_WRITE(mcbsp, SPCR1, 0);
771 MCBSP_WRITE(mcbsp, SPCR2, 0);
773 if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
774 /* We need to get IRQs here */
775 init_completion(&mcbsp->tx_irq_completion);
776 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
777 0, "McBSP", (void *)mcbsp);
779 dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
780 "for McBSP%d\n", mcbsp->tx_irq,
782 goto err_clk_disable;
786 init_completion(&mcbsp->rx_irq_completion);
787 err = request_irq(mcbsp->rx_irq,
788 omap_mcbsp_rx_irq_handler,
789 0, "McBSP", (void *)mcbsp);
791 dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
792 "for McBSP%d\n", mcbsp->rx_irq,
801 free_irq(mcbsp->tx_irq, (void *)mcbsp);
803 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
804 mcbsp->pdata->ops->free(id);
806 /* Do procedure specific to omap34xx arch, if applicable */
807 omap34xx_mcbsp_free(mcbsp);
809 clk_disable(mcbsp->fclk);
810 clk_disable(mcbsp->iclk);
812 spin_lock(&mcbsp->lock);
814 mcbsp->reg_cache = NULL;
816 spin_unlock(&mcbsp->lock);
821 EXPORT_SYMBOL(omap_mcbsp_request);
823 void omap_mcbsp_free(unsigned int id)
825 struct omap_mcbsp *mcbsp;
828 if (!omap_mcbsp_check_valid_id(id)) {
829 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
832 mcbsp = id_to_mcbsp_ptr(id);
834 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
835 mcbsp->pdata->ops->free(id);
837 /* Do procedure specific to omap34xx arch, if applicable */
838 omap34xx_mcbsp_free(mcbsp);
840 clk_disable(mcbsp->fclk);
841 clk_disable(mcbsp->iclk);
843 if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
846 free_irq(mcbsp->rx_irq, (void *)mcbsp);
847 free_irq(mcbsp->tx_irq, (void *)mcbsp);
850 reg_cache = mcbsp->reg_cache;
852 spin_lock(&mcbsp->lock);
854 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
857 mcbsp->reg_cache = NULL;
858 spin_unlock(&mcbsp->lock);
863 EXPORT_SYMBOL(omap_mcbsp_free);
866 * Here we start the McBSP, by enabling transmitter, receiver or both.
867 * If no transmitter or receiver is active prior calling, then sample-rate
868 * generator and frame sync are started.
870 void omap_mcbsp_start(unsigned int id, int tx, int rx)
872 struct omap_mcbsp *mcbsp;
876 if (!omap_mcbsp_check_valid_id(id)) {
877 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
880 mcbsp = id_to_mcbsp_ptr(id);
882 if (cpu_is_omap34xx())
883 omap_st_start(mcbsp);
885 mcbsp->rx_word_length = (MCBSP_READ_CACHE(mcbsp, RCR1) >> 5) & 0x7;
886 mcbsp->tx_word_length = (MCBSP_READ_CACHE(mcbsp, XCR1) >> 5) & 0x7;
888 /* Only enable SRG, if McBSP is master */
889 w = MCBSP_READ_CACHE(mcbsp, PCR0);
890 if (w & (FSXM | FSRM | CLKXM | CLKRM))
891 enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
892 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
895 /* Start the sample generator */
896 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
897 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
900 /* Enable transmitter and receiver */
902 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
903 MCBSP_WRITE(mcbsp, SPCR2, w | tx);
906 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
907 MCBSP_WRITE(mcbsp, SPCR1, w | rx);
910 * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
911 * REVISIT: 100us may give enough time for two CLKSRG, however
912 * due to some unknown PM related, clock gating etc. reason it
918 /* Start frame sync */
919 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
920 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
923 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
924 /* Release the transmitter and receiver */
925 w = MCBSP_READ_CACHE(mcbsp, XCCR);
926 w &= ~(tx ? XDISABLE : 0);
927 MCBSP_WRITE(mcbsp, XCCR, w);
928 w = MCBSP_READ_CACHE(mcbsp, RCCR);
929 w &= ~(rx ? RDISABLE : 0);
930 MCBSP_WRITE(mcbsp, RCCR, w);
933 /* Dump McBSP Regs */
934 omap_mcbsp_dump_reg(id);
936 EXPORT_SYMBOL(omap_mcbsp_start);
938 void omap_mcbsp_stop(unsigned int id, int tx, int rx)
940 struct omap_mcbsp *mcbsp;
944 if (!omap_mcbsp_check_valid_id(id)) {
945 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
949 mcbsp = id_to_mcbsp_ptr(id);
951 /* Reset transmitter */
953 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
954 w = MCBSP_READ_CACHE(mcbsp, XCCR);
955 w |= (tx ? XDISABLE : 0);
956 MCBSP_WRITE(mcbsp, XCCR, w);
958 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
959 MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
963 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
964 w = MCBSP_READ_CACHE(mcbsp, RCCR);
965 w |= (rx ? RDISABLE : 0);
966 MCBSP_WRITE(mcbsp, RCCR, w);
968 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
969 MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
971 idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
972 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
975 /* Reset the sample rate generator */
976 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
977 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
980 if (cpu_is_omap34xx())
983 EXPORT_SYMBOL(omap_mcbsp_stop);
985 /* polled mcbsp i/o operations */
986 int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
988 struct omap_mcbsp *mcbsp;
990 if (!omap_mcbsp_check_valid_id(id)) {
991 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
995 mcbsp = id_to_mcbsp_ptr(id);
997 MCBSP_WRITE(mcbsp, DXR1, buf);
998 /* if frame sync error - clear the error */
999 if (MCBSP_READ(mcbsp, SPCR2) & XSYNC_ERR) {
1001 MCBSP_WRITE(mcbsp, SPCR2, MCBSP_READ_CACHE(mcbsp, SPCR2));
1005 /* wait for transmit confirmation */
1007 while (!(MCBSP_READ(mcbsp, SPCR2) & XRDY)) {
1008 if (attemps++ > 1000) {
1009 MCBSP_WRITE(mcbsp, SPCR2,
1010 MCBSP_READ_CACHE(mcbsp, SPCR2) &
1013 MCBSP_WRITE(mcbsp, SPCR2,
1014 MCBSP_READ_CACHE(mcbsp, SPCR2) |
1017 dev_err(mcbsp->dev, "Could not write to"
1018 " McBSP%d Register\n", mcbsp->id);
1026 EXPORT_SYMBOL(omap_mcbsp_pollwrite);
1028 int omap_mcbsp_pollread(unsigned int id, u16 *buf)
1030 struct omap_mcbsp *mcbsp;
1032 if (!omap_mcbsp_check_valid_id(id)) {
1033 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1036 mcbsp = id_to_mcbsp_ptr(id);
1038 /* if frame sync error - clear the error */
1039 if (MCBSP_READ(mcbsp, SPCR1) & RSYNC_ERR) {
1041 MCBSP_WRITE(mcbsp, SPCR1, MCBSP_READ_CACHE(mcbsp, SPCR1));
1045 /* wait for recieve confirmation */
1047 while (!(MCBSP_READ(mcbsp, SPCR1) & RRDY)) {
1048 if (attemps++ > 1000) {
1049 MCBSP_WRITE(mcbsp, SPCR1,
1050 MCBSP_READ_CACHE(mcbsp, SPCR1) &
1053 MCBSP_WRITE(mcbsp, SPCR1,
1054 MCBSP_READ_CACHE(mcbsp, SPCR1) |
1057 dev_err(mcbsp->dev, "Could not read from"
1058 " McBSP%d Register\n", mcbsp->id);
1063 *buf = MCBSP_READ(mcbsp, DRR1);
1067 EXPORT_SYMBOL(omap_mcbsp_pollread);
1070 * IRQ based word transmission.
1072 void omap_mcbsp_xmit_word(unsigned int id, u32 word)
1074 struct omap_mcbsp *mcbsp;
1075 omap_mcbsp_word_length word_length;
1077 if (!omap_mcbsp_check_valid_id(id)) {
1078 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1082 mcbsp = id_to_mcbsp_ptr(id);
1083 word_length = mcbsp->tx_word_length;
1085 wait_for_completion(&mcbsp->tx_irq_completion);
1087 if (word_length > OMAP_MCBSP_WORD_16)
1088 MCBSP_WRITE(mcbsp, DXR2, word >> 16);
1089 MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
1091 EXPORT_SYMBOL(omap_mcbsp_xmit_word);
1093 u32 omap_mcbsp_recv_word(unsigned int id)
1095 struct omap_mcbsp *mcbsp;
1096 u16 word_lsb, word_msb = 0;
1097 omap_mcbsp_word_length word_length;
1099 if (!omap_mcbsp_check_valid_id(id)) {
1100 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1103 mcbsp = id_to_mcbsp_ptr(id);
1105 word_length = mcbsp->rx_word_length;
1107 wait_for_completion(&mcbsp->rx_irq_completion);
1109 if (word_length > OMAP_MCBSP_WORD_16)
1110 word_msb = MCBSP_READ(mcbsp, DRR2);
1111 word_lsb = MCBSP_READ(mcbsp, DRR1);
1113 return (word_lsb | (word_msb << 16));
1115 EXPORT_SYMBOL(omap_mcbsp_recv_word);
1117 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
1119 struct omap_mcbsp *mcbsp;
1120 omap_mcbsp_word_length tx_word_length;
1121 omap_mcbsp_word_length rx_word_length;
1122 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
1124 if (!omap_mcbsp_check_valid_id(id)) {
1125 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1128 mcbsp = id_to_mcbsp_ptr(id);
1129 tx_word_length = mcbsp->tx_word_length;
1130 rx_word_length = mcbsp->rx_word_length;
1132 if (tx_word_length != rx_word_length)
1135 /* First we wait for the transmitter to be ready */
1136 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1137 while (!(spcr2 & XRDY)) {
1138 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1139 if (attempts++ > 1000) {
1140 /* We must reset the transmitter */
1141 MCBSP_WRITE(mcbsp, SPCR2,
1142 MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
1144 MCBSP_WRITE(mcbsp, SPCR2,
1145 MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
1147 dev_err(mcbsp->dev, "McBSP%d transmitter not "
1148 "ready\n", mcbsp->id);
1153 /* Now we can push the data */
1154 if (tx_word_length > OMAP_MCBSP_WORD_16)
1155 MCBSP_WRITE(mcbsp, DXR2, word >> 16);
1156 MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
1158 /* We wait for the receiver to be ready */
1159 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1160 while (!(spcr1 & RRDY)) {
1161 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1162 if (attempts++ > 1000) {
1163 /* We must reset the receiver */
1164 MCBSP_WRITE(mcbsp, SPCR1,
1165 MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
1167 MCBSP_WRITE(mcbsp, SPCR1,
1168 MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
1170 dev_err(mcbsp->dev, "McBSP%d receiver not "
1171 "ready\n", mcbsp->id);
1176 /* Receiver is ready, let's read the dummy data */
1177 if (rx_word_length > OMAP_MCBSP_WORD_16)
1178 word_msb = MCBSP_READ(mcbsp, DRR2);
1179 word_lsb = MCBSP_READ(mcbsp, DRR1);
1183 EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
1185 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
1187 struct omap_mcbsp *mcbsp;
1189 omap_mcbsp_word_length tx_word_length;
1190 omap_mcbsp_word_length rx_word_length;
1191 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
1193 if (!omap_mcbsp_check_valid_id(id)) {
1194 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1198 mcbsp = id_to_mcbsp_ptr(id);
1200 tx_word_length = mcbsp->tx_word_length;
1201 rx_word_length = mcbsp->rx_word_length;
1203 if (tx_word_length != rx_word_length)
1206 /* First we wait for the transmitter to be ready */
1207 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1208 while (!(spcr2 & XRDY)) {
1209 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1210 if (attempts++ > 1000) {
1211 /* We must reset the transmitter */
1212 MCBSP_WRITE(mcbsp, SPCR2,
1213 MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
1215 MCBSP_WRITE(mcbsp, SPCR2,
1216 MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
1218 dev_err(mcbsp->dev, "McBSP%d transmitter not "
1219 "ready\n", mcbsp->id);
1224 /* We first need to enable the bus clock */
1225 if (tx_word_length > OMAP_MCBSP_WORD_16)
1226 MCBSP_WRITE(mcbsp, DXR2, clock_word >> 16);
1227 MCBSP_WRITE(mcbsp, DXR1, clock_word & 0xffff);
1229 /* We wait for the receiver to be ready */
1230 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1231 while (!(spcr1 & RRDY)) {
1232 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1233 if (attempts++ > 1000) {
1234 /* We must reset the receiver */
1235 MCBSP_WRITE(mcbsp, SPCR1,
1236 MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
1238 MCBSP_WRITE(mcbsp, SPCR1,
1239 MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
1241 dev_err(mcbsp->dev, "McBSP%d receiver not "
1242 "ready\n", mcbsp->id);
1247 /* Receiver is ready, there is something for us */
1248 if (rx_word_length > OMAP_MCBSP_WORD_16)
1249 word_msb = MCBSP_READ(mcbsp, DRR2);
1250 word_lsb = MCBSP_READ(mcbsp, DRR1);
1252 word[0] = (word_lsb | (word_msb << 16));
1256 EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
1259 * Simple DMA based buffer rx/tx routines.
1260 * Nothing fancy, just a single buffer tx/rx through DMA.
1261 * The DMA resources are released once the transfer is done.
1262 * For anything fancier, you should use your own customized DMA
1263 * routines and callbacks.
1265 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
1266 unsigned int length)
1268 struct omap_mcbsp *mcbsp;
1274 if (!omap_mcbsp_check_valid_id(id)) {
1275 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1278 mcbsp = id_to_mcbsp_ptr(id);
1280 if (omap_request_dma(mcbsp->dma_tx_sync, "McBSP TX",
1281 omap_mcbsp_tx_dma_callback,
1284 dev_err(mcbsp->dev, " Unable to request DMA channel for "
1285 "McBSP%d TX. Trying IRQ based TX\n",
1289 mcbsp->dma_tx_lch = dma_tx_ch;
1291 dev_err(mcbsp->dev, "McBSP%d TX DMA on channel %d\n", mcbsp->id,
1294 init_completion(&mcbsp->tx_dma_completion);
1296 if (cpu_class_is_omap1()) {
1297 src_port = OMAP_DMA_PORT_TIPB;
1298 dest_port = OMAP_DMA_PORT_EMIFF;
1300 if (cpu_class_is_omap2())
1301 sync_dev = mcbsp->dma_tx_sync;
1303 omap_set_dma_transfer_params(mcbsp->dma_tx_lch,
1304 OMAP_DMA_DATA_TYPE_S16,
1306 OMAP_DMA_SYNC_ELEMENT,
1309 omap_set_dma_dest_params(mcbsp->dma_tx_lch,
1311 OMAP_DMA_AMODE_CONSTANT,
1312 mcbsp->phys_base + OMAP_MCBSP_REG_DXR1,
1315 omap_set_dma_src_params(mcbsp->dma_tx_lch,
1317 OMAP_DMA_AMODE_POST_INC,
1321 omap_start_dma(mcbsp->dma_tx_lch);
1322 wait_for_completion(&mcbsp->tx_dma_completion);
1326 EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
1328 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
1329 unsigned int length)
1331 struct omap_mcbsp *mcbsp;
1337 if (!omap_mcbsp_check_valid_id(id)) {
1338 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1341 mcbsp = id_to_mcbsp_ptr(id);
1343 if (omap_request_dma(mcbsp->dma_rx_sync, "McBSP RX",
1344 omap_mcbsp_rx_dma_callback,
1347 dev_err(mcbsp->dev, "Unable to request DMA channel for "
1348 "McBSP%d RX. Trying IRQ based RX\n",
1352 mcbsp->dma_rx_lch = dma_rx_ch;
1354 dev_err(mcbsp->dev, "McBSP%d RX DMA on channel %d\n", mcbsp->id,
1357 init_completion(&mcbsp->rx_dma_completion);
1359 if (cpu_class_is_omap1()) {
1360 src_port = OMAP_DMA_PORT_TIPB;
1361 dest_port = OMAP_DMA_PORT_EMIFF;
1363 if (cpu_class_is_omap2())
1364 sync_dev = mcbsp->dma_rx_sync;
1366 omap_set_dma_transfer_params(mcbsp->dma_rx_lch,
1367 OMAP_DMA_DATA_TYPE_S16,
1369 OMAP_DMA_SYNC_ELEMENT,
1372 omap_set_dma_src_params(mcbsp->dma_rx_lch,
1374 OMAP_DMA_AMODE_CONSTANT,
1375 mcbsp->phys_base + OMAP_MCBSP_REG_DRR1,
1378 omap_set_dma_dest_params(mcbsp->dma_rx_lch,
1380 OMAP_DMA_AMODE_POST_INC,
1384 omap_start_dma(mcbsp->dma_rx_lch);
1385 wait_for_completion(&mcbsp->rx_dma_completion);
1389 EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
1393 * Since SPI setup is much simpler than the generic McBSP one,
1394 * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
1395 * Once this is done, you can call omap_mcbsp_start().
1397 void omap_mcbsp_set_spi_mode(unsigned int id,
1398 const struct omap_mcbsp_spi_cfg *spi_cfg)
1400 struct omap_mcbsp *mcbsp;
1401 struct omap_mcbsp_reg_cfg mcbsp_cfg;
1403 if (!omap_mcbsp_check_valid_id(id)) {
1404 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1407 mcbsp = id_to_mcbsp_ptr(id);
1409 memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
1411 /* SPI has only one frame */
1412 mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
1413 mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
1415 /* Clock stop mode */
1416 if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
1417 mcbsp_cfg.spcr1 |= (1 << 12);
1419 mcbsp_cfg.spcr1 |= (3 << 11);
1421 /* Set clock parities */
1422 if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1423 mcbsp_cfg.pcr0 |= CLKRP;
1425 mcbsp_cfg.pcr0 &= ~CLKRP;
1427 if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1428 mcbsp_cfg.pcr0 &= ~CLKXP;
1430 mcbsp_cfg.pcr0 |= CLKXP;
1432 /* Set SCLKME to 0 and CLKSM to 1 */
1433 mcbsp_cfg.pcr0 &= ~SCLKME;
1434 mcbsp_cfg.srgr2 |= CLKSM;
1437 if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
1438 mcbsp_cfg.pcr0 &= ~FSXP;
1440 mcbsp_cfg.pcr0 |= FSXP;
1442 if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
1443 mcbsp_cfg.pcr0 |= CLKXM;
1444 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);
1445 mcbsp_cfg.pcr0 |= FSXM;
1446 mcbsp_cfg.srgr2 &= ~FSGM;
1447 mcbsp_cfg.xcr2 |= XDATDLY(1);
1448 mcbsp_cfg.rcr2 |= RDATDLY(1);
1450 mcbsp_cfg.pcr0 &= ~CLKXM;
1451 mcbsp_cfg.srgr1 |= CLKGDV(1);
1452 mcbsp_cfg.pcr0 &= ~FSXM;
1453 mcbsp_cfg.xcr2 &= ~XDATDLY(3);
1454 mcbsp_cfg.rcr2 &= ~RDATDLY(3);
1457 mcbsp_cfg.xcr2 &= ~XPHASE;
1458 mcbsp_cfg.rcr2 &= ~RPHASE;
1460 omap_mcbsp_config(id, &mcbsp_cfg);
1462 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
1464 #ifdef CONFIG_ARCH_OMAP3
1465 #define max_thres(m) (mcbsp->pdata->buffer_size)
1466 #define valid_threshold(m, val) ((val) <= max_thres(m))
1467 #define THRESHOLD_PROP_BUILDER(prop) \
1468 static ssize_t prop##_show(struct device *dev, \
1469 struct device_attribute *attr, char *buf) \
1471 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
1473 return sprintf(buf, "%u\n", mcbsp->prop); \
1476 static ssize_t prop##_store(struct device *dev, \
1477 struct device_attribute *attr, \
1478 const char *buf, size_t size) \
1480 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
1481 unsigned long val; \
1484 status = strict_strtoul(buf, 0, &val); \
1488 if (!valid_threshold(mcbsp, val)) \
1491 mcbsp->prop = val; \
1495 static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
1497 THRESHOLD_PROP_BUILDER(max_tx_thres);
1498 THRESHOLD_PROP_BUILDER(max_rx_thres);
1500 static const char *dma_op_modes[] = {
1501 "element", "threshold", "frame",
1504 static ssize_t dma_op_mode_show(struct device *dev,
1505 struct device_attribute *attr, char *buf)
1507 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1508 int dma_op_mode, i = 0;
1510 const char * const *s;
1512 dma_op_mode = mcbsp->dma_op_mode;
1514 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
1515 if (dma_op_mode == i)
1516 len += sprintf(buf + len, "[%s] ", *s);
1518 len += sprintf(buf + len, "%s ", *s);
1520 len += sprintf(buf + len, "\n");
1525 static ssize_t dma_op_mode_store(struct device *dev,
1526 struct device_attribute *attr,
1527 const char *buf, size_t size)
1529 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1530 const char * const *s;
1533 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
1534 if (sysfs_streq(buf, *s))
1537 if (i == ARRAY_SIZE(dma_op_modes))
1540 spin_lock_irq(&mcbsp->lock);
1545 mcbsp->dma_op_mode = i;
1548 spin_unlock_irq(&mcbsp->lock);
1553 static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
1555 static ssize_t st_taps_show(struct device *dev,
1556 struct device_attribute *attr, char *buf)
1558 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1559 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1563 spin_lock_irq(&mcbsp->lock);
1564 for (i = 0; i < st_data->nr_taps; i++)
1565 status += sprintf(&buf[status], (i ? ", %d" : "%d"),
1568 status += sprintf(&buf[status], "\n");
1569 spin_unlock_irq(&mcbsp->lock);
1574 static ssize_t st_taps_store(struct device *dev,
1575 struct device_attribute *attr,
1576 const char *buf, size_t size)
1578 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1579 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1580 int val, tmp, status, i = 0;
1582 spin_lock_irq(&mcbsp->lock);
1583 memset(st_data->taps, 0, sizeof(st_data->taps));
1584 st_data->nr_taps = 0;
1587 status = sscanf(buf, "%d%n", &val, &tmp);
1588 if (status < 0 || status == 0) {
1592 if (val < -32768 || val > 32767) {
1596 st_data->taps[i++] = val;
1603 st_data->nr_taps = i;
1606 spin_unlock_irq(&mcbsp->lock);
1611 static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
1613 static const struct attribute *additional_attrs[] = {
1614 &dev_attr_max_tx_thres.attr,
1615 &dev_attr_max_rx_thres.attr,
1616 &dev_attr_dma_op_mode.attr,
1620 static const struct attribute_group additional_attr_group = {
1621 .attrs = (struct attribute **)additional_attrs,
1624 static inline int __devinit omap_additional_add(struct device *dev)
1626 return sysfs_create_group(&dev->kobj, &additional_attr_group);
1629 static inline void __devexit omap_additional_remove(struct device *dev)
1631 sysfs_remove_group(&dev->kobj, &additional_attr_group);
1634 static const struct attribute *sidetone_attrs[] = {
1635 &dev_attr_st_taps.attr,
1639 static const struct attribute_group sidetone_attr_group = {
1640 .attrs = (struct attribute **)sidetone_attrs,
1643 static int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
1645 struct platform_device *pdev;
1646 struct resource *res;
1647 struct omap_mcbsp_st_data *st_data;
1650 st_data = kzalloc(sizeof(*mcbsp->st_data), GFP_KERNEL);
1656 pdev = container_of(mcbsp->dev, struct platform_device, dev);
1658 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone");
1659 st_data->io_base_st = ioremap(res->start, resource_size(res));
1660 if (!st_data->io_base_st) {
1665 err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1669 mcbsp->st_data = st_data;
1673 iounmap(st_data->io_base_st);
1681 static void __devexit omap_st_remove(struct omap_mcbsp *mcbsp)
1683 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1686 sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1687 iounmap(st_data->io_base_st);
1692 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
1694 mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1695 if (cpu_is_omap34xx()) {
1697 * Initially configure the maximum thresholds to a safe value.
1698 * The McBSP FIFO usage with these values should not go under
1700 * If the whole FIFO without safety buffer is used, than there
1701 * is a possibility that the DMA will be not able to push the
1702 * new data on time, causing channel shifts in runtime.
1704 mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
1705 mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
1707 * REVISIT: Set dmap_op_mode to THRESHOLD as default
1708 * for mcbsp2 instances.
1710 if (omap_additional_add(mcbsp->dev))
1711 dev_warn(mcbsp->dev,
1712 "Unable to create additional controls\n");
1714 if (mcbsp->id == 2 || mcbsp->id == 3)
1715 if (omap_st_add(mcbsp))
1716 dev_warn(mcbsp->dev,
1717 "Unable to create sidetone controls\n");
1720 mcbsp->max_tx_thres = -EINVAL;
1721 mcbsp->max_rx_thres = -EINVAL;
1725 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
1727 if (cpu_is_omap34xx()) {
1728 omap_additional_remove(mcbsp->dev);
1730 if (mcbsp->id == 2 || mcbsp->id == 3)
1731 omap_st_remove(mcbsp);
1735 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
1736 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
1737 #endif /* CONFIG_ARCH_OMAP3 */
1740 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
1741 * 730 has only 2 McBSP, and both of them are MPU peripherals.
1743 static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1745 struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
1746 struct omap_mcbsp *mcbsp;
1747 int id = pdev->id - 1;
1748 struct resource *res;
1752 dev_err(&pdev->dev, "McBSP device initialized without"
1758 dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
1760 if (id >= omap_mcbsp_count) {
1761 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
1766 mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
1772 spin_lock_init(&mcbsp->lock);
1775 mcbsp->dma_tx_lch = -1;
1776 mcbsp->dma_rx_lch = -1;
1778 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1780 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1782 dev_err(&pdev->dev, "%s:mcbsp%d has invalid memory"
1783 "resource\n", __func__, pdev->id);
1788 mcbsp->phys_base = res->start;
1789 omap_mcbsp_cache_size = resource_size(res);
1790 mcbsp->io_base = ioremap(res->start, resource_size(res));
1791 if (!mcbsp->io_base) {
1796 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
1798 mcbsp->phys_dma_base = mcbsp->phys_base;
1800 mcbsp->phys_dma_base = res->start;
1802 /* Default I/O is IRQ based */
1803 mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
1805 mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
1806 mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
1808 /* From OMAP4 there will be a single irq line */
1809 if (mcbsp->tx_irq == -ENXIO)
1810 mcbsp->tx_irq = platform_get_irq(pdev, 0);
1812 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1814 dev_err(&pdev->dev, "%s:mcbsp%d has invalid rx DMA channel\n",
1815 __func__, pdev->id);
1819 mcbsp->dma_rx_sync = res->start;
1821 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1823 dev_err(&pdev->dev, "%s:mcbsp%d has invalid tx DMA channel\n",
1824 __func__, pdev->id);
1828 mcbsp->dma_tx_sync = res->start;
1830 mcbsp->iclk = clk_get(&pdev->dev, "ick");
1831 if (IS_ERR(mcbsp->iclk)) {
1832 ret = PTR_ERR(mcbsp->iclk);
1833 dev_err(&pdev->dev, "unable to get ick: %d\n", ret);
1837 mcbsp->fclk = clk_get(&pdev->dev, "fck");
1838 if (IS_ERR(mcbsp->fclk)) {
1839 ret = PTR_ERR(mcbsp->fclk);
1840 dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
1844 mcbsp->pdata = pdata;
1845 mcbsp->dev = &pdev->dev;
1846 mcbsp_ptr[id] = mcbsp;
1847 platform_set_drvdata(pdev, mcbsp);
1849 /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
1850 omap34xx_device_init(mcbsp);
1855 clk_put(mcbsp->iclk);
1857 iounmap(mcbsp->io_base);
1864 static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
1866 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
1868 platform_set_drvdata(pdev, NULL);
1871 if (mcbsp->pdata && mcbsp->pdata->ops &&
1872 mcbsp->pdata->ops->free)
1873 mcbsp->pdata->ops->free(mcbsp->id);
1875 omap34xx_device_exit(mcbsp);
1877 clk_put(mcbsp->fclk);
1878 clk_put(mcbsp->iclk);
1880 iounmap(mcbsp->io_base);
1887 static struct platform_driver omap_mcbsp_driver = {
1888 .probe = omap_mcbsp_probe,
1889 .remove = __devexit_p(omap_mcbsp_remove),
1891 .name = "omap-mcbsp",
1895 int __init omap_mcbsp_init(void)
1897 /* Register the McBSP driver */
1898 return platform_driver_register(&omap_mcbsp_driver);