1 // include/asm-arm/mach-omap/usb.h
3 #ifndef __ASM_ARCH_OMAP_USB_H
4 #define __ASM_ARCH_OMAP_USB_H
6 #include <linux/usb/musb.h>
7 #include <plat/board.h>
9 #define OMAP3_HS_USB_PORTS 3
11 enum usbhs_omap_port_mode {
12 OMAP_USBHS_PORT_MODE_UNUSED,
13 OMAP_EHCI_PORT_MODE_PHY,
14 OMAP_EHCI_PORT_MODE_TLL,
15 OMAP_EHCI_PORT_MODE_HSIC,
16 OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0,
17 OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM,
18 OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0,
19 OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM,
20 OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0,
21 OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM,
22 OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0,
23 OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM,
24 OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0,
25 OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM
28 struct usbhs_omap_board_data {
29 enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
31 /* have to be valid if phy_reset is true and portx is in phy mode */
32 int reset_gpio_port[OMAP3_HS_USB_PORTS];
34 /* Set this to true for ES2.x silicon */
35 unsigned es2_compatibility:1;
40 * Regulators for USB PHYs.
41 * Each PHY can have a separate regulator.
43 struct regulator *regulator[OMAP3_HS_USB_PORTS];
46 struct ehci_hcd_omap_platform_data {
47 enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
48 int reset_gpio_port[OMAP3_HS_USB_PORTS];
49 struct regulator *regulator_vbus[OMAP3_HS_USB_PORTS];
50 struct regulator *regulator[OMAP3_HS_USB_PORTS];
54 struct ohci_hcd_omap_platform_data {
55 enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
56 unsigned es2_compatibility:1;
59 struct usbhs_omap_platform_data {
60 enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
62 struct ehci_hcd_omap_platform_data *ehci_data;
63 struct ohci_hcd_omap_platform_data *ohci_data;
65 /*-------------------------------------------------------------------------*/
67 #define OMAP1_OTG_BASE 0xfffb0400
68 #define OMAP1_UDC_BASE 0xfffb4000
69 #define OMAP1_OHCI_BASE 0xfffba000
71 #define OMAP2_OHCI_BASE 0x4805e000
72 #define OMAP2_UDC_BASE 0x4805e200
73 #define OMAP2_OTG_BASE 0x4805e300
75 #ifdef CONFIG_ARCH_OMAP1
77 #define OTG_BASE OMAP1_OTG_BASE
78 #define UDC_BASE OMAP1_UDC_BASE
79 #define OMAP_OHCI_BASE OMAP1_OHCI_BASE
83 #define OTG_BASE OMAP2_OTG_BASE
84 #define UDC_BASE OMAP2_UDC_BASE
85 #define OMAP_OHCI_BASE OMAP2_OHCI_BASE
87 struct omap_musb_board_data {
92 void (*set_phy_power)(u8 on);
93 void (*clear_irq)(void);
94 void (*set_mode)(u8 mode);
98 enum musb_interface {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI};
100 extern void usb_musb_init(struct omap_musb_board_data *board_data);
102 extern void usbhs_init(const struct usbhs_omap_board_data *pdata);
104 extern int omap_usbhs_enable(struct device *dev);
105 extern void omap_usbhs_disable(struct device *dev);
107 extern int omap4430_phy_power(struct device *dev, int ID, int on);
108 extern int omap4430_phy_set_clk(struct device *dev, int on);
109 extern int omap4430_phy_init(struct device *dev);
110 extern int omap4430_phy_exit(struct device *dev);
111 extern int omap4430_phy_suspend(struct device *dev, int suspend);
114 extern void am35x_musb_reset(void);
115 extern void am35x_musb_phy_power(u8 on);
116 extern void am35x_musb_clear_irq(void);
117 extern void am35x_set_mode(u8 musb_mode);
120 * FIXME correct answer depends on hmc_mode,
121 * as does (on omap1) any nonzero value for config->otg port number
123 #ifdef CONFIG_USB_GADGET_OMAP
124 #define is_usb0_device(config) 1
126 #define is_usb0_device(config) 0
129 void omap_otg_init(struct omap_usb_config *config);
131 #if defined(CONFIG_USB) || defined(CONFIG_USB_MODULE)
132 void omap1_usb_init(struct omap_usb_config *pdata);
134 static inline void omap1_usb_init(struct omap_usb_config *pdata)
139 #if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP_OTG_MODULE)
140 void omap2_usbfs_init(struct omap_usb_config *pdata);
142 static inline void omap2_usbfs_init(struct omap_usb_config *pdata)
147 /*-------------------------------------------------------------------------*/
150 * OTG and transceiver registers, for OMAPs starting with ARM926
152 #define OTG_REV (OTG_BASE + 0x00)
153 #define OTG_SYSCON_1 (OTG_BASE + 0x04)
154 # define USB2_TRX_MODE(w) (((w)>>24)&0x07)
155 # define USB1_TRX_MODE(w) (((w)>>20)&0x07)
156 # define USB0_TRX_MODE(w) (((w)>>16)&0x07)
157 # define OTG_IDLE_EN (1 << 15)
158 # define HST_IDLE_EN (1 << 14)
159 # define DEV_IDLE_EN (1 << 13)
160 # define OTG_RESET_DONE (1 << 2)
161 # define OTG_SOFT_RESET (1 << 1)
162 #define OTG_SYSCON_2 (OTG_BASE + 0x08)
163 # define OTG_EN (1 << 31)
164 # define USBX_SYNCHRO (1 << 30)
165 # define OTG_MST16 (1 << 29)
166 # define SRP_GPDATA (1 << 28)
167 # define SRP_GPDVBUS (1 << 27)
168 # define SRP_GPUVBUS(w) (((w)>>24)&0x07)
169 # define A_WAIT_VRISE(w) (((w)>>20)&0x07)
170 # define B_ASE_BRST(w) (((w)>>16)&0x07)
171 # define SRP_DPW (1 << 14)
172 # define SRP_DATA (1 << 13)
173 # define SRP_VBUS (1 << 12)
174 # define OTG_PADEN (1 << 10)
175 # define HMC_PADEN (1 << 9)
176 # define UHOST_EN (1 << 8)
177 # define HMC_TLLSPEED (1 << 7)
178 # define HMC_TLLATTACH (1 << 6)
179 # define OTG_HMC(w) (((w)>>0)&0x3f)
180 #define OTG_CTRL (OTG_BASE + 0x0c)
181 # define OTG_USB2_EN (1 << 29)
182 # define OTG_USB2_DP (1 << 28)
183 # define OTG_USB2_DM (1 << 27)
184 # define OTG_USB1_EN (1 << 26)
185 # define OTG_USB1_DP (1 << 25)
186 # define OTG_USB1_DM (1 << 24)
187 # define OTG_USB0_EN (1 << 23)
188 # define OTG_USB0_DP (1 << 22)
189 # define OTG_USB0_DM (1 << 21)
190 # define OTG_ASESSVLD (1 << 20)
191 # define OTG_BSESSEND (1 << 19)
192 # define OTG_BSESSVLD (1 << 18)
193 # define OTG_VBUSVLD (1 << 17)
194 # define OTG_ID (1 << 16)
195 # define OTG_DRIVER_SEL (1 << 15)
196 # define OTG_A_SETB_HNPEN (1 << 12)
197 # define OTG_A_BUSREQ (1 << 11)
198 # define OTG_B_HNPEN (1 << 9)
199 # define OTG_B_BUSREQ (1 << 8)
200 # define OTG_BUSDROP (1 << 7)
201 # define OTG_PULLDOWN (1 << 5)
202 # define OTG_PULLUP (1 << 4)
203 # define OTG_DRV_VBUS (1 << 3)
204 # define OTG_PD_VBUS (1 << 2)
205 # define OTG_PU_VBUS (1 << 1)
206 # define OTG_PU_ID (1 << 0)
207 #define OTG_IRQ_EN (OTG_BASE + 0x10) /* 16-bit */
208 # define DRIVER_SWITCH (1 << 15)
209 # define A_VBUS_ERR (1 << 13)
210 # define A_REQ_TMROUT (1 << 12)
211 # define A_SRP_DETECT (1 << 11)
212 # define B_HNP_FAIL (1 << 10)
213 # define B_SRP_TMROUT (1 << 9)
214 # define B_SRP_DONE (1 << 8)
215 # define B_SRP_STARTED (1 << 7)
216 # define OPRT_CHG (1 << 0)
217 #define OTG_IRQ_SRC (OTG_BASE + 0x14) /* 16-bit */
218 // same bits as in IRQ_EN
219 #define OTG_OUTCTRL (OTG_BASE + 0x18) /* 16-bit */
220 # define OTGVPD (1 << 14)
221 # define OTGVPU (1 << 13)
222 # define OTGPUID (1 << 12)
223 # define USB2VDR (1 << 10)
224 # define USB2PDEN (1 << 9)
225 # define USB2PUEN (1 << 8)
226 # define USB1VDR (1 << 6)
227 # define USB1PDEN (1 << 5)
228 # define USB1PUEN (1 << 4)
229 # define USB0VDR (1 << 2)
230 # define USB0PDEN (1 << 1)
231 # define USB0PUEN (1 << 0)
232 #define OTG_TEST (OTG_BASE + 0x20) /* 16-bit */
233 #define OTG_VENDOR_CODE (OTG_BASE + 0xfc) /* 16-bit */
235 /*-------------------------------------------------------------------------*/
238 #define USB_TRANSCEIVER_CTRL (0xfffe1000 + 0x0064)
239 # define CONF_USB2_UNI_R (1 << 8)
240 # define CONF_USB1_UNI_R (1 << 7)
241 # define CONF_USB_PORT0_R(x) (((x)>>4)&0x7)
242 # define CONF_USB0_ISOLATE_R (1 << 3)
243 # define CONF_USB_PWRDN_DM_R (1 << 2)
244 # define CONF_USB_PWRDN_DP_R (1 << 1)
247 # define USB_UNIDIR 0x0
248 # define USB_UNIDIR_TLL 0x1
249 # define USB_BIDIR 0x2
250 # define USB_BIDIR_TLL 0x3
251 # define USBTXWRMODEI(port, x) ((x) << (22 - (port * 2)))
252 # define USBT2TLL5PI (1 << 17)
253 # define USB0PUENACTLOI (1 << 16)
254 # define USBSTANDBYCTRL (1 << 15)
256 /* USB 2.0 PHY Control */
257 #define CONF2_PHY_GPIOMODE (1 << 23)
258 #define CONF2_OTGMODE (3 << 14)
259 #define CONF2_NO_OVERRIDE (0 << 14)
260 #define CONF2_FORCE_HOST (1 << 14)
261 #define CONF2_FORCE_DEVICE (2 << 14)
262 #define CONF2_FORCE_HOST_VBUS_LOW (3 << 14)
263 #define CONF2_SESENDEN (1 << 13)
264 #define CONF2_VBDTCTEN (1 << 12)
265 #define CONF2_REFFREQ_24MHZ (2 << 8)
266 #define CONF2_REFFREQ_26MHZ (7 << 8)
267 #define CONF2_REFFREQ_13MHZ (6 << 8)
268 #define CONF2_REFFREQ (0xf << 8)
269 #define CONF2_PHYCLKGD (1 << 7)
270 #define CONF2_VBUSSENSE (1 << 6)
271 #define CONF2_PHY_PLLON (1 << 5)
272 #define CONF2_RESET (1 << 4)
273 #define CONF2_PHYPWRDN (1 << 3)
274 #define CONF2_OTGPWRDN (1 << 2)
275 #define CONF2_DATPOL (1 << 1)
277 #if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_USB)
278 u32 omap1_usb0_init(unsigned nwires, unsigned is_device);
279 u32 omap1_usb1_init(unsigned nwires);
280 u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup);
282 static inline u32 omap1_usb0_init(unsigned nwires, unsigned is_device)
286 static inline u32 omap1_usb1_init(unsigned nwires)
291 static inline u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup)
297 #endif /* __ASM_ARCH_OMAP_USB_H */