2 * arch/arm/plat-omap/include/plat/dmtimer.h
4 * OMAP Dual-Mode Timers
6 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
7 * Tarun Kanti DebBarma <tarun.kanti@ti.com>
8 * Thara Gopinath <thara@ti.com>
10 * Platform device conversion and hwmod support.
12 * Copyright (C) 2005 Nokia Corporation
13 * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
14 * PWM and clock framwork support by Timo Teras.
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
21 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
24 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 * You should have received a copy of the GNU General Public License along
31 * with this program; if not, write to the Free Software Foundation, Inc.,
32 * 675 Mass Ave, Cambridge, MA 02139, USA.
35 #include <linux/clk.h>
36 #include <linux/delay.h>
38 #include <linux/platform_device.h>
40 #ifndef __ASM_ARCH_DMTIMER_H
41 #define __ASM_ARCH_DMTIMER_H
44 #define OMAP_TIMER_SRC_SYS_CLK 0x00
45 #define OMAP_TIMER_SRC_32_KHZ 0x01
46 #define OMAP_TIMER_SRC_EXT_CLK 0x02
48 /* timer interrupt enable bits */
49 #define OMAP_TIMER_INT_CAPTURE (1 << 2)
50 #define OMAP_TIMER_INT_OVERFLOW (1 << 1)
51 #define OMAP_TIMER_INT_MATCH (1 << 0)
54 #define OMAP_TIMER_TRIGGER_NONE 0x00
55 #define OMAP_TIMER_TRIGGER_OVERFLOW 0x01
56 #define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
59 * IP revision identifier so that Highlander IP
60 * in OMAP4 can be distinguished.
62 #define OMAP_TIMER_IP_VERSION_1 0x1
64 /* timer capabilities used in hwmod database */
65 #define OMAP_TIMER_SECURE 0x80000000
66 #define OMAP_TIMER_ALWON 0x40000000
67 #define OMAP_TIMER_HAS_PWM 0x20000000
69 struct omap_timer_capability_dev_attr {
96 struct dmtimer_platform_data {
97 int (*set_timer_src)(struct platform_device *pdev, int source);
99 u32 needs_manual_reset:1;
104 int (*get_context_loss_count)(struct device *dev);
107 struct omap_dm_timer *omap_dm_timer_request(void);
108 struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
109 int omap_dm_timer_free(struct omap_dm_timer *timer);
110 void omap_dm_timer_enable(struct omap_dm_timer *timer);
111 void omap_dm_timer_disable(struct omap_dm_timer *timer);
113 int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
115 u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
116 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer);
118 int omap_dm_timer_trigger(struct omap_dm_timer *timer);
119 int omap_dm_timer_start(struct omap_dm_timer *timer);
120 int omap_dm_timer_stop(struct omap_dm_timer *timer);
122 int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
123 int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
124 int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
125 int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
126 int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
127 int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
129 int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value);
131 unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer);
132 int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value);
133 unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer);
134 int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value);
136 int omap_dm_timers_active(void);
139 * Do not use the defines below, they are not needed. They should be only
140 * used by dmtimer.c and sys_timer related code.
144 * The interrupt registers are different between v1 and v2 ip.
145 * These registers are offsets from timer->iobase.
147 #define OMAP_TIMER_ID_OFFSET 0x00
148 #define OMAP_TIMER_OCP_CFG_OFFSET 0x10
150 #define OMAP_TIMER_V1_SYS_STAT_OFFSET 0x14
151 #define OMAP_TIMER_V1_STAT_OFFSET 0x18
152 #define OMAP_TIMER_V1_INT_EN_OFFSET 0x1c
154 #define OMAP_TIMER_V2_IRQSTATUS_RAW 0x24
155 #define OMAP_TIMER_V2_IRQSTATUS 0x28
156 #define OMAP_TIMER_V2_IRQENABLE_SET 0x2c
157 #define OMAP_TIMER_V2_IRQENABLE_CLR 0x30
160 * The functional registers have a different base on v1 and v2 ip.
161 * These registers are offsets from timer->func_base. The func_base
162 * is samae as io_base for v1 and io_base + 0x14 for v2 ip.
165 #define OMAP_TIMER_V2_FUNC_OFFSET 0x14
167 #define _OMAP_TIMER_WAKEUP_EN_OFFSET 0x20
168 #define _OMAP_TIMER_CTRL_OFFSET 0x24
169 #define OMAP_TIMER_CTRL_GPOCFG (1 << 14)
170 #define OMAP_TIMER_CTRL_CAPTMODE (1 << 13)
171 #define OMAP_TIMER_CTRL_PT (1 << 12)
172 #define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8)
173 #define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8)
174 #define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8)
175 #define OMAP_TIMER_CTRL_SCPWM (1 << 7)
176 #define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */
177 #define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */
178 #define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* prescaler value shift */
179 #define OMAP_TIMER_CTRL_POSTED (1 << 2)
180 #define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */
181 #define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */
182 #define _OMAP_TIMER_COUNTER_OFFSET 0x28
183 #define _OMAP_TIMER_LOAD_OFFSET 0x2c
184 #define _OMAP_TIMER_TRIGGER_OFFSET 0x30
185 #define _OMAP_TIMER_WRITE_PEND_OFFSET 0x34
186 #define WP_NONE 0 /* no write pending bit */
187 #define WP_TCLR (1 << 0)
188 #define WP_TCRR (1 << 1)
189 #define WP_TLDR (1 << 2)
190 #define WP_TTGR (1 << 3)
191 #define WP_TMAR (1 << 4)
192 #define WP_TPIR (1 << 5)
193 #define WP_TNIR (1 << 6)
194 #define WP_TCVR (1 << 7)
195 #define WP_TOCR (1 << 8)
196 #define WP_TOWR (1 << 9)
197 #define _OMAP_TIMER_MATCH_OFFSET 0x38
198 #define _OMAP_TIMER_CAPTURE_OFFSET 0x3c
199 #define _OMAP_TIMER_IF_CTRL_OFFSET 0x40
200 #define _OMAP_TIMER_CAPTURE2_OFFSET 0x44 /* TCAR2, 34xx only */
201 #define _OMAP_TIMER_TICK_POS_OFFSET 0x48 /* TPIR, 34xx only */
202 #define _OMAP_TIMER_TICK_NEG_OFFSET 0x4c /* TNIR, 34xx only */
203 #define _OMAP_TIMER_TICK_COUNT_OFFSET 0x50 /* TCVR, 34xx only */
204 #define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET 0x54 /* TOCR, 34xx only */
205 #define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET 0x58 /* TOWR, 34xx only */
207 /* register offsets with the write pending bit encoded */
210 #define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \
211 | (WP_NONE << WPSHIFT))
213 #define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \
214 | (WP_TCLR << WPSHIFT))
216 #define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \
217 | (WP_TCRR << WPSHIFT))
219 #define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \
220 | (WP_TLDR << WPSHIFT))
222 #define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \
223 | (WP_TTGR << WPSHIFT))
225 #define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \
226 | (WP_NONE << WPSHIFT))
228 #define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \
229 | (WP_TMAR << WPSHIFT))
231 #define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \
232 | (WP_NONE << WPSHIFT))
234 #define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \
235 | (WP_NONE << WPSHIFT))
237 #define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \
238 | (WP_NONE << WPSHIFT))
240 #define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \
241 | (WP_TPIR << WPSHIFT))
243 #define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \
244 | (WP_TNIR << WPSHIFT))
246 #define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \
247 | (WP_TCVR << WPSHIFT))
249 #define OMAP_TIMER_TICK_INT_MASK_SET_REG \
250 (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
252 #define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
253 (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
255 struct omap_dm_timer {
256 unsigned long phys_base;
259 struct clk *iclk, *fclk;
261 void __iomem *io_base;
262 void __iomem *sys_stat; /* TISTAT timer status */
263 void __iomem *irq_stat; /* TISR/IRQSTATUS interrupt status */
264 void __iomem *irq_ena; /* irq enable */
265 void __iomem *irq_dis; /* irq disable, only on v2 ip */
266 void __iomem *pend; /* write pending */
267 void __iomem *func_base; /* function register base */
272 struct timer_regs context;
276 struct platform_device *pdev;
277 struct list_head node;
279 int (*get_context_loss_count)(struct device *dev);
282 int omap_dm_timer_prepare(struct omap_dm_timer *timer);
284 static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg,
288 while (__raw_readl(timer->pend) & (reg >> WPSHIFT))
291 return __raw_readl(timer->func_base + (reg & 0xff));
294 static inline void __omap_dm_timer_write(struct omap_dm_timer *timer,
295 u32 reg, u32 val, int posted)
298 while (__raw_readl(timer->pend) & (reg >> WPSHIFT))
301 __raw_writel(val, timer->func_base + (reg & 0xff));
304 static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
308 /* Assume v1 ip if bits [31:16] are zero */
309 tidr = __raw_readl(timer->io_base);
312 timer->sys_stat = timer->io_base +
313 OMAP_TIMER_V1_SYS_STAT_OFFSET;
314 timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET;
315 timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
317 timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET;
318 timer->func_base = timer->io_base;
322 timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS;
323 timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET;
324 timer->irq_dis = timer->io_base + OMAP_TIMER_V2_IRQENABLE_CLR;
325 timer->pend = timer->io_base +
326 _OMAP_TIMER_WRITE_PEND_OFFSET +
327 OMAP_TIMER_V2_FUNC_OFFSET;
328 timer->func_base = timer->io_base + OMAP_TIMER_V2_FUNC_OFFSET;
332 /* Assumes the source clock has been set by caller */
333 static inline void __omap_dm_timer_reset(struct omap_dm_timer *timer,
334 int autoidle, int wakeup)
338 l = __raw_readl(timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET);
339 l |= 0x02 << 3; /* Set to smart-idle mode */
340 l |= 0x2 << 8; /* Set clock activity to perserve f-clock on idle */
348 __raw_writel(l, timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET);
350 /* Match hardware reset default of posted mode */
351 __omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG,
352 OMAP_TIMER_CTRL_POSTED, 0);
355 static inline int __omap_dm_timer_set_source(struct clk *timer_fck,
360 clk_disable(timer_fck);
361 ret = clk_set_parent(timer_fck, parent);
362 clk_enable(timer_fck);
365 * When the functional clock disappears, too quick writes seem
366 * to cause an abort. XXX Is this still necessary?
373 static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer,
374 int posted, unsigned long rate)
378 l = __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
379 if (l & OMAP_TIMER_CTRL_ST) {
381 __omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, l, posted);
382 #ifdef CONFIG_ARCH_OMAP2PLUS
383 /* Readback to make sure write has completed */
384 __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
386 * Wait for functional clock period x 3.5 to make sure that
389 udelay(3500000 / rate + 1);
393 /* Ack possibly pending interrupt */
394 __raw_writel(OMAP_TIMER_INT_OVERFLOW, timer->irq_stat);
397 static inline void __omap_dm_timer_load_start(struct omap_dm_timer *timer,
398 u32 ctrl, unsigned int load,
401 __omap_dm_timer_write(timer, OMAP_TIMER_COUNTER_REG, load, posted);
402 __omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, ctrl, posted);
405 static inline void __omap_dm_timer_int_enable(struct omap_dm_timer *timer,
408 __raw_writel(value, timer->irq_ena);
409 __omap_dm_timer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value, 0);
412 static inline unsigned int
413 __omap_dm_timer_read_counter(struct omap_dm_timer *timer, int posted)
415 return __omap_dm_timer_read(timer, OMAP_TIMER_COUNTER_REG, posted);
418 static inline void __omap_dm_timer_write_status(struct omap_dm_timer *timer,
421 __raw_writel(value, timer->irq_stat);
424 #endif /* __ASM_ARCH_DMTIMER_H */