arch/arm/plat-omap/include/mach/mcbsp.h

   1 /*
   2  * arch/arm/plat-omap/include/mach/mcbsp.h
   3  *
   4  * Defines for Multi-Channel Buffered Serial Port
   5  *
   6  * Copyright (C) 2002 RidgeRun, Inc.
   7  * Author: Steve Johnson
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  22  *
  23  */
  24 #ifndef __ASM_ARCH_OMAP_MCBSP_H
  25 #define __ASM_ARCH_OMAP_MCBSP_H
  26
  27 #include <linux/completion.h>
  28 #include <linux/spinlock.h>
  29
  30 #include <mach/hardware.h>
  31 #include <mach/clock.h>
  32
  33 #define OMAP730_MCBSP1_BASE     0xfffb1000
  34 #define OMAP730_MCBSP2_BASE     0xfffb1800
  35
  36 #define OMAP1510_MCBSP1_BASE    0xe1011800
  37 #define OMAP1510_MCBSP2_BASE    0xfffb1000
  38 #define OMAP1510_MCBSP3_BASE    0xe1017000
  39
  40 #define OMAP1610_MCBSP1_BASE    0xe1011800
  41 #define OMAP1610_MCBSP2_BASE    0xfffb1000
  42 #define OMAP1610_MCBSP3_BASE    0xe1017000
  43
  44 #define OMAP24XX_MCBSP1_BASE    0x48074000
  45 #define OMAP24XX_MCBSP2_BASE    0x48076000
  46 #define OMAP2430_MCBSP3_BASE    0x4808c000
  47 #define OMAP2430_MCBSP4_BASE    0x4808e000
  48 #define OMAP2430_MCBSP5_BASE    0x48096000
  49
  50 #define OMAP34XX_MCBSP1_BASE    0x48074000
  51 #define OMAP34XX_MCBSP2_BASE    0x49022000
  52 #define OMAP34XX_MCBSP3_BASE    0x49024000
  53 #define OMAP34XX_MCBSP4_BASE    0x49026000
  54 #define OMAP34XX_MCBSP5_BASE    0x48096000
  55
  56 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730)
  57
  58 #define OMAP_MCBSP_REG_DRR2     0x00
  59 #define OMAP_MCBSP_REG_DRR1     0x02
  60 #define OMAP_MCBSP_REG_DXR2     0x04
  61 #define OMAP_MCBSP_REG_DXR1     0x06
  62 #define OMAP_MCBSP_REG_SPCR2    0x08
  63 #define OMAP_MCBSP_REG_SPCR1    0x0a
  64 #define OMAP_MCBSP_REG_RCR2     0x0c
  65 #define OMAP_MCBSP_REG_RCR1     0x0e
  66 #define OMAP_MCBSP_REG_XCR2     0x10
  67 #define OMAP_MCBSP_REG_XCR1     0x12
  68 #define OMAP_MCBSP_REG_SRGR2    0x14
  69 #define OMAP_MCBSP_REG_SRGR1    0x16
  70 #define OMAP_MCBSP_REG_MCR2     0x18
  71 #define OMAP_MCBSP_REG_MCR1     0x1a
  72 #define OMAP_MCBSP_REG_RCERA    0x1c
  73 #define OMAP_MCBSP_REG_RCERB    0x1e
  74 #define OMAP_MCBSP_REG_XCERA    0x20
  75 #define OMAP_MCBSP_REG_XCERB    0x22
  76 #define OMAP_MCBSP_REG_PCR0     0x24
  77 #define OMAP_MCBSP_REG_RCERC    0x26
  78 #define OMAP_MCBSP_REG_RCERD    0x28
  79 #define OMAP_MCBSP_REG_XCERC    0x2A
  80 #define OMAP_MCBSP_REG_XCERD    0x2C
  81 #define OMAP_MCBSP_REG_RCERE    0x2E
  82 #define OMAP_MCBSP_REG_RCERF    0x30
  83 #define OMAP_MCBSP_REG_XCERE    0x32
  84 #define OMAP_MCBSP_REG_XCERF    0x34
  85 #define OMAP_MCBSP_REG_RCERG    0x36
  86 #define OMAP_MCBSP_REG_RCERH    0x38
  87 #define OMAP_MCBSP_REG_XCERG    0x3A
  88 #define OMAP_MCBSP_REG_XCERH    0x3C
  89
  90 /* Dummy defines, these are not available on omap1 */
  91 #define OMAP_MCBSP_REG_XCCR     0x00
  92 #define OMAP_MCBSP_REG_RCCR     0x00
  93
  94 #define AUDIO_MCBSP_DATAWRITE   (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1)
  95 #define AUDIO_MCBSP_DATAREAD    (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1)
  96
  97 #define AUDIO_MCBSP             OMAP_MCBSP1
  98 #define AUDIO_DMA_TX            OMAP_DMA_MCBSP1_TX
  99 #define AUDIO_DMA_RX            OMAP_DMA_MCBSP1_RX
 100
 101 #elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
 102
 103 #define OMAP_MCBSP_REG_DRR2     0x00
 104 #define OMAP_MCBSP_REG_DRR1     0x04
 105 #define OMAP_MCBSP_REG_DXR2     0x08
 106 #define OMAP_MCBSP_REG_DXR1     0x0C
 107 #define OMAP_MCBSP_REG_DRR      0x00
 108 #define OMAP_MCBSP_REG_DXR      0x08
 109 #define OMAP_MCBSP_REG_SPCR2    0x10
 110 #define OMAP_MCBSP_REG_SPCR1    0x14
 111 #define OMAP_MCBSP_REG_RCR2     0x18
 112 #define OMAP_MCBSP_REG_RCR1     0x1C
 113 #define OMAP_MCBSP_REG_XCR2     0x20
 114 #define OMAP_MCBSP_REG_XCR1     0x24
 115 #define OMAP_MCBSP_REG_SRGR2    0x28
 116 #define OMAP_MCBSP_REG_SRGR1    0x2C
 117 #define OMAP_MCBSP_REG_MCR2     0x30
 118 #define OMAP_MCBSP_REG_MCR1     0x34
 119 #define OMAP_MCBSP_REG_RCERA    0x38
 120 #define OMAP_MCBSP_REG_RCERB    0x3C
 121 #define OMAP_MCBSP_REG_XCERA    0x40
 122 #define OMAP_MCBSP_REG_XCERB    0x44
 123 #define OMAP_MCBSP_REG_PCR0     0x48
 124 #define OMAP_MCBSP_REG_RCERC    0x4C
 125 #define OMAP_MCBSP_REG_RCERD    0x50
 126 #define OMAP_MCBSP_REG_XCERC    0x54
 127 #define OMAP_MCBSP_REG_XCERD    0x58
 128 #define OMAP_MCBSP_REG_RCERE    0x5C
 129 #define OMAP_MCBSP_REG_RCERF    0x60
 130 #define OMAP_MCBSP_REG_XCERE    0x64
 131 #define OMAP_MCBSP_REG_XCERF    0x68
 132 #define OMAP_MCBSP_REG_RCERG    0x6C
 133 #define OMAP_MCBSP_REG_RCERH    0x70
 134 #define OMAP_MCBSP_REG_XCERG    0x74
 135 #define OMAP_MCBSP_REG_XCERH    0x78
 136 #define OMAP_MCBSP_REG_SYSCON   0x8C
 137 #define OMAP_MCBSP_REG_XCCR     0xAC
 138 #define OMAP_MCBSP_REG_RCCR     0xB0
 139
 140 #define AUDIO_MCBSP_DATAWRITE   (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)
 141 #define AUDIO_MCBSP_DATAREAD    (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)
 142
 143 #define AUDIO_MCBSP             OMAP_MCBSP2
 144 #define AUDIO_DMA_TX            OMAP24XX_DMA_MCBSP2_TX
 145 #define AUDIO_DMA_RX            OMAP24XX_DMA_MCBSP2_RX
 146
 147 #endif
 148
 149 /************************** McBSP SPCR1 bit definitions ***********************/
 150 #define RRST                    0x0001
 151 #define RRDY                    0x0002
 152 #define RFULL                   0x0004
 153 #define RSYNC_ERR               0x0008
 154 #define RINTM(value)            ((value)<<4)    /* bits 4:5 */
 155 #define ABIS                    0x0040
 156 #define DXENA                   0x0080
 157 #define CLKSTP(value)           ((value)<<11)   /* bits 11:12 */
 158 #define RJUST(value)            ((value)<<13)   /* bits 13:14 */
 159 #define ALB                     0x8000
 160 #define DLB                     0x8000
 161
 162 /************************** McBSP SPCR2 bit definitions ***********************/
 163 #define XRST            0x0001
 164 #define XRDY            0x0002
 165 #define XEMPTY          0x0004
 166 #define XSYNC_ERR       0x0008
 167 #define XINTM(value)    ((value)<<4)            /* bits 4:5 */
 168 #define GRST            0x0040
 169 #define FRST            0x0080
 170 #define SOFT            0x0100
 171 #define FREE            0x0200
 172
 173 /************************** McBSP PCR bit definitions *************************/
 174 #define CLKRP           0x0001
 175 #define CLKXP           0x0002
 176 #define FSRP            0x0004
 177 #define FSXP            0x0008
 178 #define DR_STAT         0x0010
 179 #define DX_STAT         0x0020
 180 #define CLKS_STAT       0x0040
 181 #define SCLKME          0x0080
 182 #define CLKRM           0x0100
 183 #define CLKXM           0x0200
 184 #define FSRM            0x0400
 185 #define FSXM            0x0800
 186 #define RIOEN           0x1000
 187 #define XIOEN           0x2000
 188 #define IDLE_EN         0x4000
 189
 190 /************************** McBSP RCR1 bit definitions ************************/
 191 #define RWDLEN1(value)          ((value)<<5)    /* Bits 5:7 */
 192 #define RFRLEN1(value)          ((value)<<8)    /* Bits 8:14 */
 193
 194 /************************** McBSP XCR1 bit definitions ************************/
 195 #define XWDLEN1(value)          ((value)<<5)    /* Bits 5:7 */
 196 #define XFRLEN1(value)          ((value)<<8)    /* Bits 8:14 */
 197
 198 /*************************** McBSP RCR2 bit definitions ***********************/
 199 #define RDATDLY(value)          (value)         /* Bits 0:1 */
 200 #define RFIG                    0x0004
 201 #define RCOMPAND(value)         ((value)<<3)    /* Bits 3:4 */
 202 #define RWDLEN2(value)          ((value)<<5)    /* Bits 5:7 */
 203 #define RFRLEN2(value)          ((value)<<8)    /* Bits 8:14 */
 204 #define RPHASE                  0x8000
 205
 206 /*************************** McBSP XCR2 bit definitions ***********************/
 207 #define XDATDLY(value)          (value)         /* Bits 0:1 */
 208 #define XFIG                    0x0004
 209 #define XCOMPAND(value)         ((value)<<3)    /* Bits 3:4 */
 210 #define XWDLEN2(value)          ((value)<<5)    /* Bits 5:7 */
 211 #define XFRLEN2(value)          ((value)<<8)    /* Bits 8:14 */
 212 #define XPHASE                  0x8000
 213
 214 /************************* McBSP SRGR1 bit definitions ************************/
 215 #define CLKGDV(value)           (value)         /* Bits 0:7 */
 216 #define FWID(value)             ((value)<<8)    /* Bits 8:15 */
 217
 218 /************************* McBSP SRGR2 bit definitions ************************/
 219 #define FPER(value)             (value)         /* Bits 0:11 */
 220 #define FSGM                    0x1000
 221 #define CLKSM                   0x2000
 222 #define CLKSP                   0x4000
 223 #define GSYNC                   0x8000
 224
 225 /************************* McBSP MCR1 bit definitions *************************/
 226 #define RMCM                    0x0001
 227 #define RCBLK(value)            ((value)<<2)    /* Bits 2:4 */
 228 #define RPABLK(value)           ((value)<<5)    /* Bits 5:6 */
 229 #define RPBBLK(value)           ((value)<<7)    /* Bits 7:8 */
 230
 231 /************************* McBSP MCR2 bit definitions *************************/
 232 #define XMCM(value)             (value)         /* Bits 0:1 */
 233 #define XCBLK(value)            ((value)<<2)    /* Bits 2:4 */
 234 #define XPABLK(value)           ((value)<<5)    /* Bits 5:6 */
 235 #define XPBBLK(value)           ((value)<<7)    /* Bits 7:8 */
 236
 237 /*********************** McBSP XCCR bit definitions *************************/
 238 #define EXTCLKGATE              0x8000
 239 #define PPCONNECT               0x4000
 240 #define DXENDLY(value)          ((value)<<12)   /* Bits 12:13 */
 241 #define XFULL_CYCLE             0x0800
 242 #define DILB                    0x0020
 243 #define XDMAEN                  0x0008
 244 #define XDISABLE                0x0001
 245
 246 /********************** McBSP RCCR bit definitions *************************/
 247 #define RFULL_CYCLE             0x0800
 248 #define RDMAEN                  0x0008
 249 #define RDISABLE                0x0001
 250
 251 /********************** McBSP SYSCONFIG bit definitions ********************/
 252 #define SOFTRST                 0x0002
 253
 254 /* we don't do multichannel for now */
 255 struct omap_mcbsp_reg_cfg {
 256         u16 spcr2;
 257         u16 spcr1;
 258         u16 rcr2;
 259         u16 rcr1;
 260         u16 xcr2;
 261         u16 xcr1;
 262         u16 srgr2;
 263         u16 srgr1;
 264         u16 mcr2;
 265         u16 mcr1;
 266         u16 pcr0;
 267         u16 rcerc;
 268         u16 rcerd;
 269         u16 xcerc;
 270         u16 xcerd;
 271         u16 rcere;
 272         u16 rcerf;
 273         u16 xcere;
 274         u16 xcerf;
 275         u16 rcerg;
 276         u16 rcerh;
 277         u16 xcerg;
 278         u16 xcerh;
 279         u16 xccr;
 280         u16 rccr;
 281 };
 282
 283 typedef enum {
 284         OMAP_MCBSP1 = 0,
 285         OMAP_MCBSP2,
 286         OMAP_MCBSP3,
 287         OMAP_MCBSP4,
 288         OMAP_MCBSP5
 289 } omap_mcbsp_id;
 290
 291 typedef int __bitwise omap_mcbsp_io_type_t;
 292 #define OMAP_MCBSP_IRQ_IO ((__force omap_mcbsp_io_type_t) 1)
 293 #define OMAP_MCBSP_POLL_IO ((__force omap_mcbsp_io_type_t) 2)
 294
 295 typedef enum {
 296         OMAP_MCBSP_WORD_8 = 0,
 297         OMAP_MCBSP_WORD_12,
 298         OMAP_MCBSP_WORD_16,
 299         OMAP_MCBSP_WORD_20,
 300         OMAP_MCBSP_WORD_24,
 301         OMAP_MCBSP_WORD_32,
 302 } omap_mcbsp_word_length;
 303
 304 typedef enum {
 305         OMAP_MCBSP_CLK_RISING = 0,
 306         OMAP_MCBSP_CLK_FALLING,
 307 } omap_mcbsp_clk_polarity;
 308
 309 typedef enum {
 310         OMAP_MCBSP_FS_ACTIVE_HIGH = 0,
 311         OMAP_MCBSP_FS_ACTIVE_LOW,
 312 } omap_mcbsp_fs_polarity;
 313
 314 typedef enum {
 315         OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0,
 316         OMAP_MCBSP_CLK_STP_MODE_DELAY,
 317 } omap_mcbsp_clk_stp_mode;
 318
 319
 320 /******* SPI specific mode **********/
 321 typedef enum {
 322         OMAP_MCBSP_SPI_MASTER = 0,
 323         OMAP_MCBSP_SPI_SLAVE,
 324 } omap_mcbsp_spi_mode;
 325
 326 struct omap_mcbsp_spi_cfg {
 327         omap_mcbsp_spi_mode             spi_mode;
 328         omap_mcbsp_clk_polarity         rx_clock_polarity;
 329         omap_mcbsp_clk_polarity         tx_clock_polarity;
 330         omap_mcbsp_fs_polarity          fsx_polarity;
 331         u8                              clk_div;
 332         omap_mcbsp_clk_stp_mode         clk_stp_mode;
 333         omap_mcbsp_word_length          word_length;
 334 };
 335
 336 /* Platform specific configuration */
 337 struct omap_mcbsp_ops {
 338         void (*request)(unsigned int);
 339         void (*free)(unsigned int);
 340 };
 341
 342 struct omap_mcbsp_platform_data {
 343         unsigned long phys_base;
 344         u8 dma_rx_sync, dma_tx_sync;
 345         u16 rx_irq, tx_irq;
 346         struct omap_mcbsp_ops *ops;
 347 };
 348
 349 struct omap_mcbsp {
 350         struct device *dev;
 351         unsigned long phys_base;
 352         void __iomem *io_base;
 353         u8 id;
 354         u8 free;
 355         omap_mcbsp_word_length rx_word_length;
 356         omap_mcbsp_word_length tx_word_length;
 357
 358         omap_mcbsp_io_type_t io_type; /* IRQ or poll */
 359         /* IRQ based TX/RX */
 360         int rx_irq;
 361         int tx_irq;
 362
 363         /* DMA stuff */
 364         u8 dma_rx_sync;
 365         short dma_rx_lch;
 366         u8 dma_tx_sync;
 367         short dma_tx_lch;
 368
 369         /* Completion queues */
 370         struct completion tx_irq_completion;
 371         struct completion rx_irq_completion;
 372         struct completion tx_dma_completion;
 373         struct completion rx_dma_completion;
 374
 375         /* Protect the field .free, while checking if the mcbsp is in use */
 376         spinlock_t lock;
 377         struct omap_mcbsp_platform_data *pdata;
 378         struct clk *iclk;
 379         struct clk *fclk;
 380 };
 381 extern struct omap_mcbsp **mcbsp_ptr;
 382 extern int omap_mcbsp_count;
 383
 384 int omap_mcbsp_init(void);
 385 void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
 386                                         int size);
 387 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
 388 int omap_mcbsp_request(unsigned int id);
 389 void omap_mcbsp_free(unsigned int id);
 390 void omap_mcbsp_start(unsigned int id);
 391 void omap_mcbsp_stop(unsigned int id);
 392 void omap_mcbsp_xmit_word(unsigned int id, u32 word);
 393 u32 omap_mcbsp_recv_word(unsigned int id);
 394
 395 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
 396 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
 397 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word);
 398 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word);
 399
 400
 401 /* SPI specific API */
 402 void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);
 403
 404 /* Polled read/write functions */
 405 int omap_mcbsp_pollread(unsigned int id, u16 * buf);
 406 int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
 407 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);
 408
 409 #endif