arch/arm/plat-omap/include/mach/mcbsp.h

   1 /*
   2  * arch/arm/plat-omap/include/mach/mcbsp.h
   3  *
   4  * Defines for Multi-Channel Buffered Serial Port
   5  *
   6  * Copyright (C) 2002 RidgeRun, Inc.
   7  * Author: Steve Johnson
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  22  *
  23  */
  24 #ifndef __ASM_ARCH_OMAP_MCBSP_H
  25 #define __ASM_ARCH_OMAP_MCBSP_H
  26
  27 #include <linux/completion.h>
  28 #include <linux/spinlock.h>
  29
  30 #include <mach/hardware.h>
  31 #include <mach/clock.h>
  32
  33 #define OMAP730_MCBSP1_BASE     0xfffb1000
  34 #define OMAP730_MCBSP2_BASE     0xfffb1800
  35
  36 #define OMAP1510_MCBSP1_BASE    0xe1011800
  37 #define OMAP1510_MCBSP2_BASE    0xfffb1000
  38 #define OMAP1510_MCBSP3_BASE    0xe1017000
  39
  40 #define OMAP1610_MCBSP1_BASE    0xe1011800
  41 #define OMAP1610_MCBSP2_BASE    0xfffb1000
  42 #define OMAP1610_MCBSP3_BASE    0xe1017000
  43
  44 #define OMAP24XX_MCBSP1_BASE    0x48074000
  45 #define OMAP24XX_MCBSP2_BASE    0x48076000
  46 #define OMAP2430_MCBSP3_BASE    0x4808c000
  47 #define OMAP2430_MCBSP4_BASE    0x4808e000
  48 #define OMAP2430_MCBSP5_BASE    0x48096000
  49
  50 #define OMAP34XX_MCBSP1_BASE    0x48074000
  51 #define OMAP34XX_MCBSP2_BASE    0x49022000
  52 #define OMAP34XX_MCBSP3_BASE    0x49024000
  53 #define OMAP34XX_MCBSP4_BASE    0x49026000
  54 #define OMAP34XX_MCBSP5_BASE    0x48096000
  55
  56 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730)
  57
  58 #define OMAP_MCBSP_REG_DRR2     0x00
  59 #define OMAP_MCBSP_REG_DRR1     0x02
  60 #define OMAP_MCBSP_REG_DXR2     0x04
  61 #define OMAP_MCBSP_REG_DXR1     0x06
  62 #define OMAP_MCBSP_REG_SPCR2    0x08
  63 #define OMAP_MCBSP_REG_SPCR1    0x0a
  64 #define OMAP_MCBSP_REG_RCR2     0x0c
  65 #define OMAP_MCBSP_REG_RCR1     0x0e
  66 #define OMAP_MCBSP_REG_XCR2     0x10
  67 #define OMAP_MCBSP_REG_XCR1     0x12
  68 #define OMAP_MCBSP_REG_SRGR2    0x14
  69 #define OMAP_MCBSP_REG_SRGR1    0x16
  70 #define OMAP_MCBSP_REG_MCR2     0x18
  71 #define OMAP_MCBSP_REG_MCR1     0x1a
  72 #define OMAP_MCBSP_REG_RCERA    0x1c
  73 #define OMAP_MCBSP_REG_RCERB    0x1e
  74 #define OMAP_MCBSP_REG_XCERA    0x20
  75 #define OMAP_MCBSP_REG_XCERB    0x22
  76 #define OMAP_MCBSP_REG_PCR0     0x24
  77 #define OMAP_MCBSP_REG_RCERC    0x26
  78 #define OMAP_MCBSP_REG_RCERD    0x28
  79 #define OMAP_MCBSP_REG_XCERC    0x2A
  80 #define OMAP_MCBSP_REG_XCERD    0x2C
  81 #define OMAP_MCBSP_REG_RCERE    0x2E
  82 #define OMAP_MCBSP_REG_RCERF    0x30
  83 #define OMAP_MCBSP_REG_XCERE    0x32
  84 #define OMAP_MCBSP_REG_XCERF    0x34
  85 #define OMAP_MCBSP_REG_RCERG    0x36
  86 #define OMAP_MCBSP_REG_RCERH    0x38
  87 #define OMAP_MCBSP_REG_XCERG    0x3A
  88 #define OMAP_MCBSP_REG_XCERH    0x3C
  89
  90 /* Dummy defines, these are not available on omap1 */
  91 #define OMAP_MCBSP_REG_XCCR     0x00
  92 #define OMAP_MCBSP_REG_RCCR     0x00
  93
  94 #define AUDIO_MCBSP_DATAWRITE   (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1)
  95 #define AUDIO_MCBSP_DATAREAD    (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1)
  96
  97 #define AUDIO_MCBSP             OMAP_MCBSP1
  98 #define AUDIO_DMA_TX            OMAP_DMA_MCBSP1_TX
  99 #define AUDIO_DMA_RX            OMAP_DMA_MCBSP1_RX
 100
 101 #elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
 102
 103 #define OMAP_MCBSP_REG_DRR2     0x00
 104 #define OMAP_MCBSP_REG_DRR1     0x04
 105 #define OMAP_MCBSP_REG_DXR2     0x08
 106 #define OMAP_MCBSP_REG_DXR1     0x0C
 107 #define OMAP_MCBSP_REG_DRR      0x00
 108 #define OMAP_MCBSP_REG_DXR      0x08
 109 #define OMAP_MCBSP_REG_SPCR2    0x10
 110 #define OMAP_MCBSP_REG_SPCR1    0x14
 111 #define OMAP_MCBSP_REG_RCR2     0x18
 112 #define OMAP_MCBSP_REG_RCR1     0x1C
 113 #define OMAP_MCBSP_REG_XCR2     0x20
 114 #define OMAP_MCBSP_REG_XCR1     0x24
 115 #define OMAP_MCBSP_REG_SRGR2    0x28
 116 #define OMAP_MCBSP_REG_SRGR1    0x2C
 117 #define OMAP_MCBSP_REG_MCR2     0x30
 118 #define OMAP_MCBSP_REG_MCR1     0x34
 119 #define OMAP_MCBSP_REG_RCERA    0x38
 120 #define OMAP_MCBSP_REG_RCERB    0x3C
 121 #define OMAP_MCBSP_REG_XCERA    0x40
 122 #define OMAP_MCBSP_REG_XCERB    0x44
 123 #define OMAP_MCBSP_REG_PCR0     0x48
 124 #define OMAP_MCBSP_REG_RCERC    0x4C
 125 #define OMAP_MCBSP_REG_RCERD    0x50
 126 #define OMAP_MCBSP_REG_XCERC    0x54
 127 #define OMAP_MCBSP_REG_XCERD    0x58
 128 #define OMAP_MCBSP_REG_RCERE    0x5C
 129 #define OMAP_MCBSP_REG_RCERF    0x60
 130 #define OMAP_MCBSP_REG_XCERE    0x64
 131 #define OMAP_MCBSP_REG_XCERF    0x68
 132 #define OMAP_MCBSP_REG_RCERG    0x6C
 133 #define OMAP_MCBSP_REG_RCERH    0x70
 134 #define OMAP_MCBSP_REG_XCERG    0x74
 135 #define OMAP_MCBSP_REG_XCERH    0x78
 136 #define OMAP_MCBSP_REG_SYSCON   0x8C
 137 #define OMAP_MCBSP_REG_THRSH2   0x90
 138 #define OMAP_MCBSP_REG_THRSH1   0x94
 139 #define OMAP_MCBSP_REG_IRQST    0xA0
 140 #define OMAP_MCBSP_REG_IRQEN    0xA4
 141 #define OMAP_MCBSP_REG_WAKEUPEN 0xA8
 142 #define OMAP_MCBSP_REG_XCCR     0xAC
 143 #define OMAP_MCBSP_REG_RCCR     0xB0
 144
 145 #define AUDIO_MCBSP_DATAWRITE   (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)
 146 #define AUDIO_MCBSP_DATAREAD    (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)
 147
 148 #define AUDIO_MCBSP             OMAP_MCBSP2
 149 #define AUDIO_DMA_TX            OMAP24XX_DMA_MCBSP2_TX
 150 #define AUDIO_DMA_RX            OMAP24XX_DMA_MCBSP2_RX
 151
 152 #endif
 153
 154 /************************** McBSP SPCR1 bit definitions ***********************/
 155 #define RRST                    0x0001
 156 #define RRDY                    0x0002
 157 #define RFULL                   0x0004
 158 #define RSYNC_ERR               0x0008
 159 #define RINTM(value)            ((value)<<4)    /* bits 4:5 */
 160 #define ABIS                    0x0040
 161 #define DXENA                   0x0080
 162 #define CLKSTP(value)           ((value)<<11)   /* bits 11:12 */
 163 #define RJUST(value)            ((value)<<13)   /* bits 13:14 */
 164 #define ALB                     0x8000
 165 #define DLB                     0x8000
 166
 167 /************************** McBSP SPCR2 bit definitions ***********************/
 168 #define XRST            0x0001
 169 #define XRDY            0x0002
 170 #define XEMPTY          0x0004
 171 #define XSYNC_ERR       0x0008
 172 #define XINTM(value)    ((value)<<4)            /* bits 4:5 */
 173 #define GRST            0x0040
 174 #define FRST            0x0080
 175 #define SOFT            0x0100
 176 #define FREE            0x0200
 177
 178 /************************** McBSP PCR bit definitions *************************/
 179 #define CLKRP           0x0001
 180 #define CLKXP           0x0002
 181 #define FSRP            0x0004
 182 #define FSXP            0x0008
 183 #define DR_STAT         0x0010
 184 #define DX_STAT         0x0020
 185 #define CLKS_STAT       0x0040
 186 #define SCLKME          0x0080
 187 #define CLKRM           0x0100
 188 #define CLKXM           0x0200
 189 #define FSRM            0x0400
 190 #define FSXM            0x0800
 191 #define RIOEN           0x1000
 192 #define XIOEN           0x2000
 193 #define IDLE_EN         0x4000
 194
 195 /************************** McBSP RCR1 bit definitions ************************/
 196 #define RWDLEN1(value)          ((value)<<5)    /* Bits 5:7 */
 197 #define RFRLEN1(value)          ((value)<<8)    /* Bits 8:14 */
 198
 199 /************************** McBSP XCR1 bit definitions ************************/
 200 #define XWDLEN1(value)          ((value)<<5)    /* Bits 5:7 */
 201 #define XFRLEN1(value)          ((value)<<8)    /* Bits 8:14 */
 202
 203 /*************************** McBSP RCR2 bit definitions ***********************/
 204 #define RDATDLY(value)          (value)         /* Bits 0:1 */
 205 #define RFIG                    0x0004
 206 #define RCOMPAND(value)         ((value)<<3)    /* Bits 3:4 */
 207 #define RWDLEN2(value)          ((value)<<5)    /* Bits 5:7 */
 208 #define RFRLEN2(value)          ((value)<<8)    /* Bits 8:14 */
 209 #define RPHASE                  0x8000
 210
 211 /*************************** McBSP XCR2 bit definitions ***********************/
 212 #define XDATDLY(value)          (value)         /* Bits 0:1 */
 213 #define XFIG                    0x0004
 214 #define XCOMPAND(value)         ((value)<<3)    /* Bits 3:4 */
 215 #define XWDLEN2(value)          ((value)<<5)    /* Bits 5:7 */
 216 #define XFRLEN2(value)          ((value)<<8)    /* Bits 8:14 */
 217 #define XPHASE                  0x8000
 218
 219 /************************* McBSP SRGR1 bit definitions ************************/
 220 #define CLKGDV(value)           (value)         /* Bits 0:7 */
 221 #define FWID(value)             ((value)<<8)    /* Bits 8:15 */
 222
 223 /************************* McBSP SRGR2 bit definitions ************************/
 224 #define FPER(value)             (value)         /* Bits 0:11 */
 225 #define FSGM                    0x1000
 226 #define CLKSM                   0x2000
 227 #define CLKSP                   0x4000
 228 #define GSYNC                   0x8000
 229
 230 /************************* McBSP MCR1 bit definitions *************************/
 231 #define RMCM                    0x0001
 232 #define RCBLK(value)            ((value)<<2)    /* Bits 2:4 */
 233 #define RPABLK(value)           ((value)<<5)    /* Bits 5:6 */
 234 #define RPBBLK(value)           ((value)<<7)    /* Bits 7:8 */
 235
 236 /************************* McBSP MCR2 bit definitions *************************/
 237 #define XMCM(value)             (value)         /* Bits 0:1 */
 238 #define XCBLK(value)            ((value)<<2)    /* Bits 2:4 */
 239 #define XPABLK(value)           ((value)<<5)    /* Bits 5:6 */
 240 #define XPBBLK(value)           ((value)<<7)    /* Bits 7:8 */
 241
 242 /*********************** McBSP XCCR bit definitions *************************/
 243 #define EXTCLKGATE              0x8000
 244 #define PPCONNECT               0x4000
 245 #define DXENDLY(value)          ((value)<<12)   /* Bits 12:13 */
 246 #define XFULL_CYCLE             0x0800
 247 #define DILB                    0x0020
 248 #define XDMAEN                  0x0008
 249 #define XDISABLE                0x0001
 250
 251 /********************** McBSP RCCR bit definitions *************************/
 252 #define RFULL_CYCLE             0x0800
 253 #define RDMAEN                  0x0008
 254 #define RDISABLE                0x0001
 255
 256 /********************** McBSP SYSCONFIG bit definitions ********************/
 257 #define CLOCKACTIVITY(value)    ((value)<<8)
 258 #define SIDLEMODE(value)        ((value)<<3)
 259 #define ENAWAKEUP               0x0004
 260 #define SOFTRST                 0x0002
 261
 262 /********************** McBSP DMA operating modes **************************/
 263 #define MCBSP_DMA_MODE_ELEMENT          0
 264 #define MCBSP_DMA_MODE_THRESHOLD        1
 265 #define MCBSP_DMA_MODE_FRAME            2
 266
 267 /********************** McBSP WAKEUPEN bit definitions *********************/
 268 #define XEMPTYEOFEN             0x4000
 269 #define XRDYEN                  0x0400
 270 #define XEOFEN                  0x0200
 271 #define XFSXEN                  0x0100
 272 #define XSYNCERREN              0x0080
 273 #define RRDYEN                  0x0008
 274 #define REOFEN                  0x0004
 275 #define RFSREN                  0x0002
 276 #define RSYNCERREN              0x0001
 277
 278 /* we don't do multichannel for now */
 279 struct omap_mcbsp_reg_cfg {
 280         u16 spcr2;
 281         u16 spcr1;
 282         u16 rcr2;
 283         u16 rcr1;
 284         u16 xcr2;
 285         u16 xcr1;
 286         u16 srgr2;
 287         u16 srgr1;
 288         u16 mcr2;
 289         u16 mcr1;
 290         u16 pcr0;
 291         u16 rcerc;
 292         u16 rcerd;
 293         u16 xcerc;
 294         u16 xcerd;
 295         u16 rcere;
 296         u16 rcerf;
 297         u16 xcere;
 298         u16 xcerf;
 299         u16 rcerg;
 300         u16 rcerh;
 301         u16 xcerg;
 302         u16 xcerh;
 303         u16 xccr;
 304         u16 rccr;
 305 };
 306
 307 typedef enum {
 308         OMAP_MCBSP1 = 0,
 309         OMAP_MCBSP2,
 310         OMAP_MCBSP3,
 311         OMAP_MCBSP4,
 312         OMAP_MCBSP5
 313 } omap_mcbsp_id;
 314
 315 typedef int __bitwise omap_mcbsp_io_type_t;
 316 #define OMAP_MCBSP_IRQ_IO ((__force omap_mcbsp_io_type_t) 1)
 317 #define OMAP_MCBSP_POLL_IO ((__force omap_mcbsp_io_type_t) 2)
 318
 319 typedef enum {
 320         OMAP_MCBSP_WORD_8 = 0,
 321         OMAP_MCBSP_WORD_12,
 322         OMAP_MCBSP_WORD_16,
 323         OMAP_MCBSP_WORD_20,
 324         OMAP_MCBSP_WORD_24,
 325         OMAP_MCBSP_WORD_32,
 326 } omap_mcbsp_word_length;
 327
 328 typedef enum {
 329         OMAP_MCBSP_CLK_RISING = 0,
 330         OMAP_MCBSP_CLK_FALLING,
 331 } omap_mcbsp_clk_polarity;
 332
 333 typedef enum {
 334         OMAP_MCBSP_FS_ACTIVE_HIGH = 0,
 335         OMAP_MCBSP_FS_ACTIVE_LOW,
 336 } omap_mcbsp_fs_polarity;
 337
 338 typedef enum {
 339         OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0,
 340         OMAP_MCBSP_CLK_STP_MODE_DELAY,
 341 } omap_mcbsp_clk_stp_mode;
 342
 343
 344 /******* SPI specific mode **********/
 345 typedef enum {
 346         OMAP_MCBSP_SPI_MASTER = 0,
 347         OMAP_MCBSP_SPI_SLAVE,
 348 } omap_mcbsp_spi_mode;
 349
 350 struct omap_mcbsp_spi_cfg {
 351         omap_mcbsp_spi_mode             spi_mode;
 352         omap_mcbsp_clk_polarity         rx_clock_polarity;
 353         omap_mcbsp_clk_polarity         tx_clock_polarity;
 354         omap_mcbsp_fs_polarity          fsx_polarity;
 355         u8                              clk_div;
 356         omap_mcbsp_clk_stp_mode         clk_stp_mode;
 357         omap_mcbsp_word_length          word_length;
 358 };
 359
 360 /* Platform specific configuration */
 361 struct omap_mcbsp_ops {
 362         void (*request)(unsigned int);
 363         void (*free)(unsigned int);
 364 };
 365
 366 struct omap_mcbsp_platform_data {
 367         unsigned long phys_base;
 368         u8 dma_rx_sync, dma_tx_sync;
 369         u16 rx_irq, tx_irq;
 370         struct omap_mcbsp_ops *ops;
 371 #ifdef CONFIG_ARCH_OMAP34XX
 372         u16 buffer_size;
 373 #endif
 374 };
 375
 376 struct omap_mcbsp {
 377         struct device *dev;
 378         unsigned long phys_base;
 379         void __iomem *io_base;
 380         u8 id;
 381         u8 free;
 382         omap_mcbsp_word_length rx_word_length;
 383         omap_mcbsp_word_length tx_word_length;
 384
 385         omap_mcbsp_io_type_t io_type; /* IRQ or poll */
 386         /* IRQ based TX/RX */
 387         int rx_irq;
 388         int tx_irq;
 389
 390         /* DMA stuff */
 391         u8 dma_rx_sync;
 392         short dma_rx_lch;
 393         u8 dma_tx_sync;
 394         short dma_tx_lch;
 395
 396         /* Completion queues */
 397         struct completion tx_irq_completion;
 398         struct completion rx_irq_completion;
 399         struct completion tx_dma_completion;
 400         struct completion rx_dma_completion;
 401
 402         /* Protect the field .free, while checking if the mcbsp is in use */
 403         spinlock_t lock;
 404         struct omap_mcbsp_platform_data *pdata;
 405         struct clk *iclk;
 406         struct clk *fclk;
 407 #ifdef CONFIG_ARCH_OMAP34XX
 408         int dma_op_mode;
 409         u16 max_tx_thres;
 410         u16 max_rx_thres;
 411 #endif
 412 };
 413 extern struct omap_mcbsp **mcbsp_ptr;
 414 extern int omap_mcbsp_count;
 415
 416 int omap_mcbsp_init(void);
 417 void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
 418                                         int size);
 419 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
 420 #ifdef CONFIG_ARCH_OMAP34XX
 421 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
 422 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold);
 423 u16 omap_mcbsp_get_max_tx_threshold(unsigned int id);
 424 u16 omap_mcbsp_get_max_rx_threshold(unsigned int id);
 425 int omap_mcbsp_get_dma_op_mode(unsigned int id);
 426 #else
 427 static inline void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
 428 { }
 429 static inline void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
 430 { }
 431 static inline u16 omap_mcbsp_get_max_tx_threshold(unsigned int id) { return 0; }
 432 static inline u16 omap_mcbsp_get_max_rx_threshold(unsigned int id) { return 0; }
 433 static inline int omap_mcbsp_get_dma_op_mode(unsigned int id) { return 0; }
 434 #endif
 435 int omap_mcbsp_request(unsigned int id);
 436 void omap_mcbsp_free(unsigned int id);
 437 void omap_mcbsp_start(unsigned int id, int tx, int rx);
 438 void omap_mcbsp_stop(unsigned int id, int tx, int rx);
 439 void omap_mcbsp_xmit_word(unsigned int id, u32 word);
 440 u32 omap_mcbsp_recv_word(unsigned int id);
 441
 442 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
 443 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
 444 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word);
 445 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word);
 446
 447
 448 /* SPI specific API */
 449 void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);
 450
 451 /* Polled read/write functions */
 452 int omap_mcbsp_pollread(unsigned int id, u16 * buf);
 453 int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
 454 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);
 455
 456 #endif