2 * arch/arm/plat-omap/include/mach/dma.h
4 * Copyright (C) 2003 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #ifndef __ASM_ARCH_DMA_H
22 #define __ASM_ARCH_DMA_H
24 /* Hardware registers for omap1 */
25 #define OMAP1_DMA_BASE (0xfffed800)
27 #define OMAP1_DMA_GCR 0x400
28 #define OMAP1_DMA_GSCR 0x404
29 #define OMAP1_DMA_GRST 0x408
30 #define OMAP1_DMA_HW_ID 0x442
31 #define OMAP1_DMA_PCH2_ID 0x444
32 #define OMAP1_DMA_PCH0_ID 0x446
33 #define OMAP1_DMA_PCH1_ID 0x448
34 #define OMAP1_DMA_PCHG_ID 0x44a
35 #define OMAP1_DMA_PCHD_ID 0x44c
36 #define OMAP1_DMA_CAPS_0_U 0x44e
37 #define OMAP1_DMA_CAPS_0_L 0x450
38 #define OMAP1_DMA_CAPS_1_U 0x452
39 #define OMAP1_DMA_CAPS_1_L 0x454
40 #define OMAP1_DMA_CAPS_2 0x456
41 #define OMAP1_DMA_CAPS_3 0x458
42 #define OMAP1_DMA_CAPS_4 0x45a
43 #define OMAP1_DMA_PCH2_SR 0x460
44 #define OMAP1_DMA_PCH0_SR 0x480
45 #define OMAP1_DMA_PCH1_SR 0x482
46 #define OMAP1_DMA_PCHD_SR 0x4c0
48 /* Hardware registers for omap2 and omap3 */
49 #define OMAP24XX_DMA4_BASE (L4_24XX_BASE + 0x56000)
50 #define OMAP34XX_DMA4_BASE (L4_34XX_BASE + 0x56000)
51 #define OMAP44XX_DMA4_BASE (L4_44XX_BASE + 0x56000)
53 #define OMAP_DMA4_REVISION 0x00
54 #define OMAP_DMA4_GCR 0x78
55 #define OMAP_DMA4_IRQSTATUS_L0 0x08
56 #define OMAP_DMA4_IRQSTATUS_L1 0x0c
57 #define OMAP_DMA4_IRQSTATUS_L2 0x10
58 #define OMAP_DMA4_IRQSTATUS_L3 0x14
59 #define OMAP_DMA4_IRQENABLE_L0 0x18
60 #define OMAP_DMA4_IRQENABLE_L1 0x1c
61 #define OMAP_DMA4_IRQENABLE_L2 0x20
62 #define OMAP_DMA4_IRQENABLE_L3 0x24
63 #define OMAP_DMA4_SYSSTATUS 0x28
64 #define OMAP_DMA4_OCP_SYSCONFIG 0x2c
65 #define OMAP_DMA4_CAPS_0 0x64
66 #define OMAP_DMA4_CAPS_2 0x6c
67 #define OMAP_DMA4_CAPS_3 0x70
68 #define OMAP_DMA4_CAPS_4 0x74
70 #define OMAP1_LOGICAL_DMA_CH_COUNT 17
71 #define OMAP_DMA4_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */
73 /* Common channel specific registers for omap1 */
74 #define OMAP1_DMA_CH_BASE(n) (0x40 * (n) + 0x00)
75 #define OMAP1_DMA_CSDP(n) (0x40 * (n) + 0x00)
76 #define OMAP1_DMA_CCR(n) (0x40 * (n) + 0x02)
77 #define OMAP1_DMA_CICR(n) (0x40 * (n) + 0x04)
78 #define OMAP1_DMA_CSR(n) (0x40 * (n) + 0x06)
79 #define OMAP1_DMA_CEN(n) (0x40 * (n) + 0x10)
80 #define OMAP1_DMA_CFN(n) (0x40 * (n) + 0x12)
81 #define OMAP1_DMA_CSFI(n) (0x40 * (n) + 0x14)
82 #define OMAP1_DMA_CSEI(n) (0x40 * (n) + 0x16)
83 #define OMAP1_DMA_CPC(n) (0x40 * (n) + 0x18) /* 15xx only */
84 #define OMAP1_DMA_CSAC(n) (0x40 * (n) + 0x18)
85 #define OMAP1_DMA_CDAC(n) (0x40 * (n) + 0x1a)
86 #define OMAP1_DMA_CDEI(n) (0x40 * (n) + 0x1c)
87 #define OMAP1_DMA_CDFI(n) (0x40 * (n) + 0x1e)
88 #define OMAP1_DMA_CLNK_CTRL(n) (0x40 * (n) + 0x28)
90 /* Common channel specific registers for omap2 */
91 #define OMAP_DMA4_CH_BASE(n) (0x60 * (n) + 0x80)
92 #define OMAP_DMA4_CCR(n) (0x60 * (n) + 0x80)
93 #define OMAP_DMA4_CLNK_CTRL(n) (0x60 * (n) + 0x84)
94 #define OMAP_DMA4_CICR(n) (0x60 * (n) + 0x88)
95 #define OMAP_DMA4_CSR(n) (0x60 * (n) + 0x8c)
96 #define OMAP_DMA4_CSDP(n) (0x60 * (n) + 0x90)
97 #define OMAP_DMA4_CEN(n) (0x60 * (n) + 0x94)
98 #define OMAP_DMA4_CFN(n) (0x60 * (n) + 0x98)
99 #define OMAP_DMA4_CSEI(n) (0x60 * (n) + 0xa4)
100 #define OMAP_DMA4_CSFI(n) (0x60 * (n) + 0xa8)
101 #define OMAP_DMA4_CDEI(n) (0x60 * (n) + 0xac)
102 #define OMAP_DMA4_CDFI(n) (0x60 * (n) + 0xb0)
103 #define OMAP_DMA4_CSAC(n) (0x60 * (n) + 0xb4)
104 #define OMAP_DMA4_CDAC(n) (0x60 * (n) + 0xb8)
106 /* Channel specific registers only on omap1 */
107 #define OMAP1_DMA_CSSA_L(n) (0x40 * (n) + 0x08)
108 #define OMAP1_DMA_CSSA_U(n) (0x40 * (n) + 0x0a)
109 #define OMAP1_DMA_CDSA_L(n) (0x40 * (n) + 0x0c)
110 #define OMAP1_DMA_CDSA_U(n) (0x40 * (n) + 0x0e)
111 #define OMAP1_DMA_COLOR_L(n) (0x40 * (n) + 0x20)
112 #define OMAP1_DMA_COLOR_U(n) (0x40 * (n) + 0x22)
113 #define OMAP1_DMA_CCR2(n) (0x40 * (n) + 0x24)
114 #define OMAP1_DMA_LCH_CTRL(n) (0x40 * (n) + 0x2a) /* not on 15xx */
115 #define OMAP1_DMA_CCEN(n) 0
116 #define OMAP1_DMA_CCFN(n) 0
118 /* Channel specific registers only on omap2 */
119 #define OMAP_DMA4_CSSA(n) (0x60 * (n) + 0x9c)
120 #define OMAP_DMA4_CDSA(n) (0x60 * (n) + 0xa0)
121 #define OMAP_DMA4_CCEN(n) (0x60 * (n) + 0xbc)
122 #define OMAP_DMA4_CCFN(n) (0x60 * (n) + 0xc0)
123 #define OMAP_DMA4_COLOR(n) (0x60 * (n) + 0xc4)
125 /* Dummy defines to keep multi-omap compiles happy */
126 #define OMAP1_DMA_REVISION 0
127 #define OMAP1_DMA_IRQSTATUS_L0 0
128 #define OMAP1_DMA_IRQENABLE_L0 0
129 #define OMAP1_DMA_OCP_SYSCONFIG 0
130 #define OMAP_DMA4_HW_ID 0
131 #define OMAP_DMA4_CAPS_0_L 0
132 #define OMAP_DMA4_CAPS_0_U 0
133 #define OMAP_DMA4_CAPS_1_L 0
134 #define OMAP_DMA4_CAPS_1_U 0
135 #define OMAP_DMA4_GSCR 0
136 #define OMAP_DMA4_CPC(n) 0
138 #define OMAP_DMA4_LCH_CTRL(n) 0
139 #define OMAP_DMA4_COLOR_L(n) 0
140 #define OMAP_DMA4_COLOR_U(n) 0
141 #define OMAP_DMA4_CCR2(n) 0
142 #define OMAP1_DMA_CSSA(n) 0
143 #define OMAP1_DMA_CDSA(n) 0
144 #define OMAP_DMA4_CSSA_L(n) 0
145 #define OMAP_DMA4_CSSA_U(n) 0
146 #define OMAP_DMA4_CDSA_L(n) 0
147 #define OMAP_DMA4_CDSA_U(n) 0
148 #define OMAP1_DMA_COLOR(n) 0
150 /*----------------------------------------------------------------------------*/
152 /* DMA channels for omap1 */
153 #define OMAP_DMA_NO_DEVICE 0
154 #define OMAP_DMA_MCSI1_TX 1
155 #define OMAP_DMA_MCSI1_RX 2
156 #define OMAP_DMA_I2C_RX 3
157 #define OMAP_DMA_I2C_TX 4
158 #define OMAP_DMA_EXT_NDMA_REQ 5
159 #define OMAP_DMA_EXT_NDMA_REQ2 6
160 #define OMAP_DMA_UWIRE_TX 7
161 #define OMAP_DMA_MCBSP1_TX 8
162 #define OMAP_DMA_MCBSP1_RX 9
163 #define OMAP_DMA_MCBSP3_TX 10
164 #define OMAP_DMA_MCBSP3_RX 11
165 #define OMAP_DMA_UART1_TX 12
166 #define OMAP_DMA_UART1_RX 13
167 #define OMAP_DMA_UART2_TX 14
168 #define OMAP_DMA_UART2_RX 15
169 #define OMAP_DMA_MCBSP2_TX 16
170 #define OMAP_DMA_MCBSP2_RX 17
171 #define OMAP_DMA_UART3_TX 18
172 #define OMAP_DMA_UART3_RX 19
173 #define OMAP_DMA_CAMERA_IF_RX 20
174 #define OMAP_DMA_MMC_TX 21
175 #define OMAP_DMA_MMC_RX 22
176 #define OMAP_DMA_NAND 23
177 #define OMAP_DMA_IRQ_LCD_LINE 24
178 #define OMAP_DMA_MEMORY_STICK 25
179 #define OMAP_DMA_USB_W2FC_RX0 26
180 #define OMAP_DMA_USB_W2FC_RX1 27
181 #define OMAP_DMA_USB_W2FC_RX2 28
182 #define OMAP_DMA_USB_W2FC_TX0 29
183 #define OMAP_DMA_USB_W2FC_TX1 30
184 #define OMAP_DMA_USB_W2FC_TX2 31
186 /* These are only for 1610 */
187 #define OMAP_DMA_CRYPTO_DES_IN 32
188 #define OMAP_DMA_SPI_TX 33
189 #define OMAP_DMA_SPI_RX 34
190 #define OMAP_DMA_CRYPTO_HASH 35
191 #define OMAP_DMA_CCP_ATTN 36
192 #define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37
193 #define OMAP_DMA_CMT_APE_TX_CHAN_0 38
194 #define OMAP_DMA_CMT_APE_RV_CHAN_0 39
195 #define OMAP_DMA_CMT_APE_TX_CHAN_1 40
196 #define OMAP_DMA_CMT_APE_RV_CHAN_1 41
197 #define OMAP_DMA_CMT_APE_TX_CHAN_2 42
198 #define OMAP_DMA_CMT_APE_RV_CHAN_2 43
199 #define OMAP_DMA_CMT_APE_TX_CHAN_3 44
200 #define OMAP_DMA_CMT_APE_RV_CHAN_3 45
201 #define OMAP_DMA_CMT_APE_TX_CHAN_4 46
202 #define OMAP_DMA_CMT_APE_RV_CHAN_4 47
203 #define OMAP_DMA_CMT_APE_TX_CHAN_5 48
204 #define OMAP_DMA_CMT_APE_RV_CHAN_5 49
205 #define OMAP_DMA_CMT_APE_TX_CHAN_6 50
206 #define OMAP_DMA_CMT_APE_RV_CHAN_6 51
207 #define OMAP_DMA_CMT_APE_TX_CHAN_7 52
208 #define OMAP_DMA_CMT_APE_RV_CHAN_7 53
209 #define OMAP_DMA_MMC2_TX 54
210 #define OMAP_DMA_MMC2_RX 55
211 #define OMAP_DMA_CRYPTO_DES_OUT 56
213 /* DMA channels for 24xx */
214 #define OMAP24XX_DMA_NO_DEVICE 0
215 #define OMAP24XX_DMA_XTI_DMA 1 /* S_DMA_0 */
216 #define OMAP24XX_DMA_EXT_DMAREQ0 2 /* S_DMA_1 */
217 #define OMAP24XX_DMA_EXT_DMAREQ1 3 /* S_DMA_2 */
218 #define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */
219 #define OMAP24XX_DMA_GFX 5 /* S_DMA_4 */
220 #define OMAP24XX_DMA_DSS 6 /* S_DMA_5 */
221 #define OMAP242X_DMA_VLYNQ_TX 7 /* S_DMA_6 */
222 #define OMAP24XX_DMA_EXT_DMAREQ2 7 /* S_DMA_6 */
223 #define OMAP24XX_DMA_CWT 8 /* S_DMA_7 */
224 #define OMAP24XX_DMA_AES_TX 9 /* S_DMA_8 */
225 #define OMAP24XX_DMA_AES_RX 10 /* S_DMA_9 */
226 #define OMAP24XX_DMA_DES_TX 11 /* S_DMA_10 */
227 #define OMAP24XX_DMA_DES_RX 12 /* S_DMA_11 */
228 #define OMAP24XX_DMA_SHA1MD5_RX 13 /* S_DMA_12 */
229 #define OMAP34XX_DMA_SHA2MD5_RX 13 /* S_DMA_12 */
230 #define OMAP242X_DMA_EXT_DMAREQ2 14 /* S_DMA_13 */
231 #define OMAP242X_DMA_EXT_DMAREQ3 15 /* S_DMA_14 */
232 #define OMAP242X_DMA_EXT_DMAREQ4 16 /* S_DMA_15 */
233 #define OMAP242X_DMA_EAC_AC_RD 17 /* S_DMA_16 */
234 #define OMAP242X_DMA_EAC_AC_WR 18 /* S_DMA_17 */
235 #define OMAP242X_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */
236 #define OMAP242X_DMA_EAC_MD_UL_WR 20 /* S_DMA_19 */
237 #define OMAP242X_DMA_EAC_MD_DL_RD 21 /* S_DMA_20 */
238 #define OMAP242X_DMA_EAC_MD_DL_WR 22 /* S_DMA_21 */
239 #define OMAP242X_DMA_EAC_BT_UL_RD 23 /* S_DMA_22 */
240 #define OMAP242X_DMA_EAC_BT_UL_WR 24 /* S_DMA_23 */
241 #define OMAP242X_DMA_EAC_BT_DL_RD 25 /* S_DMA_24 */
242 #define OMAP242X_DMA_EAC_BT_DL_WR 26 /* S_DMA_25 */
243 #define OMAP243X_DMA_EXT_DMAREQ3 14 /* S_DMA_13 */
244 #define OMAP24XX_DMA_SPI3_TX0 15 /* S_DMA_14 */
245 #define OMAP24XX_DMA_SPI3_RX0 16 /* S_DMA_15 */
246 #define OMAP24XX_DMA_MCBSP3_TX 17 /* S_DMA_16 */
247 #define OMAP24XX_DMA_MCBSP3_RX 18 /* S_DMA_17 */
248 #define OMAP24XX_DMA_MCBSP4_TX 19 /* S_DMA_18 */
249 #define OMAP24XX_DMA_MCBSP4_RX 20 /* S_DMA_19 */
250 #define OMAP24XX_DMA_MCBSP5_TX 21 /* S_DMA_20 */
251 #define OMAP24XX_DMA_MCBSP5_RX 22 /* S_DMA_21 */
252 #define OMAP24XX_DMA_SPI3_TX1 23 /* S_DMA_22 */
253 #define OMAP24XX_DMA_SPI3_RX1 24 /* S_DMA_23 */
254 #define OMAP243X_DMA_EXT_DMAREQ4 25 /* S_DMA_24 */
255 #define OMAP243X_DMA_EXT_DMAREQ5 26 /* S_DMA_25 */
256 #define OMAP34XX_DMA_I2C3_TX 25 /* S_DMA_24 */
257 #define OMAP34XX_DMA_I2C3_RX 26 /* S_DMA_25 */
258 #define OMAP24XX_DMA_I2C1_TX 27 /* S_DMA_26 */
259 #define OMAP24XX_DMA_I2C1_RX 28 /* S_DMA_27 */
260 #define OMAP24XX_DMA_I2C2_TX 29 /* S_DMA_28 */
261 #define OMAP24XX_DMA_I2C2_RX 30 /* S_DMA_29 */
262 #define OMAP24XX_DMA_MCBSP1_TX 31 /* S_DMA_30 */
263 #define OMAP24XX_DMA_MCBSP1_RX 32 /* S_DMA_31 */
264 #define OMAP24XX_DMA_MCBSP2_TX 33 /* S_DMA_32 */
265 #define OMAP24XX_DMA_MCBSP2_RX 34 /* S_DMA_33 */
266 #define OMAP24XX_DMA_SPI1_TX0 35 /* S_DMA_34 */
267 #define OMAP24XX_DMA_SPI1_RX0 36 /* S_DMA_35 */
268 #define OMAP24XX_DMA_SPI1_TX1 37 /* S_DMA_36 */
269 #define OMAP24XX_DMA_SPI1_RX1 38 /* S_DMA_37 */
270 #define OMAP24XX_DMA_SPI1_TX2 39 /* S_DMA_38 */
271 #define OMAP24XX_DMA_SPI1_RX2 40 /* S_DMA_39 */
272 #define OMAP24XX_DMA_SPI1_TX3 41 /* S_DMA_40 */
273 #define OMAP24XX_DMA_SPI1_RX3 42 /* S_DMA_41 */
274 #define OMAP24XX_DMA_SPI2_TX0 43 /* S_DMA_42 */
275 #define OMAP24XX_DMA_SPI2_RX0 44 /* S_DMA_43 */
276 #define OMAP24XX_DMA_SPI2_TX1 45 /* S_DMA_44 */
277 #define OMAP24XX_DMA_SPI2_RX1 46 /* S_DMA_45 */
278 #define OMAP24XX_DMA_MMC2_TX 47 /* S_DMA_46 */
279 #define OMAP24XX_DMA_MMC2_RX 48 /* S_DMA_47 */
280 #define OMAP24XX_DMA_UART1_TX 49 /* S_DMA_48 */
281 #define OMAP24XX_DMA_UART1_RX 50 /* S_DMA_49 */
282 #define OMAP24XX_DMA_UART2_TX 51 /* S_DMA_50 */
283 #define OMAP24XX_DMA_UART2_RX 52 /* S_DMA_51 */
284 #define OMAP24XX_DMA_UART3_TX 53 /* S_DMA_52 */
285 #define OMAP24XX_DMA_UART3_RX 54 /* S_DMA_53 */
286 #define OMAP24XX_DMA_USB_W2FC_TX0 55 /* S_DMA_54 */
287 #define OMAP24XX_DMA_USB_W2FC_RX0 56 /* S_DMA_55 */
288 #define OMAP24XX_DMA_USB_W2FC_TX1 57 /* S_DMA_56 */
289 #define OMAP24XX_DMA_USB_W2FC_RX1 58 /* S_DMA_57 */
290 #define OMAP24XX_DMA_USB_W2FC_TX2 59 /* S_DMA_58 */
291 #define OMAP24XX_DMA_USB_W2FC_RX2 60 /* S_DMA_59 */
292 #define OMAP24XX_DMA_MMC1_TX 61 /* S_DMA_60 */
293 #define OMAP24XX_DMA_MMC1_RX 62 /* S_DMA_61 */
294 #define OMAP24XX_DMA_MS 63 /* S_DMA_62 */
295 #define OMAP242X_DMA_EXT_DMAREQ5 64 /* S_DMA_63 */
296 #define OMAP243X_DMA_EXT_DMAREQ6 64 /* S_DMA_63 */
297 #define OMAP34XX_DMA_EXT_DMAREQ3 64 /* S_DMA_63 */
298 #define OMAP34XX_DMA_AES2_TX 65 /* S_DMA_64 */
299 #define OMAP34XX_DMA_AES2_RX 66 /* S_DMA_65 */
300 #define OMAP34XX_DMA_DES2_TX 67 /* S_DMA_66 */
301 #define OMAP34XX_DMA_DES2_RX 68 /* S_DMA_67 */
302 #define OMAP34XX_DMA_SHA1MD5_RX 69 /* S_DMA_68 */
303 #define OMAP34XX_DMA_SPI4_TX0 70 /* S_DMA_69 */
304 #define OMAP34XX_DMA_SPI4_RX0 71 /* S_DMA_70 */
305 #define OMAP34XX_DSS_DMA0 72 /* S_DMA_71 */
306 #define OMAP34XX_DSS_DMA1 73 /* S_DMA_72 */
307 #define OMAP34XX_DSS_DMA2 74 /* S_DMA_73 */
308 #define OMAP34XX_DSS_DMA3 75 /* S_DMA_74 */
309 #define OMAP34XX_DMA_MMC3_TX 77 /* S_DMA_76 */
310 #define OMAP34XX_DMA_MMC3_RX 78 /* S_DMA_77 */
311 #define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */
312 #define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */
314 /*----------------------------------------------------------------------------*/
316 /* Hardware registers for LCD DMA */
317 #define OMAP1510_DMA_LCD_BASE (0xfffedb00)
318 #define OMAP1510_DMA_LCD_CTRL (OMAP1510_DMA_LCD_BASE + 0x00)
319 #define OMAP1510_DMA_LCD_TOP_F1_L (OMAP1510_DMA_LCD_BASE + 0x02)
320 #define OMAP1510_DMA_LCD_TOP_F1_U (OMAP1510_DMA_LCD_BASE + 0x04)
321 #define OMAP1510_DMA_LCD_BOT_F1_L (OMAP1510_DMA_LCD_BASE + 0x06)
322 #define OMAP1510_DMA_LCD_BOT_F1_U (OMAP1510_DMA_LCD_BASE + 0x08)
324 #define OMAP1610_DMA_LCD_BASE (0xfffee300)
325 #define OMAP1610_DMA_LCD_CSDP (OMAP1610_DMA_LCD_BASE + 0xc0)
326 #define OMAP1610_DMA_LCD_CCR (OMAP1610_DMA_LCD_BASE + 0xc2)
327 #define OMAP1610_DMA_LCD_CTRL (OMAP1610_DMA_LCD_BASE + 0xc4)
328 #define OMAP1610_DMA_LCD_TOP_B1_L (OMAP1610_DMA_LCD_BASE + 0xc8)
329 #define OMAP1610_DMA_LCD_TOP_B1_U (OMAP1610_DMA_LCD_BASE + 0xca)
330 #define OMAP1610_DMA_LCD_BOT_B1_L (OMAP1610_DMA_LCD_BASE + 0xcc)
331 #define OMAP1610_DMA_LCD_BOT_B1_U (OMAP1610_DMA_LCD_BASE + 0xce)
332 #define OMAP1610_DMA_LCD_TOP_B2_L (OMAP1610_DMA_LCD_BASE + 0xd0)
333 #define OMAP1610_DMA_LCD_TOP_B2_U (OMAP1610_DMA_LCD_BASE + 0xd2)
334 #define OMAP1610_DMA_LCD_BOT_B2_L (OMAP1610_DMA_LCD_BASE + 0xd4)
335 #define OMAP1610_DMA_LCD_BOT_B2_U (OMAP1610_DMA_LCD_BASE + 0xd6)
336 #define OMAP1610_DMA_LCD_SRC_EI_B1 (OMAP1610_DMA_LCD_BASE + 0xd8)
337 #define OMAP1610_DMA_LCD_SRC_FI_B1_L (OMAP1610_DMA_LCD_BASE + 0xda)
338 #define OMAP1610_DMA_LCD_SRC_EN_B1 (OMAP1610_DMA_LCD_BASE + 0xe0)
339 #define OMAP1610_DMA_LCD_SRC_FN_B1 (OMAP1610_DMA_LCD_BASE + 0xe4)
340 #define OMAP1610_DMA_LCD_LCH_CTRL (OMAP1610_DMA_LCD_BASE + 0xea)
341 #define OMAP1610_DMA_LCD_SRC_FI_B1_U (OMAP1610_DMA_LCD_BASE + 0xf4)
343 #define OMAP1_DMA_TOUT_IRQ (1 << 0)
344 #define OMAP_DMA_DROP_IRQ (1 << 1)
345 #define OMAP_DMA_HALF_IRQ (1 << 2)
346 #define OMAP_DMA_FRAME_IRQ (1 << 3)
347 #define OMAP_DMA_LAST_IRQ (1 << 4)
348 #define OMAP_DMA_BLOCK_IRQ (1 << 5)
349 #define OMAP1_DMA_SYNC_IRQ (1 << 6)
350 #define OMAP2_DMA_PKT_IRQ (1 << 7)
351 #define OMAP2_DMA_TRANS_ERR_IRQ (1 << 8)
352 #define OMAP2_DMA_SECURE_ERR_IRQ (1 << 9)
353 #define OMAP2_DMA_SUPERVISOR_ERR_IRQ (1 << 10)
354 #define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11)
356 #define OMAP_DMA_DATA_TYPE_S8 0x00
357 #define OMAP_DMA_DATA_TYPE_S16 0x01
358 #define OMAP_DMA_DATA_TYPE_S32 0x02
360 #define OMAP_DMA_SYNC_ELEMENT 0x00
361 #define OMAP_DMA_SYNC_FRAME 0x01
362 #define OMAP_DMA_SYNC_BLOCK 0x02
363 #define OMAP_DMA_SYNC_PACKET 0x03
365 #define OMAP_DMA_SRC_SYNC 0x01
366 #define OMAP_DMA_DST_SYNC 0x00
368 #define OMAP_DMA_PORT_EMIFF 0x00
369 #define OMAP_DMA_PORT_EMIFS 0x01
370 #define OMAP_DMA_PORT_OCP_T1 0x02
371 #define OMAP_DMA_PORT_TIPB 0x03
372 #define OMAP_DMA_PORT_OCP_T2 0x04
373 #define OMAP_DMA_PORT_MPUI 0x05
375 #define OMAP_DMA_AMODE_CONSTANT 0x00
376 #define OMAP_DMA_AMODE_POST_INC 0x01
377 #define OMAP_DMA_AMODE_SINGLE_IDX 0x02
378 #define OMAP_DMA_AMODE_DOUBLE_IDX 0x03
380 #define DMA_DEFAULT_FIFO_DEPTH 0x10
381 #define DMA_DEFAULT_ARB_RATE 0x01
382 /* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */
383 #define DMA_THREAD_RESERVE_NORM (0x00 << 12) /* Def */
384 #define DMA_THREAD_RESERVE_ONET (0x01 << 12)
385 #define DMA_THREAD_RESERVE_TWOT (0x02 << 12)
386 #define DMA_THREAD_RESERVE_THREET (0x03 << 12)
387 #define DMA_THREAD_FIFO_NONE (0x00 << 14) /* Def */
388 #define DMA_THREAD_FIFO_75 (0x01 << 14)
389 #define DMA_THREAD_FIFO_25 (0x02 << 14)
390 #define DMA_THREAD_FIFO_50 (0x03 << 14)
393 #ifndef CONFIG_ARCH_OMAP1
394 #define OMAP_DMA_STATIC_CHAIN 0x1
395 #define OMAP_DMA_DYNAMIC_CHAIN 0x2
396 #define OMAP_DMA_CHAIN_ACTIVE 0x1
397 #define OMAP_DMA_CHAIN_INACTIVE 0x0
400 #define DMA_CH_PRIO_HIGH 0x1
401 #define DMA_CH_PRIO_LOW 0x0 /* Def */
403 /* LCD DMA block numbers */
406 OMAP_LCD_DMA_B1_BOTTOM,
408 OMAP_LCD_DMA_B2_BOTTOM
411 enum omap_dma_burst_mode {
412 OMAP_DMA_DATA_BURST_DIS = 0,
413 OMAP_DMA_DATA_BURST_4,
414 OMAP_DMA_DATA_BURST_8,
415 OMAP_DMA_DATA_BURST_16,
419 OMAP_DMA_LITTLE_ENDIAN = 0,
423 enum omap_dma_color_mode {
424 OMAP_DMA_COLOR_DIS = 0,
425 OMAP_DMA_CONSTANT_FILL,
426 OMAP_DMA_TRANSPARENT_COPY
429 enum omap_dma_write_mode {
430 OMAP_DMA_WRITE_NON_POSTED = 0,
431 OMAP_DMA_WRITE_POSTED,
432 OMAP_DMA_WRITE_LAST_NON_POSTED
435 enum omap_dma_channel_mode {
442 struct omap_dma_channel_params {
443 int data_type; /* data type 8,16,32 */
444 int elem_count; /* number of elements in a frame */
445 int frame_count; /* number of frames in a element */
447 int src_port; /* Only on OMAP1 REVISIT: Is this needed? */
448 int src_amode; /* constant, post increment, indexed,
450 unsigned long src_start; /* source address : physical */
451 int src_ei; /* source element index */
452 int src_fi; /* source frame index */
454 int dst_port; /* Only on OMAP1 REVISIT: Is this needed? */
455 int dst_amode; /* constant, post increment, indexed,
457 unsigned long dst_start; /* source address : physical */
458 int dst_ei; /* source element index */
459 int dst_fi; /* source frame index */
461 int trigger; /* trigger attached if the channel is
463 int sync_mode; /* sycn on element, frame , block or packet */
464 int src_or_dst_synch; /* source synch(1) or destination synch(0) */
466 int ie; /* interrupt enabled */
468 unsigned char read_prio;/* read priority */
469 unsigned char write_prio;/* write priority */
471 #ifndef CONFIG_ARCH_OMAP1
472 enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */
477 extern void omap_set_dma_priority(int lch, int dst_port, int priority);
478 extern int omap_request_dma(int dev_id, const char *dev_name,
479 void (*callback)(int lch, u16 ch_status, void *data),
480 void *data, int *dma_ch);
481 extern void omap_enable_dma_irq(int ch, u16 irq_bits);
482 extern void omap_disable_dma_irq(int ch, u16 irq_bits);
483 extern void omap_free_dma(int ch);
484 extern void omap_start_dma(int lch);
485 extern void omap_stop_dma(int lch);
486 extern void omap_set_dma_transfer_params(int lch, int data_type,
487 int elem_count, int frame_count,
489 int dma_trigger, int src_or_dst_synch);
490 extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
492 extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);
493 extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode);
495 extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
496 unsigned long src_start,
497 int src_ei, int src_fi);
498 extern void omap_set_dma_src_index(int lch, int eidx, int fidx);
499 extern void omap_set_dma_src_data_pack(int lch, int enable);
500 extern void omap_set_dma_src_burst_mode(int lch,
501 enum omap_dma_burst_mode burst_mode);
503 extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
504 unsigned long dest_start,
505 int dst_ei, int dst_fi);
506 extern void omap_set_dma_dest_index(int lch, int eidx, int fidx);
507 extern void omap_set_dma_dest_data_pack(int lch, int enable);
508 extern void omap_set_dma_dest_burst_mode(int lch,
509 enum omap_dma_burst_mode burst_mode);
511 extern void omap_set_dma_params(int lch,
512 struct omap_dma_channel_params *params);
514 extern void omap_dma_link_lch(int lch_head, int lch_queue);
515 extern void omap_dma_unlink_lch(int lch_head, int lch_queue);
517 extern int omap_set_dma_callback(int lch,
518 void (*callback)(int lch, u16 ch_status, void *data),
520 extern dma_addr_t omap_get_dma_src_pos(int lch);
521 extern dma_addr_t omap_get_dma_dst_pos(int lch);
522 extern void omap_clear_dma(int lch);
523 extern int omap_get_dma_active_status(int lch);
524 extern int omap_dma_running(void);
525 extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,
527 extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
528 unsigned char write_prio);
529 extern void omap_set_dma_dst_endian_type(int lch, enum end_type etype);
530 extern void omap_set_dma_src_endian_type(int lch, enum end_type etype);
531 extern int omap_get_dma_index(int lch, int *ei, int *fi);
534 #ifndef CONFIG_ARCH_OMAP1
535 extern int omap_request_dma_chain(int dev_id, const char *dev_name,
536 void (*callback) (int lch, u16 ch_status,
538 int *chain_id, int no_of_chans,
540 struct omap_dma_channel_params params);
541 extern int omap_free_dma_chain(int chain_id);
542 extern int omap_dma_chain_a_transfer(int chain_id, int src_start,
543 int dest_start, int elem_count,
544 int frame_count, void *callbk_data);
545 extern int omap_start_dma_chain_transfers(int chain_id);
546 extern int omap_stop_dma_chain_transfers(int chain_id);
547 extern int omap_get_dma_chain_index(int chain_id, int *ei, int *fi);
548 extern int omap_get_dma_chain_dst_pos(int chain_id);
549 extern int omap_get_dma_chain_src_pos(int chain_id);
551 extern int omap_modify_dma_chain_params(int chain_id,
552 struct omap_dma_channel_params params);
553 extern int omap_dma_chain_status(int chain_id);
556 /* LCD DMA functions */
557 extern int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
559 extern void omap_free_lcd_dma(void);
560 extern void omap_setup_lcd_dma(void);
561 extern void omap_enable_lcd_dma(void);
562 extern void omap_stop_lcd_dma(void);
563 extern void omap_set_lcd_dma_ext_controller(int external);
564 extern void omap_set_lcd_dma_single_transfer(int single);
565 extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
567 extern void omap_set_lcd_dma_b1_rotation(int rotate);
568 extern void omap_set_lcd_dma_b1_vxres(unsigned long vxres);
569 extern void omap_set_lcd_dma_b1_mirror(int mirror);
570 extern void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale);
572 #endif /* __ASM_ARCH_DMA_H */
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