arch/arm/plat-omap/dmtimer.c

   1 /*
   2  * linux/arch/arm/plat-omap/dmtimer.c
   3  *
   4  * OMAP Dual-Mode Timers
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * OMAP2 support by Juha Yrjola
   8  * API improvements and OMAP2 clock framework support by Timo Teras
   9  *
  10  * Copyright (C) 2009 Texas Instruments
  11  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  12  *
  13  * This program is free software; you can redistribute it and/or modify it
  14  * under the terms of the GNU General Public License as published by the
  15  * Free Software Foundation; either version 2 of the License, or (at your
  16  * option) any later version.
  17  *
  18  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  19  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  20  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  21  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  22  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  23  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  25  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  *
  27  * You should have received a copy of the  GNU General Public License along
  28  * with this program; if not, write  to the Free Software Foundation, Inc.,
  29  * 675 Mass Ave, Cambridge, MA 02139, USA.
  30  */
  31
  32 #include <linux/init.h>
  33 #include <linux/spinlock.h>
  34 #include <linux/errno.h>
  35 #include <linux/list.h>
  36 #include <linux/clk.h>
  37 #include <linux/delay.h>
  38 #include <linux/io.h>
  39 #include <linux/module.h>
  40 #include <mach/hardware.h>
  41 #include <plat/dmtimer.h>
  42 #include <mach/irqs.h>
  43
  44 /* register offsets */
  45 #define _OMAP_TIMER_ID_OFFSET           0x00
  46 #define _OMAP_TIMER_OCP_CFG_OFFSET      0x10
  47 #define _OMAP_TIMER_SYS_STAT_OFFSET     0x14
  48 #define _OMAP_TIMER_STAT_OFFSET         0x18
  49 #define _OMAP_TIMER_INT_EN_OFFSET       0x1c
  50 #define _OMAP_TIMER_WAKEUP_EN_OFFSET    0x20
  51 #define _OMAP_TIMER_CTRL_OFFSET         0x24
  52 #define         OMAP_TIMER_CTRL_GPOCFG          (1 << 14)
  53 #define         OMAP_TIMER_CTRL_CAPTMODE        (1 << 13)
  54 #define         OMAP_TIMER_CTRL_PT              (1 << 12)
  55 #define         OMAP_TIMER_CTRL_TCM_LOWTOHIGH   (0x1 << 8)
  56 #define         OMAP_TIMER_CTRL_TCM_HIGHTOLOW   (0x2 << 8)
  57 #define         OMAP_TIMER_CTRL_TCM_BOTHEDGES   (0x3 << 8)
  58 #define         OMAP_TIMER_CTRL_SCPWM           (1 << 7)
  59 #define         OMAP_TIMER_CTRL_CE              (1 << 6) /* compare enable */
  60 #define         OMAP_TIMER_CTRL_PRE             (1 << 5) /* prescaler enable */
  61 #define         OMAP_TIMER_CTRL_PTV_SHIFT       2 /* prescaler value shift */
  62 #define         OMAP_TIMER_CTRL_POSTED          (1 << 2)
  63 #define         OMAP_TIMER_CTRL_AR              (1 << 1) /* auto-reload enable */
  64 #define         OMAP_TIMER_CTRL_ST              (1 << 0) /* start timer */
  65 #define _OMAP_TIMER_COUNTER_OFFSET      0x28
  66 #define _OMAP_TIMER_LOAD_OFFSET         0x2c
  67 #define _OMAP_TIMER_TRIGGER_OFFSET      0x30
  68 #define _OMAP_TIMER_WRITE_PEND_OFFSET   0x34
  69 #define         WP_NONE                 0       /* no write pending bit */
  70 #define         WP_TCLR                 (1 << 0)
  71 #define         WP_TCRR                 (1 << 1)
  72 #define         WP_TLDR                 (1 << 2)
  73 #define         WP_TTGR                 (1 << 3)
  74 #define         WP_TMAR                 (1 << 4)
  75 #define         WP_TPIR                 (1 << 5)
  76 #define         WP_TNIR                 (1 << 6)
  77 #define         WP_TCVR                 (1 << 7)
  78 #define         WP_TOCR                 (1 << 8)
  79 #define         WP_TOWR                 (1 << 9)
  80 #define _OMAP_TIMER_MATCH_OFFSET        0x38
  81 #define _OMAP_TIMER_CAPTURE_OFFSET      0x3c
  82 #define _OMAP_TIMER_IF_CTRL_OFFSET      0x40
  83 #define _OMAP_TIMER_CAPTURE2_OFFSET             0x44    /* TCAR2, 34xx only */
  84 #define _OMAP_TIMER_TICK_POS_OFFSET             0x48    /* TPIR, 34xx only */
  85 #define _OMAP_TIMER_TICK_NEG_OFFSET             0x4c    /* TNIR, 34xx only */
  86 #define _OMAP_TIMER_TICK_COUNT_OFFSET           0x50    /* TCVR, 34xx only */
  87 #define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET    0x54    /* TOCR, 34xx only */
  88 #define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET  0x58    /* TOWR, 34xx only */
  89
  90 /* register offsets with the write pending bit encoded */
  91 #define WPSHIFT                                 16
  92
  93 #define OMAP_TIMER_ID_REG                       (_OMAP_TIMER_ID_OFFSET \
  94                                                         | (WP_NONE << WPSHIFT))
  95
  96 #define OMAP_TIMER_OCP_CFG_REG                  (_OMAP_TIMER_OCP_CFG_OFFSET \
  97                                                         | (WP_NONE << WPSHIFT))
  98
  99 #define OMAP_TIMER_SYS_STAT_REG                 (_OMAP_TIMER_SYS_STAT_OFFSET \
 100                                                         | (WP_NONE << WPSHIFT))
 101
 102 #define OMAP_TIMER_STAT_REG                     (_OMAP_TIMER_STAT_OFFSET \
 103                                                         | (WP_NONE << WPSHIFT))
 104
 105 #define OMAP_TIMER_INT_EN_REG                   (_OMAP_TIMER_INT_EN_OFFSET \
 106                                                         | (WP_NONE << WPSHIFT))
 107
 108 #define OMAP_TIMER_WAKEUP_EN_REG                (_OMAP_TIMER_WAKEUP_EN_OFFSET \
 109                                                         | (WP_NONE << WPSHIFT))
 110
 111 #define OMAP_TIMER_CTRL_REG                     (_OMAP_TIMER_CTRL_OFFSET \
 112                                                         | (WP_TCLR << WPSHIFT))
 113
 114 #define OMAP_TIMER_COUNTER_REG                  (_OMAP_TIMER_COUNTER_OFFSET \
 115                                                         | (WP_TCRR << WPSHIFT))
 116
 117 #define OMAP_TIMER_LOAD_REG                     (_OMAP_TIMER_LOAD_OFFSET \
 118                                                         | (WP_TLDR << WPSHIFT))
 119
 120 #define OMAP_TIMER_TRIGGER_REG                  (_OMAP_TIMER_TRIGGER_OFFSET \
 121                                                         | (WP_TTGR << WPSHIFT))
 122
 123 #define OMAP_TIMER_WRITE_PEND_REG               (_OMAP_TIMER_WRITE_PEND_OFFSET \
 124                                                         | (WP_NONE << WPSHIFT))
 125
 126 #define OMAP_TIMER_MATCH_REG                    (_OMAP_TIMER_MATCH_OFFSET \
 127                                                         | (WP_TMAR << WPSHIFT))
 128
 129 #define OMAP_TIMER_CAPTURE_REG                  (_OMAP_TIMER_CAPTURE_OFFSET \
 130                                                         | (WP_NONE << WPSHIFT))
 131
 132 #define OMAP_TIMER_IF_CTRL_REG                  (_OMAP_TIMER_IF_CTRL_OFFSET \
 133                                                         | (WP_NONE << WPSHIFT))
 134
 135 #define OMAP_TIMER_CAPTURE2_REG                 (_OMAP_TIMER_CAPTURE2_OFFSET \
 136                                                         | (WP_NONE << WPSHIFT))
 137
 138 #define OMAP_TIMER_TICK_POS_REG                 (_OMAP_TIMER_TICK_POS_OFFSET \
 139                                                         | (WP_TPIR << WPSHIFT))
 140
 141 #define OMAP_TIMER_TICK_NEG_REG                 (_OMAP_TIMER_TICK_NEG_OFFSET \
 142                                                         | (WP_TNIR << WPSHIFT))
 143
 144 #define OMAP_TIMER_TICK_COUNT_REG               (_OMAP_TIMER_TICK_COUNT_OFFSET \
 145                                                         | (WP_TCVR << WPSHIFT))
 146
 147 #define OMAP_TIMER_TICK_INT_MASK_SET_REG                                \
 148                 (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
 149
 150 #define OMAP_TIMER_TICK_INT_MASK_COUNT_REG                              \
 151                 (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
 152
 153 struct omap_dm_timer {
 154         unsigned long phys_base;
 155         int irq;
 156 #ifdef CONFIG_ARCH_OMAP2PLUS
 157         struct clk *iclk, *fclk;
 158 #endif
 159         void __iomem *io_base;
 160         unsigned reserved:1;
 161         unsigned enabled:1;
 162         unsigned posted:1;
 163 };
 164
 165 static int dm_timer_count;
 166
 167 #ifdef CONFIG_ARCH_OMAP1
 168 static struct omap_dm_timer omap1_dm_timers[] = {
 169         { .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 },
 170         { .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 },
 171         { .phys_base = 0xfffb2400, .irq = INT_1610_GPTIMER3 },
 172         { .phys_base = 0xfffb2c00, .irq = INT_1610_GPTIMER4 },
 173         { .phys_base = 0xfffb3400, .irq = INT_1610_GPTIMER5 },
 174         { .phys_base = 0xfffb3c00, .irq = INT_1610_GPTIMER6 },
 175         { .phys_base = 0xfffb7400, .irq = INT_1610_GPTIMER7 },
 176         { .phys_base = 0xfffbd400, .irq = INT_1610_GPTIMER8 },
 177 };
 178
 179 static const int omap1_dm_timer_count = ARRAY_SIZE(omap1_dm_timers);
 180
 181 #else
 182 #define omap1_dm_timers                 NULL
 183 #define omap1_dm_timer_count            0
 184 #endif  /* CONFIG_ARCH_OMAP1 */
 185
 186 #ifdef CONFIG_ARCH_OMAP2
 187 static struct omap_dm_timer omap2_dm_timers[] = {
 188         { .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 },
 189         { .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 },
 190         { .phys_base = 0x48078000, .irq = INT_24XX_GPTIMER3 },
 191         { .phys_base = 0x4807a000, .irq = INT_24XX_GPTIMER4 },
 192         { .phys_base = 0x4807c000, .irq = INT_24XX_GPTIMER5 },
 193         { .phys_base = 0x4807e000, .irq = INT_24XX_GPTIMER6 },
 194         { .phys_base = 0x48080000, .irq = INT_24XX_GPTIMER7 },
 195         { .phys_base = 0x48082000, .irq = INT_24XX_GPTIMER8 },
 196         { .phys_base = 0x48084000, .irq = INT_24XX_GPTIMER9 },
 197         { .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 },
 198         { .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 },
 199         { .phys_base = 0x4808a000, .irq = INT_24XX_GPTIMER12 },
 200 };
 201
 202 static const char *omap2_dm_source_names[] __initdata = {
 203         "sys_ck",
 204         "func_32k_ck",
 205         "alt_ck",
 206         NULL
 207 };
 208
 209 static struct clk *omap2_dm_source_clocks[3];
 210 static const int omap2_dm_timer_count = ARRAY_SIZE(omap2_dm_timers);
 211
 212 #else
 213 #define omap2_dm_timers                 NULL
 214 #define omap2_dm_timer_count            0
 215 #define omap2_dm_source_names           NULL
 216 #define omap2_dm_source_clocks          NULL
 217 #endif  /* CONFIG_ARCH_OMAP2 */
 218
 219 #ifdef CONFIG_ARCH_OMAP3
 220 static struct omap_dm_timer omap3_dm_timers[] = {
 221         { .phys_base = 0x48318000, .irq = INT_24XX_GPTIMER1 },
 222         { .phys_base = 0x49032000, .irq = INT_24XX_GPTIMER2 },
 223         { .phys_base = 0x49034000, .irq = INT_24XX_GPTIMER3 },
 224         { .phys_base = 0x49036000, .irq = INT_24XX_GPTIMER4 },
 225         { .phys_base = 0x49038000, .irq = INT_24XX_GPTIMER5 },
 226         { .phys_base = 0x4903A000, .irq = INT_24XX_GPTIMER6 },
 227         { .phys_base = 0x4903C000, .irq = INT_24XX_GPTIMER7 },
 228         { .phys_base = 0x4903E000, .irq = INT_24XX_GPTIMER8 },
 229         { .phys_base = 0x49040000, .irq = INT_24XX_GPTIMER9 },
 230         { .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 },
 231         { .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 },
 232         { .phys_base = 0x48304000, .irq = INT_34XX_GPT12_IRQ },
 233 };
 234
 235 static const char *omap3_dm_source_names[] __initdata = {
 236         "sys_ck",
 237         "omap_32k_fck",
 238         NULL
 239 };
 240
 241 static struct clk *omap3_dm_source_clocks[2];
 242 static const int omap3_dm_timer_count = ARRAY_SIZE(omap3_dm_timers);
 243
 244 #else
 245 #define omap3_dm_timers                 NULL
 246 #define omap3_dm_timer_count            0
 247 #define omap3_dm_source_names           NULL
 248 #define omap3_dm_source_clocks          NULL
 249 #endif  /* CONFIG_ARCH_OMAP3 */
 250
 251 #ifdef CONFIG_ARCH_OMAP4
 252 static struct omap_dm_timer omap4_dm_timers[] = {
 253         { .phys_base = 0x4a318000, .irq = OMAP44XX_IRQ_GPT1 },
 254         { .phys_base = 0x48032000, .irq = OMAP44XX_IRQ_GPT2 },
 255         { .phys_base = 0x48034000, .irq = OMAP44XX_IRQ_GPT3 },
 256         { .phys_base = 0x48036000, .irq = OMAP44XX_IRQ_GPT4 },
 257         { .phys_base = 0x40138000, .irq = OMAP44XX_IRQ_GPT5 },
 258         { .phys_base = 0x4013a000, .irq = OMAP44XX_IRQ_GPT6 },
 259         { .phys_base = 0x4013a000, .irq = OMAP44XX_IRQ_GPT7 },
 260         { .phys_base = 0x4013e000, .irq = OMAP44XX_IRQ_GPT8 },
 261         { .phys_base = 0x4803e000, .irq = OMAP44XX_IRQ_GPT9 },
 262         { .phys_base = 0x48086000, .irq = OMAP44XX_IRQ_GPT10 },
 263         { .phys_base = 0x48088000, .irq = OMAP44XX_IRQ_GPT11 },
 264         { .phys_base = 0x4a320000, .irq = OMAP44XX_IRQ_GPT12 },
 265 };
 266 static const char *omap4_dm_source_names[] __initdata = {
 267         "sys_clkin_ck",
 268         "sys_32k_ck",
 269         NULL
 270 };
 271 static struct clk *omap4_dm_source_clocks[2];
 272 static const int omap4_dm_timer_count = ARRAY_SIZE(omap4_dm_timers);
 273
 274 #else
 275 #define omap4_dm_timers                 NULL
 276 #define omap4_dm_timer_count            0
 277 #define omap4_dm_source_names           NULL
 278 #define omap4_dm_source_clocks          NULL
 279 #endif  /* CONFIG_ARCH_OMAP4 */
 280
 281 static struct omap_dm_timer *dm_timers;
 282 static const char **dm_source_names;
 283 static struct clk **dm_source_clocks;
 284
 285 static spinlock_t dm_timer_lock;
 286
 287 /*
 288  * Reads timer registers in posted and non-posted mode. The posted mode bit
 289  * is encoded in reg. Note that in posted mode write pending bit must be
 290  * checked. Otherwise a read of a non completed write will produce an error.
 291  */
 292 static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
 293 {
 294         if (timer->posted)
 295                 while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
 296                                 & (reg >> WPSHIFT))
 297                         cpu_relax();
 298         return readl(timer->io_base + (reg & 0xff));
 299 }
 300
 301 /*
 302  * Writes timer registers in posted and non-posted mode. The posted mode bit
 303  * is encoded in reg. Note that in posted mode the write pending bit must be
 304  * checked. Otherwise a write on a register which has a pending write will be
 305  * lost.
 306  */
 307 static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
 308                                                 u32 value)
 309 {
 310         if (timer->posted)
 311                 while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
 312                                 & (reg >> WPSHIFT))
 313                         cpu_relax();
 314         writel(value, timer->io_base + (reg & 0xff));
 315 }
 316
 317 static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
 318 {
 319         int c;
 320
 321         c = 0;
 322         while (!(omap_dm_timer_read_reg(timer, OMAP_TIMER_SYS_STAT_REG) & 1)) {
 323                 c++;
 324                 if (c > 100000) {
 325                         printk(KERN_ERR "Timer failed to reset\n");
 326                         return;
 327                 }
 328         }
 329 }
 330
 331 static void omap_dm_timer_reset(struct omap_dm_timer *timer)
 332 {
 333         u32 l;
 334
 335         if (!cpu_class_is_omap2() || timer != &dm_timers[0]) {
 336                 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
 337                 omap_dm_timer_wait_for_reset(timer);
 338         }
 339         omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
 340
 341         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG);
 342         l |= 0x02 << 3;  /* Set to smart-idle mode */
 343         l |= 0x2 << 8;   /* Set clock activity to perserve f-clock on idle */
 344
 345         /*
 346          * Enable wake-up on OMAP2 CPUs.
 347          */
 348         if (cpu_class_is_omap2())
 349                 l |= 1 << 2;
 350         omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l);
 351
 352         /* Match hardware reset default of posted mode */
 353         omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
 354                         OMAP_TIMER_CTRL_POSTED);
 355         timer->posted = 1;
 356 }
 357
 358 static void omap_dm_timer_prepare(struct omap_dm_timer *timer)
 359 {
 360         omap_dm_timer_enable(timer);
 361         omap_dm_timer_reset(timer);
 362 }
 363
 364 struct omap_dm_timer *omap_dm_timer_request(void)
 365 {
 366         struct omap_dm_timer *timer = NULL;
 367         unsigned long flags;
 368         int i;
 369
 370         spin_lock_irqsave(&dm_timer_lock, flags);
 371         for (i = 0; i < dm_timer_count; i++) {
 372                 if (dm_timers[i].reserved)
 373                         continue;
 374
 375                 timer = &dm_timers[i];
 376                 timer->reserved = 1;
 377                 break;
 378         }
 379         spin_unlock_irqrestore(&dm_timer_lock, flags);
 380
 381         if (timer != NULL)
 382                 omap_dm_timer_prepare(timer);
 383
 384         return timer;
 385 }
 386 EXPORT_SYMBOL_GPL(omap_dm_timer_request);
 387
 388 struct omap_dm_timer *omap_dm_timer_request_specific(int id)
 389 {
 390         struct omap_dm_timer *timer;
 391         unsigned long flags;
 392
 393         spin_lock_irqsave(&dm_timer_lock, flags);
 394         if (id <= 0 || id > dm_timer_count || dm_timers[id-1].reserved) {
 395                 spin_unlock_irqrestore(&dm_timer_lock, flags);
 396                 printk("BUG: warning at %s:%d/%s(): unable to get timer %d\n",
 397                        __FILE__, __LINE__, __func__, id);
 398                 dump_stack();
 399                 return NULL;
 400         }
 401
 402         timer = &dm_timers[id-1];
 403         timer->reserved = 1;
 404         spin_unlock_irqrestore(&dm_timer_lock, flags);
 405
 406         omap_dm_timer_prepare(timer);
 407
 408         return timer;
 409 }
 410 EXPORT_SYMBOL_GPL(omap_dm_timer_request_specific);
 411
 412 void omap_dm_timer_free(struct omap_dm_timer *timer)
 413 {
 414         omap_dm_timer_enable(timer);
 415         omap_dm_timer_reset(timer);
 416         omap_dm_timer_disable(timer);
 417
 418         WARN_ON(!timer->reserved);
 419         timer->reserved = 0;
 420 }
 421 EXPORT_SYMBOL_GPL(omap_dm_timer_free);
 422
 423 void omap_dm_timer_enable(struct omap_dm_timer *timer)
 424 {
 425         if (timer->enabled)
 426                 return;
 427
 428 #ifdef CONFIG_ARCH_OMAP2PLUS
 429         if (cpu_class_is_omap2()) {
 430                 clk_enable(timer->fclk);
 431                 clk_enable(timer->iclk);
 432         }
 433 #endif
 434
 435         timer->enabled = 1;
 436 }
 437 EXPORT_SYMBOL_GPL(omap_dm_timer_enable);
 438
 439 void omap_dm_timer_disable(struct omap_dm_timer *timer)
 440 {
 441         if (!timer->enabled)
 442                 return;
 443
 444 #ifdef CONFIG_ARCH_OMAP2PLUS
 445         if (cpu_class_is_omap2()) {
 446                 clk_disable(timer->iclk);
 447                 clk_disable(timer->fclk);
 448         }
 449 #endif
 450
 451         timer->enabled = 0;
 452 }
 453 EXPORT_SYMBOL_GPL(omap_dm_timer_disable);
 454
 455 int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
 456 {
 457         return timer->irq;
 458 }
 459 EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq);
 460
 461 #if defined(CONFIG_ARCH_OMAP1)
 462
 463 /**
 464  * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR
 465  * @inputmask: current value of idlect mask
 466  */
 467 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
 468 {
 469         int i;
 470
 471         /* If ARMXOR cannot be idled this function call is unnecessary */
 472         if (!(inputmask & (1 << 1)))
 473                 return inputmask;
 474
 475         /* If any active timer is using ARMXOR return modified mask */
 476         for (i = 0; i < dm_timer_count; i++) {
 477                 u32 l;
 478
 479                 l = omap_dm_timer_read_reg(&dm_timers[i], OMAP_TIMER_CTRL_REG);
 480                 if (l & OMAP_TIMER_CTRL_ST) {
 481                         if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0)
 482                                 inputmask &= ~(1 << 1);
 483                         else
 484                                 inputmask &= ~(1 << 2);
 485                 }
 486         }
 487
 488         return inputmask;
 489 }
 490 EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask);
 491
 492 #else
 493
 494 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
 495 {
 496         return timer->fclk;
 497 }
 498 EXPORT_SYMBOL_GPL(omap_dm_timer_get_fclk);
 499
 500 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
 501 {
 502         BUG();
 503
 504         return 0;
 505 }
 506 EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask);
 507
 508 #endif
 509
 510 void omap_dm_timer_trigger(struct omap_dm_timer *timer)
 511 {
 512         omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
 513 }
 514 EXPORT_SYMBOL_GPL(omap_dm_timer_trigger);
 515
 516 void omap_dm_timer_start(struct omap_dm_timer *timer)
 517 {
 518         u32 l;
 519
 520         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 521         if (!(l & OMAP_TIMER_CTRL_ST)) {
 522                 l |= OMAP_TIMER_CTRL_ST;
 523                 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 524         }
 525 }
 526 EXPORT_SYMBOL_GPL(omap_dm_timer_start);
 527
 528 void omap_dm_timer_stop(struct omap_dm_timer *timer)
 529 {
 530         u32 l;
 531
 532         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 533         if (l & OMAP_TIMER_CTRL_ST) {
 534                 l &= ~0x1;
 535                 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 536 #ifdef CONFIG_ARCH_OMAP2PLUS
 537                 /* Readback to make sure write has completed */
 538                 omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 539                  /*
 540                   * Wait for functional clock period x 3.5 to make sure that
 541                   * timer is stopped
 542                   */
 543                 udelay(3500000 / clk_get_rate(timer->fclk) + 1);
 544                 /* Ack possibly pending interrupt */
 545                 omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG,
 546                                 OMAP_TIMER_INT_OVERFLOW);
 547 #endif
 548         }
 549 }
 550 EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
 551
 552 #ifdef CONFIG_ARCH_OMAP1
 553
 554 int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
 555 {
 556         int n = (timer - dm_timers) << 1;
 557         u32 l;
 558
 559         l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n);
 560         l |= source << n;
 561         omap_writel(l, MOD_CONF_CTRL_1);
 562
 563         return 0;
 564 }
 565 EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
 566
 567 #else
 568
 569 int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
 570 {
 571         int ret = -EINVAL;
 572
 573         if (source < 0 || source >= 3)
 574                 return -EINVAL;
 575
 576         clk_disable(timer->fclk);
 577         ret = clk_set_parent(timer->fclk, dm_source_clocks[source]);
 578         clk_enable(timer->fclk);
 579
 580         /*
 581          * When the functional clock disappears, too quick writes seem
 582          * to cause an abort. XXX Is this still necessary?
 583          */
 584         __delay(150000);
 585
 586         return ret;
 587 }
 588 EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
 589
 590 #endif
 591
 592 void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
 593                             unsigned int load)
 594 {
 595         u32 l;
 596
 597         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 598         if (autoreload)
 599                 l |= OMAP_TIMER_CTRL_AR;
 600         else
 601                 l &= ~OMAP_TIMER_CTRL_AR;
 602         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 603         omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
 604
 605         omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
 606 }
 607 EXPORT_SYMBOL_GPL(omap_dm_timer_set_load);
 608
 609 /* Optimized set_load which removes costly spin wait in timer_start */
 610 void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
 611                             unsigned int load)
 612 {
 613         u32 l;
 614
 615         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 616         if (autoreload) {
 617                 l |= OMAP_TIMER_CTRL_AR;
 618                 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
 619         } else {
 620                 l &= ~OMAP_TIMER_CTRL_AR;
 621         }
 622         l |= OMAP_TIMER_CTRL_ST;
 623
 624         omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, load);
 625         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 626 }
 627 EXPORT_SYMBOL_GPL(omap_dm_timer_set_load_start);
 628
 629 void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
 630                              unsigned int match)
 631 {
 632         u32 l;
 633
 634         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 635         if (enable)
 636                 l |= OMAP_TIMER_CTRL_CE;
 637         else
 638                 l &= ~OMAP_TIMER_CTRL_CE;
 639         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 640         omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
 641 }
 642 EXPORT_SYMBOL_GPL(omap_dm_timer_set_match);
 643
 644 void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
 645                            int toggle, int trigger)
 646 {
 647         u32 l;
 648
 649         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 650         l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM |
 651                OMAP_TIMER_CTRL_PT | (0x03 << 10));
 652         if (def_on)
 653                 l |= OMAP_TIMER_CTRL_SCPWM;
 654         if (toggle)
 655                 l |= OMAP_TIMER_CTRL_PT;
 656         l |= trigger << 10;
 657         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 658 }
 659 EXPORT_SYMBOL_GPL(omap_dm_timer_set_pwm);
 660
 661 void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
 662 {
 663         u32 l;
 664
 665         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 666         l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2));
 667         if (prescaler >= 0x00 && prescaler <= 0x07) {
 668                 l |= OMAP_TIMER_CTRL_PRE;
 669                 l |= prescaler << 2;
 670         }
 671         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 672 }
 673 EXPORT_SYMBOL_GPL(omap_dm_timer_set_prescaler);
 674
 675 void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
 676                                   unsigned int value)
 677 {
 678         omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, value);
 679         omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, value);
 680 }
 681 EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable);
 682
 683 unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
 684 {
 685         unsigned int l;
 686
 687         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_STAT_REG);
 688
 689         return l;
 690 }
 691 EXPORT_SYMBOL_GPL(omap_dm_timer_read_status);
 692
 693 void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
 694 {
 695         omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG, value);
 696 }
 697 EXPORT_SYMBOL_GPL(omap_dm_timer_write_status);
 698
 699 unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
 700 {
 701         unsigned int l;
 702
 703         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_COUNTER_REG);
 704
 705         return l;
 706 }
 707 EXPORT_SYMBOL_GPL(omap_dm_timer_read_counter);
 708
 709 void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
 710 {
 711         omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value);
 712 }
 713 EXPORT_SYMBOL_GPL(omap_dm_timer_write_counter);
 714
 715 int omap_dm_timers_active(void)
 716 {
 717         int i;
 718
 719         for (i = 0; i < dm_timer_count; i++) {
 720                 struct omap_dm_timer *timer;
 721
 722                 timer = &dm_timers[i];
 723
 724                 if (!timer->enabled)
 725                         continue;
 726
 727                 if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) &
 728                     OMAP_TIMER_CTRL_ST) {
 729                         return 1;
 730                 }
 731         }
 732         return 0;
 733 }
 734 EXPORT_SYMBOL_GPL(omap_dm_timers_active);
 735
 736 int __init omap_dm_timer_init(void)
 737 {
 738         struct omap_dm_timer *timer;
 739         int i, map_size = SZ_8K;        /* Module 4KB + L4 4KB except on omap1 */
 740
 741         if (!(cpu_is_omap16xx() || cpu_class_is_omap2()))
 742                 return -ENODEV;
 743
 744         spin_lock_init(&dm_timer_lock);
 745
 746         if (cpu_class_is_omap1()) {
 747                 dm_timers = omap1_dm_timers;
 748                 dm_timer_count = omap1_dm_timer_count;
 749                 map_size = SZ_2K;
 750         } else if (cpu_is_omap24xx()) {
 751                 dm_timers = omap2_dm_timers;
 752                 dm_timer_count = omap2_dm_timer_count;
 753                 dm_source_names = omap2_dm_source_names;
 754                 dm_source_clocks = omap2_dm_source_clocks;
 755         } else if (cpu_is_omap34xx()) {
 756                 dm_timers = omap3_dm_timers;
 757                 dm_timer_count = omap3_dm_timer_count;
 758                 dm_source_names = omap3_dm_source_names;
 759                 dm_source_clocks = omap3_dm_source_clocks;
 760         } else if (cpu_is_omap44xx()) {
 761                 dm_timers = omap4_dm_timers;
 762                 dm_timer_count = omap4_dm_timer_count;
 763                 dm_source_names = omap4_dm_source_names;
 764                 dm_source_clocks = omap4_dm_source_clocks;
 765         }
 766
 767         if (cpu_class_is_omap2())
 768                 for (i = 0; dm_source_names[i] != NULL; i++)
 769                         dm_source_clocks[i] = clk_get(NULL, dm_source_names[i]);
 770
 771         if (cpu_is_omap243x())
 772                 dm_timers[0].phys_base = 0x49018000;
 773
 774         for (i = 0; i < dm_timer_count; i++) {
 775                 timer = &dm_timers[i];
 776
 777                 /* Static mapping, never released */
 778                 timer->io_base = ioremap(timer->phys_base, map_size);
 779                 BUG_ON(!timer->io_base);
 780
 781 #ifdef CONFIG_ARCH_OMAP2PLUS
 782                 if (cpu_class_is_omap2()) {
 783                         char clk_name[16];
 784                         sprintf(clk_name, "gpt%d_ick", i + 1);
 785                         timer->iclk = clk_get(NULL, clk_name);
 786                         sprintf(clk_name, "gpt%d_fck", i + 1);
 787                         timer->fclk = clk_get(NULL, clk_name);
 788                 }
 789 #endif
 790         }
 791
 792         return 0;
 793 }